WO2005031955A1

WO2005031955A1 - A switch mode power supply

Info

Publication number: WO2005031955A1
Application number: PCT/IB2004/051695
Authority: WO
Inventors: Franciscus A. C. M. Schoofs; Johan C. Halberstadt
Original assignee: Koninklijke Philips Electronics NV
Current assignee: Koninklijke Philips NV
Priority date: 2003-09-25
Filing date: 2004-09-06
Publication date: 2005-04-07
Anticipated expiration: 2006-03-25

Abstract

A current sensing circuit senses the momentary varying current (I1) flowing through the first impedance (Rds-on), and a second current (Is) which is related to the varying momentary current (I1). A gain stage (GS) corrects the amplitude of the momentary information (MI), which represents the momentary varying current (I1), with a correction factor (CS) to obtain corrected momentary information (CMI). The correction factor (CS) is obtained by integrating (INT) the difference of the corrected momentary information (CMI) and the sensed reference information (SAI) representing the second current (Is). Due to the integration, the disturbances of the sensed currents decrease.

Description

A switch mode power supply

The invention relates to a current sensing circuit, a current-controlled switched mode power supply, an integrated circuit, and a consumer electronics apparatus.

The integrated VR controller of Semtech, commercially available under type designation SC2433, operates with current-mode control. This controller is able to operate several down-converters in parallel. The on-times of the different down-converters are shifted with respect to each other such that each of them supplies current to the load during periods in time shifted with respect to each other. This minimizes the ripple of the output voltage. The current in the inductors is sensed with a single sense resistor in the 12V input line of the VRM. When no overlap of the phases of the different down-converters occurs, the single sense resistor provides information of the current flowing during the successive phases. This provides an inherently good load sharing and over-current protection. Each of the down converters comprises a control FET and a sink FET of which the main current paths are arranged in series to receive a DC-input voltage. An inductor is connected between the junction of the main current paths and the output load. The control FET is arranged between the DC-input voltage and the inductor. The use of a single current sense resistor in the power supply input line allows for an accurate measurement of the value of the current in the input line. However, the shape of the current in the input line shows very steep and large steps when the control FETs are switched. The parasitic inductance of the sense resistor introduces error voltages which are difficult to filter. In addition, the relatively long distance of the wiring of the drains of the control FETs to this single sense resistor introduces large parasitic inductances, which causes a high amount of ringing. These effects will have severe consequences for the performance; they cause e.g. an inaccurate control of the power converter leading to disturbances of the output voltage or they restrict the switching frequency. It is an object of the invention to provide an accurate momentary current sensing. A first aspect of the invention provides a current sensing circuit as claimed in claim 1. A second aspect of the invention provides a current-controlled switched mode power supply as claimed in claim 10. A third aspect of the invention provides an integrated circuit as claimed in claim 21. A fourth aspect of the invention provides an electronics apparatus as claimed in claim 22. A fifth aspect of the invention provides an electronics apparatus as claimed in claim 23. Advantageous embodiments in accordance with the invention are defined in the dependent claims. The current sensing circuit in accordance with the first aspect of the invention has to supply an accurate sense signal representing a varying momentary current. If the varying momentary current is sensed as a voltage across a sense resistor, the sense voltage usually is inaccurate. This may be caused by the initial inaccuracy or temperature dependency of the sense resistor itself. This is e.g. the case when the RDSon of a MOST is used as sense resistor. Furthermore, the sense resistor has a parasitic behavior which causes the sense voltage across the sense resistor to deviate from the current through the sense resistor, even if the nominal value of the sense resistor is very accurate. This is true in particular if a large, rapidly varying current has to be sensed, such as, for example, in switched mode power converters. Often, the sense resistor should have a low resistance value to prevent disturbance of the operation of the circuit of which the current is sensed. In high current applications, even a low resistance value implies a relatively high parasitic series inductance. The sense voltage across the sense resistor is much too high because of this series inductance. Usually, the momentary shape of the current is required in the circuit in which the current is sensed. The sensed voltage may, for example, be used to regulate a power converter. It is not possible to average the sense voltage to obtain a better average value of the current through the sense resistor because then the required momentary information in the current is lost. Compensation networks still have significant inaccuracy rates due to tolerances of the components used. A current sensing circuit senses the momentary varying current flowing through the first impedance, and a second current which is related to the varying momentary current. A gain stage corrects the amplitude of the momentary information, which represents the momentary varying current, with a correction factor to obtain corrected momentary information. The correction factor is obtained by integrating the difference of the corrected momentary information and the sensed reference information representing the second current. Due to the integration, the disturbances associated with the sensing of the sensed currents decrease. The current sensing circuit controls the amplitude of the momentary information until the control loop is in the steady state wherein the integrated difference does not change anymore. Now, the average value of the corrected momentary information equals the average value of the reference information. Thus, the reference information is used to correct the amplitude of the momentary information. Consequently, the required momentary information on the current to be sensed is still available and is corrected in amplitude to minimize the influence of parasitic elements of the first impedance. Often, the influence of parasitic elements will be reduced by using compensation networks, the resulting waveform will be substantially correct, but with incorrect amplitude. This incorrect amplitude is corrected by using the reference information. Such a compensation network may be present in the sense circuits SCI and SC2. To conclude, the sense circuit in accordance with the invention has the advantage that the corrected momentary information has a high bandwidth, for example, suitable to be used for the instantaneous control of a power converter. A slow control loop averages the difference between the corrected momentary information and the reference information to control the gain stage to correct the inaccurate level of the momentary information as e.g. caused by parasitics. The slow control loop is able to determine the value of the second current more accurately than the sense circuit is able to determine the value of the first current because disturbances are integrated. The value of the second current is representative of the value of the first current because the second current is related to the first current. In an embodiment in accordance with the invention as defined in claim 2, the second impedance has an accurate nominal value. This has the advantage that not only the disturbances are averaged, but also that the amplitude of the corrected momentary information will be accurate even if an inaccurate first impedance is used. The first impedance need not be accurate because a deviation from its nominal impedance value or a variation in time of the impedance value will be corrected by using the second impedance. The accuracy of the amplitude of the momentary information depends on the accuracy of the nominal value of the second impedance. Thus, the first impedance, which need not be accurate, can be optimized to obtain the momentary value of the first current while the second impedance should have an accurate value, without the momentary voltage across it being critical. In an embodiment in accordance with the invention as defined in claim 3, the amplifier senses the voltage across the second impedance to obtain the reference information. The integrator integrates the difference of this reference information and the corrected momentary information. In an embodiment in accordance with the invention as defined in claim 4, the amplifier receives between its inputs the sum of the voltage across the second impedance and a voltage across the first resistor. The voltage across the first resistor is representative of the corrected momentary information. The slow control loop will adjust the amplitude of the momentary information until the average value of this sum voltage is zero, thus when the average value of the corrected momentary information is equal to the average value of the voltage across the second impedance. This sense circuit has the advantage with respect to the sense circuit defined in claim 3 that the gain of the amplifier does not influence the scaling factor of the second current. Both the corrected momentary information and the second current are processed by the same gain. In an embodiment in accordance with the invention as defined in claim 5, the switch is a field effect transistor, and the first impedance is the drain-source resistance of the field effect transistor. This inaccurate resistance which also depends on the temperature is sufficient to obtain the momentary information. The sensing with the second impedance is used in the slow loop to correct the amplitude of the momentary information. In an embodiment in accordance with the invention as defined in claim 7, the second impedance, which is an accurate resistor, is arranged in series with the drain-source path of the field effect transistor. The momentary varying current and the second current are equal. In multi-phase systems the momentary varying current per phase may differ from the second current. No corrections are required because of related non-equal currents. In an embodiment in accordance with the invention as defined in claim 9, the sensing circuit comprises two identical branches which both sense a current. Momentary information on these currents is corrected with two identical correction loops. Each correction loop integrates the difference of the corrected momentary information and the same reference information obtained over the same single sense impedance. This has the advantage that only a single reference sense impedance is required. The sensing of the currents in the branches may be inaccurate, for example the drain-source impedances may be used of field effect transistors. Preferably, the single sense impedance is an accurate resistor. Only one accurate and thus expensive reference sense impedance is required. The single reference sense impedance used in accordance with the invention is less expensive because less stringent requirements are imposed on its parasitics. If the single sense resistor is present in the input line of the power converter, it will be cheaper because the average current through it is lower. This advantage is valid also if more than two inaccurately sensed currents are to be corrected. In an embodiment in accordance with the invention as defined in claim 1 1, the sense circuit is incorporated in a down-converter wherein a series arrangement of the main current paths of a control FET (field effect transistor) and a sink FET receive a DC-input voltage. In an embodiment in accordance with the invention as defined in claim 12, the first impedance is the already present drain-source impedance of one of the FETs. This has the advantage that an extra resistor is not required. In an embodiment in accordance with the invention as defined in claim 13, the second impedance is an accurate resistor arranged in series with the drain-source path of the FET. The momentary varying current and the second current are equal. No corrections are required because of related non-equal currents. In an embodiment in accordance with the invention as defined in claim 14, the second impedance has an accurate value and is arranged in series with the inductor. Now, the voltage across the second impedance is representative of the current through the inductor and thus of the average output current of the power converter. The current through the inductor does not show sharp transitions, and thus the parasitics of the second impedance have less influence. In an embodiment in accordance with the invention as defined in claim 15, the second impedance is arranged between an input of the power converter and a node. A smoothing capacitor is coupled to the node to obtain a smoothed voltage for the series arrangement of the first mentioned switch and the further switch. Again, the second impedance carries an average current only. In an embodiment in accordance with the invention as defined in claim 18 or 19, a window circuit is added. The current through the drain-source path of the FET is available only during the on-time of the FET. The slow loop should take care that the integrated difference of the second information and the corrected momentary information is determined during the on-time of the FET only. Thus, the integrator should be active only during this on-period, or the difference should be processed only during this on-period. In an embodiment in accordance with the invention as defined in claim 20, two power converters are operated in parallel. Preferably, the periods in time during which these power converters provide current to the load differ to minimize the voltage ripple across the load. Again, in the same manner as in the embodiment in accordance with the invention as defined in claim 9, the sensing circuit comprises two identical branches which both sense a current. One branch senses the momentary current in one of the power converters, the other branch senses the momentary current in the other one of the power converters. Momentary information on these currents is corrected with two identical correction loops. Each correction loop integrates the difference of the corrected momentary information and the same reference information obtained over the same single sense impedance. This has the advantage that only a single reference sense impedance is required. The sensing of the currents in the branches may be inaccurate, for example the drain-source impedances of field effect transistors may be used. Preferably, the single sense impedance is an accurate resistor. Only one accurate and thus more expensive reference sense impedance is required. This advantage is valid also if more than two power converters are arranged in parallel and more than two inaccurately sensed currents are to be corrected. These and other aspects of the invention are apparent from and will be elucidated with reference to the embodiments described hereinafter.

In the drawings: Fig. 1 shows a block diagram of a current sensing circuit in accordance with an embodiment of the invention, Fig. 2 shows a block diagram of a current sensing circuit in accordance with an embodiment of the invention, Fig. 3 shows a block diagram of a current sensing circuit in accordance with an embodiment of the invention, Fig. 4 shows a block diagram of a current controlled switched mode power converter with a current sensing circuit in accordance with an embodiment of the invention, Fig. 5 shows a block diagram of a consumer electronics apparatus with a switched mode power converter and a current sensing circuit in accordance with an embodiment of the invention, Fig. 6 shows a block diagram of a current controlled switched mode power converter with a current sensing circuit in accordance with an embodiment of the invention, Fig. 7 shows signals for elucidating the window function of the power converter shown in Fig. 6, Fig. 8 shows a block diagram of two parallel arranged power converters.

Fig. 1 shows a block diagram of a current sensing circuit in accordance with an embodiment of the invention. A switch controller 10 controls on- and off-periods of the switch SW1, which, by way of example only, is a field effect transistor (further referred to as FET). The impedance of the main current path of the switch is indicated by the drain-source impedance Rds-on. A current II flows through the main current path of the switch SW1. A sensing circuit SCI senses the voltage across the main current path of the switch and supplies the momentary information MI, which is a momentary representation of the current II. A gain stage GS receives the momentary information MI and a correction signal CS to multiply the momentary information MI by a correction factor which depends on the correction signal CS and supplies corrected momentary information CMI. A current Is which is related to the current II flows through a sense resistor

Rs. The current Is may be equal to the current 11 , but may, for example, also be an averaged version of the current II, or only a portion of this current II . The current Is through the resistor Rs causes a voltage Al across the resistor Rs. This voltage Al is also referred to as the reference information Al. The sense circuit SC2 senses this reference information Al to supply the sensed reference information SAI. A subtractor SU subtracts the sensed reference information SAI from the corrected momentary information CMI to obtain a difference DI. The amplifier AM3 may optionally amplify the difference DI to obtain an amplified difference ADI. The integrator INT integrates the amplified difference ADI to obtain the correction signal CS. In prior art electronic systems, it is often required to sense a current. This generally requires the insertion of a current sense element in the current path. In high- efficiency systems it is not allowed to cause significant losses and thus a resistor with very low resistance has to be used. At a high current, such a resistor is expensive because usually the so-called Kelvin contacts have to be used. Further, the sensing will be inaccurate because dynamic signals are superimposed on the sensed voltage due to a parasitic inductance of the sensing resistor and wires or tracks connecting the sensing resistor to the sense circuit. Especially, if several currents have to be measured, a plurality of expensive accurate resistors with a low parasitic inductance is required. In the embodiment in accordance with the invention as shown in Fig. 1, an inaccurate sense element such as, for example, the drain-source impedance Rds-on of a FET is used. The voltage sensed across the FET is corrected by using a slow control loop. The current II which flows through the main current path of the FET causes a voltage across the FET which is sensed by the sense circuit SC 1. The sensed voltage MI is supplied to the multiplier GS which provides a variable gain of the sensed voltage MI. The output of the multiplier is compared with (e.g. subtracted from) a sensed reference signal SAI derived from the same current 11 by applying a well known sense element Rs that acts as a reference. Usually the sense element Rs is an accurate resistor. The result of the comparison is amplified with the amplifier AM3 and fed through a loop filter INT (e.g. an integrator) to control the multiplier GS. The settling point of the control action is obtained when the input signal for the amplifier AM3 is zero. Then, the average value of the output signal CMI (the corrected momentary information) is equal to the average value of the sense reference signal SAI. At a first glance, this approach shown in Fig. 1 may seem useless; it seems sufficient to sense the current through the accurate resistor Rs only instead of sensing both the voltage across the FET and the voltage across the accurate resistor Rs. However, the parasitic inductance of a discrete or integrated resistor introduces a large error in the sensed voltage. The use of expensive four point sensing may improve the accuracy of the wave shape of the sensed signal. A compensation network (RC low-pass network) is also commonly used to reduce the effects of the induced error signal. However, this compensation still suffers from limited accuracy. The advantage of using an inaccurate sensing across an inaccurate impedance (for example, the drain-source impedance of the FET) and a sensing across an accurate impedance Rs is that the first sensing provides a full spectrum signal and that the second sensing uses a reduced bandwidth to minimize the influence of parasitic effects. The correction loop averages the superimposed AC-signals caused by the parasitic inductance with the loop filter. The loop filter may comprise the amplifier AM3 and the integrator INT. Even if the sense impedance Rs has a relatively high parasitic inductance, an improved sensing is still possible because the influence of the parasitic inductance is largely compensated. It should be noted that both the switch SW1 and the sense resistor Rs are shown to be floating. This indicates that the switch SW1 can be positioned in an appropriate manner in any circuit in which the current has to be measured. The same holds for the sense resistor Rs which, dependent on the circuit, may also be positioned at many positions. For example, if the current is measured in a down converter with a control FET and a sync FET, the switch SWl may be either the control FET or the sync FET, and the sense resistor may be arranged in series with the main current path of either the control FET or the sync FET, or in the input or output line of the down converter. Fig. 2 shows a block diagram of a current sensing circuit in accordance with an embodiment of the invention. This Figure is based on Fig. 1, the only difference is that now the current II through the main current path of the switch SWl is identical to the current Is through the resistor Rs. However, in many systems it is not attractive to apply the reference resistor Rs directly in series with the current sense element Rds-on. Usually, the FET SWl operates as a switch which is turned on for part of the switching cycle only. This implies that the voltage across the main current path of the switch SWl reflects the current during a particular time slot of the switching cycle only. If the reference resistor Rs is not arranged in series with the main current path of the switch SWl, it is required to apply the same time slot to the processing of the signal from the reference resistor Rs. The time-slot-dependent processing is discussed in more detail with respect to the switches SI and S2 shown in Fig. 4. For example, the resistor Rs may be arranged in the input line of the power converter as shown in Fig. 3, or in series with the inductor L as shown in Figs. 4 to 6. It should again be noted that the series arrangement of the switch SWl and the sense resistor Rs is shown to be floating. This indicates that this series arrangement can be positioned in an appropriate manner in any circuit in which the current has to be measured. For example, if the current is measured in a down converter with a control FET and a sync FET, the switch SWl may be either the control FET or the sync FET, and the sense resistor is arranged in series with the main current path of either the control FET or the sync FET, or in the input or output line of the down converter. Fig. 3 shows a block diagram of a current sensing circuit in accordance with an embodiment of the invention. The current sensing circuit of Fig. 3 is based on the current sensing circuit of Fig. 1. Now, the resistor Rs is arranged in the input line instead of in series with the main current path of the switch SWl. Actually, the resistor Rs is arranged between the input of the current sensing circuit to receive the input voltage Vi and a node Na. Further, a smoothing capacitor Ci is connected to the node Na to smoothen the voltage at this node and to circulate the current in a small local loop with low value inductance L. The main current path of the switch SWl is also coupled to the node Na. Now, the current Is through the resistor Rs differs from the current II through the switch SWl . The current I I through the switch SWl has a shape which reflects the momentary state of the switch SWl . The current Is through the resistor Rs is more or less an average of the current II, depending on the Rs.Ci time constant. Again, the momentary value of the current II is sensed and the momentary sensed information MI representative of the current II is corrected with a correction signal CS. The correction signal CS is generated such that the average value of the corrected momentary sensed information CMI becomes equal to the average value of the reference information SAI which is representative of the current Is. The current Is has to be related to the current II. For example, it may be an averaged version or a portion only of the current II, or it may be related only during a particular period in time. The output node Nb of the switch SWl may be coupled to a load via an inductor L. Fig. 4 shows a block diagram of a switched mode power converter with a current sensing circuit in accordance with an embodiment of the invention. The switched mode power converter is a down-converter with a control switch SW2 and a sink sync switch SWl which are controlled by a switch controller 10 to have non- overlapping on-times. Usually, when the switch SW2 is closed, the switch SWl is opened, and when the switch SWl is opened the switch SW2 is closed. Thus, a non-inverted control signal Q is supplied to the control input of the control switch SW2 and an inverted control signal Qi is supplied to the control input of the sink switch SWl. The controller 10 uses the corrected information CMI to regulate the output voltage of the power converter by modulation of the on-times of the control switch SW2 and the sink switch SWl . The controller 10 requires further information, such as the output voltage Vo, to be able to regulate the power converter. Fig. 4 shows that both the control switch SW2 and the sink switch SWl are FETs. The main current paths of the FETs SWl, SW2 are arranged in series to receive the DC-input voltage Vi. A series arrangement of the sense resistor Rs and the inductor L is arranged between a junction of the main current paths and the output of the power converter. A current Is flows through the inductor L and through the resistor Rs. The power converter supplies an output voltage Vo. The sense circuit SC2 has inputs coupled across the resistor Rs to sense the voltage Vs across this resistor Rs, and an output to supply the sensed reference information SAI representative of the current Is. A switch S2 is arranged between the output of the sense circuit SC2 and an input of the subtractor SU to supply switched information WSAI to the subtractor SU. The sense circuit SCI has inputs which are coupled via a switch SI across the main current path of the sink switch SWl which has a drain-source impedance Rds-on. The momentary information MI is valid only when the switch SI is closed, and is supplied to the multiplier GS. The multiplier GS multiplies the momentary information MI with a correction factor dependent on the correction signal CS to obtain the corrected momentary information CMI as the output signal of the current sensing circuit. The correction signal CS is the integrated difference of the corrected momentary information CMI and the switched information WSAI. The switches SI and S2 are controlled synchronously, such that they are closed during the same period in time, which occurs during the on-period of the sink switch SWl. This implementation of a time-slot-dependent signal transfer is required because the voltage sensed across the main current paths of the switches (using Rds-on of the FETs) is valid only during the on-period of the respective switch SWl, SW2. Therefore, the signal derived from Rs has to be gated via a similar time-slot. The integration of the difference DI should only be active during a window in time in which both the momentary information MI about the current II and the sensed reference information SAI about the current Is valid. The implementation with the switches S 1 and S2 is one of many possible embodiments. The switch S 1 is preferably provided at the position shown because the amplitude of the voltage across the switch SWl may become very large when the switch SWl is switched off. The switch SI decouples the sensing circuit SCI from the junction of the main current paths of the switches SWl and SW2. The sensing circuit SCI need not withstand the very high voltage at this junction. But, this switch action may, for example, also be obtained by zeroing the output signal of the sensing circuit SCI outside the window. The switch S2 may also be positioned at the output of the subtractor SU. Alternatively, the output signal of the sensing circuit SC2 or the output of the subtractor SU may be zeroed outside the window. Thus, the use of the voltage across one of the switches SWl , SW2, which are relevant during a particular time slot, only requires that the proper transfer factor is obtained for the sensed reference information SAI. Thus, the sensed reference information SAI may be obtained from a current Is which is not exactly equal to the current II, as long as the same transfer factor is used on the sensed reference information SAI and on the momentary information MI. Fig. 5 shows a block diagram of an electronics apparatus with a switched mode power converter and a current sensing circuit in accordance with an embodiment of the invention. The power converter and the current sensing circuit shown in Fig. 5 are functionally equivalent to the circuit shown in Fig. 4. The switches SI and S2 are replaced by a window circuit WIN, which is introduced between the substractor SU and the integrator INT. Further, a load Lo is added to receive the output voltage Vo of the power converter. The load Lo is a circuit of the consumer electronics apparatus. The window circuit WIN takes care that the difference signal DI is integrated during an active period only. The active period is a part of or equal to the on-period of the sink switch SWl . For example, the window circuit WIN causes its output signal WDI to be zero outside the active period and transfers the input signal DI inside during the active period. The power converter is a buck converter with a control switch SW2, a sync or synchronous switch SWl, an inductor L, a load capacitor Co, and a load circuit Lo. The average value of the output current Is is sensed as the voltage Al flows (?) across the resistor Rs and is converted to sensed reference information SAI (also referred to as reference signal) by the amplifier AMI. Preferably, the amplifier AMI is a low frequency, low offset differential amplifier. The actual momentary current 11 , 12 in the power converter is measured by sensing the drain source voltage of one of the switching FETs SWl, SW2. In Fig. 5 is shown that the drain source voltage of the sink FET SWl is sensed, which is advantageous because the on-period of this sink FET SWl is relatively long compared to the on-period of the control FET SW2. The sensed drain source voltage MI (also referred to as the momentary information) is multiplied by a factor dependent on the correction signal CS to compensate for the tolerance of the drain source impedance Rds-on of the FET, and to compensate for parasitic effects. The output signal of the multiplier GS is the accurate current information CMI (also referred to as corrected momentary information) which is used by other circuits such as the switch controller 10 to regulate the power converter. This output signal CMI is also compared with the sensed average output current SAI of the power converter. The average value of the difference DI of these signals must be zero during the interval the current 11 flows through the sink switch SWl . Therefore a window function WIN is defined which multiplies the difference DI by one during the on-period of the sink switch SWl, and by zero outside this on-period. The output signal WDI of the window is integrated by the integrator INT (or low-pass filtered by the loop filter INT), which supplies the correction signal CS. If the slow correction loop has settled, the input signal WDI of the integrator INT must be zero, and thus, the corrected average value of the current 11 through the main current path of the sink FET SWl must be equal to the average value of the output current Is. The value of the resistor Rs can be selected very small because only the DC- component of the current Is needs to be sensed accurately. An accurate sensing of a small voltage is possible by applying well-known techniques that reduce offset such as e.g. application of a large transistor area and clever layout or auto zero technique or a chopper amplifier. In the circuit shown in Fig. 5, a tolerance occurs because the gain factor A 1 of the amplifier AMI determines the scaling factor of the output current Is. This problem is solved in the circuit shown in Fig. 6. It has to be noted that the switches SI and S2 shown in Fig. 4 and the window function shown in Fig. 5 are examples only. What counts is that the sensed signals are only compared during, and/or only contribute to the control signal during, equal periods in time during which both the sense signals have representative values. Fig. 6 shows a block diagram of a current controlled switched mode power converter with a current sensing circuit in accordance with an embodiment of the invention.

The power converter and current sense circuit of Fig. 6 is based on the power converter and current sense circuit of Fig. 5. The differences with respect to Fig. 5 are that, in Fig. 6, the multiplier GS has two identical current outputs CMIo and CMI. A resistor Rl is arranged between the junction of the inductor L and the resistor Rs and an input of the amplifier AM2, which replaces the amplifier AMI . The other input of the amplifier AM2 is connected to the output of the power converter via an optional resistor R2. Thus, the resistors Rl and Rs and the optional resistor

R2 are arranged in series between the inputs of the amplifier AM2. The current CMI flows through the resistor Rl while substantially (= a substantial part of ?) the output current Is flows through the resistor Rs. An optional capacitor CI is arranged between the node of the resistors Rl and Rs and the input of the amplifier AM2 to which the resistor R2 is connected.

The output current CMIo of the multiplier is the output signal of the current sense circuit.

The output signal DS of the amplifier AM2 is supplied to a window circuit WIN which supplies the windowed signal WDS and which operates in the same manner as the window circuit described with respect to Fig. 5. Once the slow calibration loop has settled, the average value of the voltage V2 between the inputs of the amplifier AM2 during the active window period must be zero.

Thus, the multiplication of the output current Is by the resistor value Rs must be equal to the output current CMI of the multiplier GS multiplied by the resistor value Rl . Or, in other words, the average value of the sensed output current Al = Rs x Is must be equal to the average value of the corrected sensed current CMI = g x Rds-on x II, wherein g is the multiplying factor of the multiplier GS. Fig. 7 shows signals for elucidating the window function of the power converter shown in Fig. 6. Fig. 7 A shows the current Is and the average value lav of this current, Fig. 7B shows the current 11 , and Fig. 7C shows the windowed signal WDS when the slow control loop is not settled. These signals are stylistic only, parasitic effects are not shown. A complete switching period of the power converter occurs during a switching period lasting from tl to t3. During the on-period of the control switch SW2, which lasts from instant t2 to instant t3, the DC-input voltage Vi is coupled to the inductor L. The voltage difference Vi - Vo across the inductor L causes the current Is through the inductor L to increase substantially linearly. During the on-period of the sink switch SWl , which lasts from instant tl to instant t2, the output voltage Vo is coupled across the inductor L and causes the current Is through the inductor L to decrease substantially linearly. The current II can only flow as long as the sink switch SWl is closed, thus from instant tl to instant t2. The window circuit WIN multiplies the difference signal DS by one (or another well defined factor) during the on-period of the sink switch SWl and by zero outside this on-period. A problem of this power converter may be that the current through the resistor Rs causes a voltage across the parasitic inductance of this resistor Rs. The substantially linearly increasing or decreasing current through Rs creates across the parasitic inductance a substantially square wave shaped voltage with positive or negative polarity, respectively. If no window is used, these negative and positive offset voltages caused by the parasitic inductance will have no influence because their average value is zero. However, if the voltage across the resistor Rs is sensed only during, for example, the decreasing part of the current Is, the offset voltage caused by the parasitic inductance has a negative value which will influence the sensing of the current Is through the resistor Rs. The resistor R2 and the capacitor R2 filter the voltage across the resistor Rs such that the influence of these offset voltages is minimal. Fig. 8 shows a block diagram of an arrangement for two power converters arranged in parallel. Each one of the two power converters is based on the power converter shown in Fig. 5. The items in Fig. 8 with an index a are identical to the items in Fig. 5 without this index a and form the first power converter. The items in Fig. 8 with an index b are identical to the items in Fig. 5 without this index b and form the second power converter. The construction of each one of the power supplies is not discussed in detail because it is identical to the construction shown in Fig. 5, only the windowing circuit WIN is not explicitly shown. The first power converter is a buck converter with a control switch SW2a, a sync or synchronous switch SWla, and an inductor La, and supplies a current ILa to the parallel arrangement of the output capacitor Co and the load Lo. The second power converter is a buck converter with a control switch SW2b, a sink or synchronous switch SWlb, and an inductor Lb, and supplies a current ILb to the parallel arrangement of the output capacitor Co and the load Lo. The value of the sum of the output currents Isa and Isb is sensed as the voltage Al across the resistor Rs, which is arranged in series with the parallel arrangement of the output capacitor Co and the load Lo. The voltage Al is converted to the sensed reference information SAI (also referred to as reference signal or sense signal) by the amplifier AMI. Preferably, the amplifier AMI is a low frequency, low offset differential amplifier. The actual momentary current I la, I2a in the first power converter is measured by sensing the drain source voltage of one of the switching FETs SWla, SW2a. In Fig. 8 is shown that the drain source voltage of the sink FET SWla is sensed, which is advantageous because the on-period of this sink FET SWla is relatively long compared to the on-period of the control FET SW2a. The sensed drain source voltage Mia (also referred to as the momentary information) is multiplied by a factor dependent on the correction signal CSa to compensate for the tolerance of the drain source impedance Rds-on of the FET SWla, and to compensate for parasitic effects. The output signal of the multiplier GSa is the accurate current information CMIa (also referred to as corrected momentary information) which is used to regulate the first power converter. This output signal CMIa is also compared with the sensed reference information SAI of the parallel arranged power converters. The average value of the difference DIa of these signals must be zero during the interval the current 11 a flows through the sink switch SWla. The actual momentary current 11 b, I2b in the second power converter is measured by sensing the drain source voltage of one of the switching FETs SWlb, SW2b. In Fig. 8 is shown that the drain source voltage of the sink FET SWlb is sensed, which is advantageous because the on-period of this sink FET SWlb is relatively long compared to the on-period of the control FET SW2b. The sensed drain source voltage Mlb (also referred to as the momentary information) is multiplied by a factor dependent on the correction signal CSb to compensate for the tolerance of the drain source impedance Rds-on of the FET SWl b, and to compensate for parasitic effects. The output signal of the multiplier GSb is the accurate current information CMIb (also referred to as corrected momentary information) which is used by the switch controller 10 to regulate the power converter. This output signal CMIb is also compared with the sensed reference information SAI of the parallel arranged power converters. The average value of the difference DIb of these signals must be zero during the interval the current lib flows through the sink switch SWlb. The windowing of the signals is not explicitly shown but may be implemented in the integrators INTa and INTb or in the subtractors SUa and SUb. It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. Although the current sense circuit, when used in a power converter, is shown to be combined with a down converter with a control switch SW2 and a sync switch SWl, the current sense circuit in accordance with the invention can be implemented in any power converter in which an accurate sensing of a current is required. The current sensing is not limited to application in a power converter. All embodiments illustrate signal processing in the analog domain. It must be understood that the goal of the invention as described in the text can be achieved as well by other approaches, e.g. by conversion of analog signals into digital signals and vice versa and by signal processing in the digital domain. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. Use of the verb "comprise" and its conjugations does not exclude the presence of elements or steps other than those stated in a claim. The article "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the device claim enumerating several means, several of these means may be embodied by one and the same item of hardware. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Claims

CLAIMS:

1. A current sensing circuit comprising: a first impedance (Rds-on; Rds-ona) and a first sensing circuit (SCI ; SCI a) for obtaining momentary information (MI; Mia) on a momentary varying current (II; I la) flowing through the first impedance (Rds-on; Rds-ona), a second impedance (Rs) for conducting a second current (Is) being related to the momentary varying current (11 ; 11 a) to obtain a reference information (Al), a gain stage (GS; GSa) for receiving the momentary information (MI; Mia) and a correction signal (CS; CSa) for controlling a gain of the gain stage (GS; GSa) to supply a corrected momentary information (CMI; CMIa), and an averaging circuit (AV) for averaging a difference between the corrected momentary information (CMI; CMIa) and the reference information (Al) to obtain the correction signal (CS; CSa).

2. A current sensing circuit as claimed in claim 1 , wherein the second impedance (Rs) has an accurate nominal value.

3. A current sensing circuit as claimed in claim 1, wherein the averaging circuit (AV) comprises: an amplifier (AMI) for receiving a voltage across the second impedance (Rs) as the reference information (Al) to supply a sensed reference information (SAI), and an integrator (INT) for integrating a difference between the corrected momentary information (CMI) and the sensed reference information (SAI) to obtain the correction signal (CS).

4. A current sensing circuit as claimed in claim 1, wherein the averaging circuit

(AV) comprises: a resistor Rl being coupled between a terminal of the second impedance (Rs) and an output of the gain stage (GS) to receive a current representing the corrected momentary information (CMI), an amplifier (AM2) for receiving a voltage across a series arrangement of the second impedance (Rs) and the resistor (Rl) to supply a difference signal (DS) being a difference between the corrected momentary information (CMI) and the reference information (IA), and an integrator (INT) for integrating the difference signal (DS) to obtain the correction signal (CS).

5. A current sensing circuit as claimed in claim 1, further comprising a semiconductor switch (SWl), a switch controller (10) for controlling said switch (SWl) to obtain a momentary varying current (IL) through a main current path of said switch (SWl), and wherein said switch (SWl ) comprises a field effect transistor, the first impedance being an on-resistance (Rds-on) of the main current path of said field effect transistor (SWl), and the first current (11 ) being the momentary varying current through the main current path of said field effect transistor (SWl).

6. A current sensing circuit as claimed in claim 1 or 5, wherein the second impedance (Rs) is a resistor.

7. A current sensing circuit as claimed in claim 6 when dependent on claim 5, wherein the resistor (Rs) is arranged in series with the main current path of the field effect transistor (SWl).

8. A current sensing circuit as claimed in claim 1 , wherein the gain stage (GS) comprises a multiplier for multiplying the momentary information (MI) by a correction factor depending on the correction signal (CS) to supply the corrected momentary information (CMI).

9. A current sensing circuit as claimed in claim 1, and further comprising: a third impedance (Rds-onb) and a third sensing circuit (SClb) for obtaining further momentary information (Mlb) on a further momentary varying current (11 b) flowing through the third impedance (Rds-onb), a gain stage (GSb) for receiving the further momentary information (Mlb) and a further correction signal (CSb) for controlling a further gain of the further gain stage (GSb) to supply a further corrected momentary information (CMIb), and a further averaging circuit (AVb) for averaging a further difference between the further corrected momentary information (CMIb) and the reference information (Al) to obtain the further correction signal (CSb), and wherein the second current (Is) is related to a sum of the first mentioned momentary varying current (I la) and the further momentary varying current (11 b) to obtain a reference information (Al).

10. A current-controlled switched mode power converter comprising: an inductor (L; La), a switch (SWl; SWla) coupled to the inductor (L; La), a switch controller (10) for controlling the switch (SWl; SWla) to obtain a periodical current (IL; ILa) through the inductor (L; La), a first impedance (Rds-on; Rds-ona) and a first sensing circuit (SCI; SCla) for obtaining momentary information (MI; Mia) on a momentary varying current (II ; Ila) flowing through the first impedance (Rds-on; Rds-ona), the momentary varying current (II; Il a) being related to the periodical current (IL; ILa), a second impedance (Rs) for conducting a second current (Is) being related to the momentary varying current (II; Ila) to obtain a reference information (Al), a gain stage (GS; GSa) for receiving the momentary information (MI; Mia) and a correction signal (CS; CSa) for controlling a gain of the gain stage (GS; GSa) to supply a corrected momentary information (CMI; CMIa), and an averaging circuit (AV) for averaging a difference between the corrected momentary information (CMI; CMIa) and the reference information (Al) to obtain the correction signal (CS; CSa).

11. A current-controlled switched mode power converter as claimed in claim 10, further comprising a further switch (SW2) having a main current path arranged in series with the main current path of the first mentioned switch (SWl), the series arrangement of said main current paths being arranged to receive a DC-input voltage (Vi), the inductor (L) being arranged between an output of said power converter and a junction of said main current paths.

12. A current-controlled switched mode power converter as claimed in claim 10, wherein the first mentioned switch (SWl) comprises a field effect transistor, the first impedance being an on-resistance (Rds-on) of the main current path of said field effect transistor (SWl).

13. A current-controlled switched mode power converter as claimed in claim 10, wherein the second impedance (Rs) is arranged in series with the main current path of the switch (SWl).

14. A current-controlled switched mode power converter as claimed in claim 10, wherein the second impedance (Rs) is arranged in series with the inductor (L).

15. A current-controlled switched mode power converter as claimed in claim 11, wherein the second impedance (Rs) is arranged between an input of said power converter and a node, a smoothing capacitor is coupled to the node for obtaining a smoothed voltage to be supplied to the series arrangement of the first mentioned switch (SWl) and the further switch (SW2).

16. A current-controlled switched mode power converter as claimed in claim 12, wherein the second impedance (Rs) has an accurate value and is arranged in series with the inductor (L), and wherein the averaging circuit (AV) comprises: an amplifier (AMI) for receiving a voltage across the second impedance (Rs) as the reference information (Al) to supply a sensed reference information (SAI), and an integrator (INT) for integrating a difference between the corrected momentary information (CMI) and the sensed reference information (SAI) to obtain the correction signal (CS).

17. A current-controlled switched mode power converter as claimed in claim 12, wherein the second impedance (Rs) has an accurate value and is arranged in series with the inductor (L), and wherein the averaging circuit (AV) comprises: a resistor Rl being coupled between an output of the gain stage (GS) to receive the corrected momentary information (CMI) and a terminal of the second impedance

(Rs), an amplifier (AM2) for receiving a voltage across a series arrangement of the second impedance (Rs) and the resistor (Rl) to supply a difference signal (DS) being a difference between the corrected momentary information (CMI) and the reference information (IA), and an integrator (INT) for integrating the difference signal (DS) to obtain the correction signal (CS).

18. A current-controlled switched mode power converter as claimed in claim 16, wherein the averaging circuit (AV) further comprises a means (DIF) for receiving the corrected momentary information (CMI) and the sensed reference information (SAI) to supply a difference signal (DI), and wherein the current-controlled switched mode power converter further comprises a window circuit (WIN) for receiving the difference signal (DI) to supply a windowed difference signal (WDI) to the integrator (INT).

19. A current-controlled switched mode power converter as claimed in claim 17, wherein the current-controlled switched mode power converter further comprises a window circuit (WIN) for receiving the difference signal (DS) to supply a windowed difference signal (WDI) to the integrator (INT).

20. A current-controlled switched mode power converter as claimed in claim 10, and further comprising: a further inductor (Lb), a further switch (SWlb) coupled to the further inductor (Lb), the switch controller (10) being arranged for controlling the further switch (SWlb) to obtain a further periodical current (ILb) through the further inductor (Lb), a third impedance (Rds-onb) and a third sensing circuit (SClb) for obtaining further momentary information (Mlb) on a further momentary varying current (lib) flowing through the third impedance (Rds-onb), the further momentary varying current (11 b) being related to the further periodical current (ILb), the second impedance (Rs) for conducting the second current (Is) being related to a sum of the first mentioned momentary varying current (Ila) and the further momentary varying current to obtain the reference information (Al), a further gain stage (GSb) for receiving the further momentary information (Mlb) and a further correction signal (CSb) for controlling a further gain of the further gain stage (GSb) to supply a further corrected momentary information (CMIb), and a further averaging circuit (AV) for averaging a difference between the further corrected momentary information (CMIb) and the reference information (Al) to obtain the further correction signal (CSb).

21. An integrated circuit comprising a current sensing circuit as claimed in claim 1.

22. A consumer electronics apparatus comprising a current sensing circuit as claimed in claim 1.

23. A consumer electronics apparatus comprising a current-controlled switched mode power converter as claimed in claim 10.