WO2005008894A1

WO2005008894A1 - Delay locked loop for generating multi-phase clocks without voltage-controlled oscillator

Info

Publication number: WO2005008894A1
Application number: PCT/KR2003/001581
Authority: WO
Inventors: Kwang Oh Kim
Original assignee: Dawin Technology Inc
Current assignee: Dawin Technology Inc
Priority date: 2003-07-23
Filing date: 2003-08-06
Publication date: 2005-01-27
Anticipated expiration: 2006-01-23
Also published as: AU2003251186A1; KR20050011586A; KR100531457B1

Abstract

Disclosed is a delay locked loop for generating multi-phase clocks without a voltage-controlled oscillator to prevent the generated multi-phase clocks from being locked to harmonics of an input clock signal frequency and to improve jitter characteristic for variations in temperature and process. The delay locked loop for generating multi-phase clocks without a voltage-controlled oscillator, comprises a clock delay means having a plurality of delay means for sequentially delaying an input clock signal to output the multi-phase clocks; a phase detector for detecting a phase difference between the input clock signal and an output clock signal of the clock delay means, to output a predetermined control signal for controlling the quantity of delay of the clock delay means; and a clock position detector for detecting a delay point of a clock signal output from the clock delay means, to output a control signal for controlling the quantity of delay of the clock delay means prior to the phase detector.

Description

DELAY LOCKED LOOP FOR GENERATING MULTI-PHASE CLOCKS WITHOUT VOLTAGE-CONTROLLED OSCILLATOR

Technical Field The present invention relates to a delay-locked loop (DLL) for

generating multi-phase clocks. More specifically, the present invention

relates to a DLL for generating multi-phase clocks without a voltage-

controlled oscillator to prevent the generated multi-phase clocks from being

locked to harmonics of an input clock signal frequency and to improve jitter

characteristic for variations in temperature and processes.

Background Art

In general, computers, various communication systems and electronic

communication appliances require high-frequency clocks for the purpose of

transmitting and receiving data at a high speed. However, transmission and

reception of data using high-frequency clocks deteriorates electromagnetic

interference characteristic of communication systems.

Accordingly, data has been transmitted using low-frequency clocks

rather than high-frequency clocks recently. Restoration of received data is

carried out using a method that generates high-frequency clocks using a phase locked loop (PLL) or creates multi-phase clocks using a delay and

phase locked loop (D/PLL) for high-speed data transmission systems to lock

the clocks and received data with each other and restore the data.

However, the clocks created using PLL have very high frequency so

that skew may generate between the clocks and data in a system. This

causes the system to operate erroneously and affects jitter characteristic of

the clocks. Furthermore, PLL is not suitable for high-speed data

communication because it has a problem of jitter accumulation due to

integration characteristic of a voltage-controlled oscillator. The multi-phase clocks generated through D/PLL can eliminate skew

that generates when PLL is used.

FIG. 1 is a block diagram showing the construction of a conventional

D/PLL for generating multi-phase clocks. The conventional D/PLL, shown in

FIG. 1 , feeds back a loop, which is constructed of a voltage-controlled delay

line 1 , a voltage-controlled oscillator 2, a phase and frequency detector

(PFD) 3, a charge pump 4, a loop filter 5, and a voltage-current converter 6,

hundreds to thousands times to lock the phase and frequency of an output

clock signal DCLK of the voltage-controlled delay line 1 to those of an input

clock signal RCLK, thereby generating desired multi-phase clocks CLKi to

CLK_IM. The voltage-controlled delay line 1 delays the input clock signal RCLK by a predetermined delay time on the basis of predetermined delay control

signals CTP and CTN applied thereto from the outside to output multi-phase

clocks CLKι to CLK_IM. The voltage-controlled oscillator 2 outputs a clock

signal VCLK with a predetermined frequency in response to the delay control

signals CTP and CTN. The phase and frequency detector 3 compares the

phase and frequency of the clock signal VCLK output from the voltage-

controlled oscillator 2 with those of a clock signal DCLK that is selected from

the multi-phase clocks CLKι to CLKN output from the voltage-controlled

delay line 1 (preferably, the clock signal of the final delay stage is selected)

and outputs a predetermined down control signal DN for increasing the

quantity of delay of the input clock signal RCLK or an up control signal UP

for decreasing the quantity of delay according to the comparison result. The

charge pump 4 outputs a voltage signal corresponding to the quantity of

electrical charges charged/discharged in response to the up control signal

UP or down control signal DN that has a ' HIGH' level, for example, output

from the phase and frequency detector 3. The loop filter 5 filters high-

frequency components of the voltage signal output from the charge pump 4.

The voltage-current converter 6 outputs the delay control signals CTP and

CTN to control the operation of the voltage-controlled delay line 1 and

voltage-controlled oscillator 2 according to the output voltage level of the loop filter 5.

However, the conventional D/PLL having the aforementioned

construction stores jitter and various noises according to integration

characteristic of the voltage-controlled oscillator 2, which deteriorates jitter

characteristic of the multi-phase clocks CLKi to CLKN. Furthermore,

mismatch between the voltage-controlled oscillator 2 and voltage-controlled

delay line 1 , caused by variations in temperature and process, obstructs

locking of the input clock signal RCLK and the multi-phase clocks CLKi to

CLKN, deteriorates characteristics of the multi-phase clocks CLKi to CLKN

and makes it difficult to transmit and receive data at high-speed.

In the case that the voltage-controlled oscillator 2 is eliminated from

the construction of the conventional D/PLL in order to improve jitter

characteristic, a general delay locked loop, as shown in FIG. 2, is obtained.

The phase and frequency detector 3 of this DLL uses the input clock signal

RCLK and the output clock signal DCLK of the voltage-controlled delay line 1

as input signals for detecting a clock phase difference.

FIG. 3a shows waveforms of the output signals of the phase and

frequency detector 3 when the quantity of delay of the voltage-controlled

delay line 1 is more than 3T/2. As shown in FIG. 3a, the phase and

frequency detector 3 outputs ' HIGH' level down control signal DN, for example, when the rising edge of the output clock signal DCLK of the

voltage-controlled delay line 1 is prior to the rising edge of the input clock

signal RCLK. This down control signal DN increase the quantity of delay of

the voltage-controlled delay line 1 to lock the output clock signal DCLK of

the voltage-controlled delay linel to the second harmonics (Δ=2T) of the

input clock signal RCLK, generating multi-phase clocks CLKi to CLKN.

In the case that the rising edge of the input clock signal RCLK is

followed by the rising edge of the output clock signal DCLK of the voltage-

controlled delay line 1 (in case of Δ>2T), the phase and frequency detector 3

outputs ' HIGH' level up control signal UP, for example. This up control

signal UP decreases the quantity of delay of the voltage-controlled delay line

1 and locks the output clock signal DCLK to the second harmonics (Δ=2T) of

the input clock signal RCLK to generate multi-phase clocks CLKi to CLKN. However, there is a problem that the frequency of the multi-phase

clocks CLKi to CLKN locked to the harmonics of the input clock signal RCLK

according to the above-described procedure is locked to 1 /(order of

harmonics) of the frequency of a normal clock.

FIG. 3b shows the waveforms of the output signals of the phase and

frequency detector 3 when the quantity of delay of the voltage-controlled

delay line 1 is less than 1/2. As shown in FIG. 3b, the rising edge of the input clock signal RCLK is followed by the rising edge of the output clock

signal DCLK of the voltage-controlled delay line 1 all the time. In this case,

the phase and frequency detector 3 outputs only the up control signal UP

having ' HIGH' level, for example, until clock locking is achieved. This

decreases the quantity of delay of the voltage-controlled delay line 1 and,

finally, reduces it to a physical minimum delay time. As a result, the multi^¬

phase clocks CLKi to CLKN output from the voltage-controlled delay line 1

remain at a certain point within T/2 of the input clock signal RCLK, which

causes an erroneous operation in which locking is not accomplished. That is, DLL having the aforementioned construction does not have

the voltage-controlled oscillator that locks the frequency of the output clock

signal DCLK to that of the input clock signal RCLK so that an erroneous

operation occurs when the quantity of delay of the voltage-controlled delay

line 1 is more than 3T/2 (T corresponds to one period of the input clock

signal) of the input clock signal RCLK or less than T/2.

Disclosure of Invention

Accordingly, an object of the present invention is to provide a delay

locked loop for generating multi-phase clocks without a voltage-controlled

oscillator, which prevents the multi-phase clocks from being locked to harmonics of the frequency of an input clock signal, restrains jitter and noise

caused by integration characteristic of the voltage-controlled oscillator from

increasing, and improves jitter characteristic for variations in temperature and

process. To accomplish the object of the present invention, there is provided a

delay locked loop for generating multi-phase clocks without a voltage-

controlled oscillator, comprising a clock delay means having a plurality of

delay means for sequentially delaying an input clock signal, to output the

multi-phase clocks; a phase detector for detecting a phase difference

between the input clock signal and an output clock signal of the clock delay

means, to output a predetermined control signal for controlling the quantity

of delay of the clock delay means; and a clock position detector for

detecting a delay point of a clock signal output from the clock delay means,

to output a control signal for controlling the quantity of delay of the clock

delay means prior to the phase detector.

To accomplish the object of the present invention, there is provided a

delay locked loop for generating multi-phase clocks without a voltage-

controlled oscillator, comprising a voltage-controlled delay line for

controlling the quantity of delay of an input clock signal on the basis of the

quantity of current of a first control signal applied thereto, to output first to Nth clock signals that are sequentially delayed; a clock position detector for

performing a logical operation for at least two of the first to Nth clock signals,

to output a second control signal for controlling the quantity of delay of the

voltage-controlled delay line; a phase and frequency detector for comparing

the phase of one of the output clock signals of the voltage-controlled delay

line with the phase of the input clock signal, to output a third control signal

for controlling the quantity of current of the first control signal; a charge

pump for charging or discharging electrical charges according to signal

levels of the third control signal and the second control signal prior to the

third control signal and outputting a voltage signal corresponding to the

quantity charged or discharged electrical charges; a loop filter for filtering

high-frequency components of the voltage signal output from the charge

pump; and a voltage-current converter for outputting the first control signal

corresponding to rising/falling state of an output voltage level of the loop

filter.

The clock position detector receives at least two of the first to Nth

clocks at a specific interval within one period of the input clock signal to

detect a delay point of the Nth clock .

The clock position detector detects the delay point of the Nth clock in

response to the falling edge of the input clock signal. The quantity of delay of the voltage-controlled delay line increases or

decreases according to a voltage level of the third control signal when the

quantity of delay is in the range of T/2 to 3T/2 of the input clock signal, and

it increases or decreases according to a voltage level of the second control

signal when it is less than T/2 or more than 3T/2 of the input clock signal.

According to the aforementioned construction, the multi-phase

clocks generated by the delay locked loop is prevented from being locked to

harmonics of the input clock signal frequency, and jitter characteristic is

improved for variations in temperature and process because the delay locked

loop does not employ a voltage-controlled oscillator.

Brief Description of Drawings

Further objects and advantages of the invention can be more fully

understood from the following detailed description taken in conjunction with

the accompanying drawings, in which'-

FIG. 1 is a block diagram showing the construction of a conventional

D/PLL for generating multi-phase clocks;

FIG. 2 is a block diagram showing the construction of a general delay

locked loop without voltage-controlled oscillator; FIG. 3a shows the waveforms of output signals of the phase and frequency detector when the quantity of delay of the voltage-controlled delay

line of FIG. 2 is more than 3T/2;

FIG. 3b shows the waveforms of output signals of the phase and

frequency detector when the quantity of delay of the voltage-controlled delay

line of FIG. 2 is less than T/2;

FIG. 4 is a block diagram showing the construction of a delay locked

loop for generating multi-phase clocks without a voltage-controlled

oscillator in accordance with the present invention;

FIG. 5 is a circuit diagram showing the internal construction of the

voltage-controlled delay line shown in FIG. 4;

FIG. 6 is a circuit diagram showing the internal construction of the

clock position detector shown in FIG. 4;

FIG. 7 is a circuit diagram showing the internal construction of the

phase and frequency detector shown in FIG. 4; FIG. 8a shows the waveforms of output signals of the phase and

frequency detector when the quantity of delay of the voltage-controlled delay

line of FIG. 4 is in the range from T/2 to 3T/2;

FIG. 8b shows the waveforms of output signals of the phase and

frequency detector when the quantity of delay of the voltage-controlled delay

line of FIG. 4 is more than 3T/2; and FIG. 8c shows the waveforms of output signals of the phase and

frequency detector when the quantity of delay of the voltage-controlled delay

line of FIG. 4 is less than T/2.

Best Mode for Carrying Out the Invention

The present invention will now be described in detail in connection

with preferred embodiments with reference to the accompanying drawings. FIG. 4 is a block diagram showing the construction of a delay locked

loop for generating multi-phase clocks without a voltage-controlled

oscillator in accordance with the present invention. Now referring to FIG. 4,

identical elements described with reference to FIG. 1 , have the same

reference numerals and detailed description will be omitted.

The delay locked loop shown in FIG. 4 includes a voltage-controlled

delay line 10, a clock position detector 20, a phase and frequency detector

30, a charge pump 40, a loop filter 5 and a voltage-current converter 6,

which form a loop.

The voltage-controlled delay line 10 sequentially delays an input clock

signal RCLK through internal buffers according to delay control signals CTP

and CTN output from the voltage-current converter 6, to output multi-phase

clocks CLKi to CLKN (preferably, N is a positive integer and a multiple of 2) in u the same manner as that of the voltage-controlled delay line 1 of FIG. 1 . The

voltage-controlled delay line 10 selectively outputs Jth and Kth delayed clock

signals CLKj and CLK« among the multi-phase clocks CLKi to CLKN to the

clock position detector 20 and outputs the Nth delayed clock signal DCLK

(that is, CLKN) to the phase and frequency detector 30 in order to control the

quantity of delay of the input clock signal RCLK. A method of selecting the

Jth and Kth delayed clock signals CLKj and CLK_K will be described in detail

hereinafter.

The clock position detector 20 detects signal levels of the Jth and Kth

clock signals applied from the voltage-controlled delay line 10 at the falling

edge of the input clock signal RCLK and performs a logical operation for the

detected signal levels to output an unconditional up or down control signal

UCUP or UCDN with a predetermined level for controlling the quantity of

electrical charges charged/discharged of the charge pump 40. In a preferred embodiment of the present invention, when the

unconditional up control signal UCUP has a ' HIGH' level, for instance, the

charge pump 40 charges electrical charges unconditionally irrespective of

the signal level of an up or down control signal UP or DN. Consequently, the

output voltage level of the charge pump 40 is raised so that the quantity of

current of the delay control signals CTP and CTN is increased but the quantity of delay of the voltage-controlled delay line 10 is decreased. In the case that the unconditional down control signal UCDN has a ' HIGH' level, for example, the charge pump 40 discharges electrical charges unconditionally irrespective of the signal level of the up or down control signal UP or DN so that its output voltage level decreases. This reduces the quantity of current of the delay control signals CTP and CTN but increases the quantity of delay of the voltage-controlled delay line 10.

According to the aforementioned control operation, the clock position detector 20 outputs the unconditional up or down control signal UCUP or

• UCDN when the quantity of delay of the voltage-controlled delay line 10 is more than 3T/2 of the input clock signal RCLK or less than T/2 to control the quantity of delay of the voltage-controlled delay line 10 irrespective of the signal level of the up or down control signal UP or DN. Accordingly, the multi-phase clocks CLKi to CLKN are prevented from being locked to harmonics of the frequency of the input clock signal RCLK or being in a state that they cannot locked to the input clock signal.

The phase and frequency detector 30 detects a phase difference between the input clock signal RCLK and the output clock signal DCLK of the voltage-controlled delay line 10 and outputs the up or down control signal UP or DN based on the detected phase difference, to control the quantity of charged/discharged electrical charges of the charge pump 40. Distinguished

from the conventional phase and frequency detector 3 shown in FIG. 1 that

detects the phase difference between the output clock signal VCLK of the

voltage-controlled oscillator 2 and the output clock signal DCLK of the

voltage-controlled delay line 1 to output the up or down control signal UP or

DN, the phase and frequency detector 30 according to the present invention

uses the input clock signal RCLK as an input signal for detecting the phase

difference so that the voltage-controlled oscillator 2 can be eliminated from

the delay locked loop. The charge pump 40 charges/discharges electrical charges in

response to the up or down control signal UP or DN output from the phase

and frequency detector 30 and the unconditional up or down control signal

UCUP or UCDN output from the clock position detector 20, and outputs a

voltage signal corresponding to the quantity of charged/discharged electrical

charges to the loop filter 5. The voltage signal output from the charge pump

40 is converted into the delay control signals CTP and CTN through the loop

filter 5 and the voltage-current converter 6, to control the quantity of delay of

the voltage-controlled delay line 10.

The construction and operation of the delay locked loop according to

the present invention is described in more detail with reference to FIGS. 5, 6 and 7.

FIG. 5 is a circuit diagram showing the internal construction of the

voltage-controlled delay line 10 shown in FIG. 4. As shown in FIG. 5, the

voltage-controlled delay line 10 includes first to Nth inverters 10ι to 1 ON that

are sequentially connected.

The first inverter 10ι delays and inverts the input clock signal RCLK in

response to the input clock signal RCLK and delay control signals CTP and

CTN applied thereto. The delayed and inverted clock is output as a first clock

signal CLKi and used as an input signal of the second inverter I O₂. In the

same manner, the second to Nth inverters 10₂ to 10N delay and invert the first

to (N— 1 )th clock signals CLKi to CLKN-_I in response to the delay control

signals CTP and CTN, respectively. These delayed and inverted clock signals

are respectively output as the second to Nth clock signals CLK2 to CLKN, to

thereby generate the multi-phase clocks CLKi to CLKN. The Jth and Kth clock signals CLKj and CLKK output from the Jth and

Kth inverters 10j and 10κ (not shown) (J and K are integers, N is an integer

and a multiple of 2, — < J < — and — < K < — ) are supplied to the clock 4 2 2 4

position detector 20 as its input signals to be used as reference signals for

outputting the unconditional up or down control signal UCUP or UCDN. The

Jth and Kth clock signals CLKj and CLKK are inverted clock signals when they are output from odd-numbered inverters but buffered clock signals when

they are output from even-numbered inverters. The input clock signal RCLK

is sequentially delayed for a predetermined period of time T=N*t (here, t

means delay time of each inverter) to be supplied to the phase and

frequency detector 30 as its input signal DCLK.

According to experiments carried out by the applicant, an appropriate

quantity of delay for preventing the delay locked loop from operating

erroneously can be obtained when the Jth clock signal CLKj is selected from

the range of T/4 to T/2 of the input clock signal RCLK and the Kth clock

signal CLK_K is selected from the range of T/2 to 3T/4 of the input clock

signal RCLK.

The selection ranges of the Jth and Kth clock signals are employed

when two internal clocks are used as the reference signals for controlling the

quantity of delay of the input clock signal RCLK. It is also possible to use

more than two reference signals for detecting clock positions more

accurately.

That is, the above-described ranges of the input clock signals RCLK

from which the reference signals are selected are exemplary so that it is

possible to select reference signals at a specific interval within one period T

of the input clock signal RCLK in consideration of the number of reference signals used. In the case that four internal clocks are used as the reference

signals for controlling the quantity of delay, for instance, it is preferable that

the reference signals are selected from the ranges of 0—T/4, T/4—T/2,

T/2-3T/4 and 3T/4-T, respectively. FIG. 6 is a circuit diagram showing the internal construction of the

clock position detector 20 shown in FIG. 4. Referring to FIG. 6, the clock

position detector 20 includes first and second D-flip flops 21 and 22, a

NAND gate 23, and inverters 24 and 25. The first and second D-flip flops 21

and 22 respectively receive the Jth and Kth clock signals CLKj and CLKK

through their input ports and respectively accept the input clock signal RCLK

through their inverted clock input ports. The output ports of the first and

second D-flip flops 21 and 22 are respectively connected to the input ports

of the NAND gate 23. The inverters 24 and 25 are connected to the output

port of the first D-flip flop 21 and the output port of the NAND gate 23,

respectively.

Specifically, the first D-flip flop 21 receives the Jth clock signal CLKj

output from the voltage-controlled delay line 10 and outputs the Jth clock

signal CLKj with a ' HIGH' or ' LOW level to one input port of the NAND

gate 23 and the inverter 24 in response to the falling edge of the input clock

signal RCLK. Here, the inverter 24 inverts the output signal of the first D-flip flop 21 to output it as the unconditional up control signal UCUP. The second

D-flip flop 22 accepts the Kth clock signal CLKK output from the voltage-

controlled delay line 10 and outputs the Kth clock signal CLKK with a

' HIGH' or ' LOW' level to the other input port of the NAND gate 23 in

response to the falling edge of the input clock signal RCLK. Here, the

inverter 25 inverts the output signal of the NAND gate 23 to output it as the

unconditional down control signal UCDN.

The following table 1 represents output levels of the unconditional up

and down control signals UCUP and UCDN according to signal levels of the

Jth and Kth clock signals CLKj and CLKK at the falling edge of the input clock

signal RCLK.

Table 1

In table 1 , when the Jth clock signal CLKj is ' HIGH' and the Kth

clock signal CLKK is ' LOW' , which means that the quantity of delay of the

voltage-controlled delay line 10 is in the range of T/2-3T/2, the delay locked

loop can control the quantity of delay of the voltage-controlled delay line 10 only using the up or down control signal UP or DN in the same manner as the

conventional DLL.

In the case that the Jth clock signal CLKj is ' LOW' and the Kth

clock signal CLK_K is ' HIGH' or ' LOW' , which means that the quantity of

delay of the voltage-controlled delay line 10 is more than 3T/2, the clock

position detector 20 outputs the unconditional up control signal UCUP with

HIGH' level to charge the charge pump 40 so as to prevent the delay

locked loop from being locked to harmonics of the input clock signal RCLK

as shown in FIG. 3a. As the output voltage level of the charge pump 40

increases, the quantity of delay of the voltage-controlled delay line 10 is

reduced to the range of T/2—3T/2 where the quantity of delay can be

controlled through the up or down control signal UP or DN.

When both of the Jth clock signal CLK and the Kth clock signal CLKK

are ' HIGH' , which means that the quantity of delay of the voltage-

controlled delay line 10 is less than T/2, the clock position detector 20

outputs the unconditional down control signal UCDN with ' HIGH' level to

discharge the charge pump 40 so as to prevent the delay locked loop from

being in a state that it is not locked to the input clock signal RCLK as shown

in FIG. 3b. As the output voltage level of the charge pump 40 decreases, the

quantity of delay of the voltage-controlled delay line 10 increases to the range of T/2—3T/2 where the quantity of delay can be controlled through the

up or down control signal UP or DN.

FIG. 7 is a circuit diagram showing the internal construction of the

phase and frequency detector 30 shown in FIG. 4. Referring to FIG. 7, the

phase and frequency detector 30 includes third and fourth D-flip flops 31

and 32, first and second delay means 33 and 34. The third D-flip flop 31

receives the input clock signal RCLK through its clock input port. The reset

terminal of the third D-flip flop 31 is connected to the output port of the first

delay means 33 consisting of a plurality of inverters 33ι to 33₄ and its signal

input port is provided with internal operation voltage V_DD- The fourth D-flip

flop 32 accepts the output clock signal DCLK of the voltage-controlled delay

line 10 through its clock input port. The reset terminal of the fourth D-flip

flop 32 is connected to the output port of the second delay means 34

consisting of a plurality of inverters 34ι to 34₄ and its signal input port is

provided with the internal operation voltage V_DD- The first delay means 33

receives the output clock signal DCLK of the voltage-controlled delay line 10

through its input port, and the second delay means 34 accepts the input

clock signal RCLK through its input port. In FIG. 7, each of the first and

second delay means 33 and 34 is constructed of even-numbered inverters. The input clock signal RCLK is supplied to the third D-flip flop 31 as its operation clock and delayed by a predetermined period of time through

the second delay means 34 to be applied to the reset terminal of the fourth

D-flip flop 32. The third D-flip flop 31 outputs the up control signal UP to the

charge pump 40. The output clock signal DCLK of the voltage-controlled

delay line 10 is supplied to the fourth D-flip flop 32 as its operation clock

and delayed by a predetermined period of time through the first delay means

33 to be applied to the reset terminal of the third D-flip flop 31 . The fourth

D-flip flop 32 outputs the down control signal DN to the charge pump 40. In the above-described construction, when the input clock signal

RCLK is prior to the output clock signal DCLK of the voltage-controlled delay

line 10, the up control signal UP that is the output signal of the third D-flip

flop 31 becomes ' HIGH' level at the rising edge of the input clock signal

RCLK and the third D-flip flop 31 is reset at the rising edge of the output

clock signal DCLK of the voltage-controlled delay line 10 to convert the up

control signal UP into ' LOW' level. Here, the phase and frequency

detector 30 outputs the up control signal UP having ' HIGH' level for a

period of time corresponding to the sum of the delay time of the first delay

means 33 and the phase difference between the input clock signal RCLK and

the output clock signal DCLK. In the case that the output clock signal DCLK of the voltage- controlled delay line 10 is followed by the input clock signal RCLK, the down

control signal DN that is the output signal of the fourth D-flip flop 32

becomes a ' HIGH' level at the rising edge of the output clock signal DCLK

and the fourth D-flip flop 32 is reset at the rising edge of the input clock

signal RCLK, to convert the down control signal DN into ' LOW' level. Here,

the phase and frequency detector 30 outputs the down control signal DN

having ' HIGH' level for a period of time corresponding to the sum of the

delay time of the second delay means 34 and the phase difference between

the input clock signal RCLK and the output clock signal DCLK. If the phase and frequency detector 30 does not have the first and

second delay means 33 and 34 and the phase difference between the input

clock signal RCLK and output clock signal DCLK is smaller than setup-hold

time of the third and fourth D-flip flops 31 and 32, the third and fourth D-flip

flops 31 and 32 have no variation in their output signals. Thus, the phase and

frequency detector 30 cannot output the up or down control signal UP and

DN although there is a phase difference between the input clock signal RCLK

and the output clock signal DCLK.

To solve this problem, the phase and frequency detector 30

according to the present invention is constructed in such a manner that

additional delay means are respectively connected to the third and fourth D- flip flops 31 and 32 to satisfy the setup-hold time of the D-flip flops so as to

detect even a minute phase difference (tens picosecond, for instance)

between the input clock signal RCLK and the output clock signal DCLK. It is

also possible to use a general phase and frequency detector in the case that

an electronic appliance to which the delay locked loop according to the

present invention is applied does not require detection of a minute phase

difference.

The charge pump 40 shown in FIG. 4 charges/discharges electrical

charges in response to up/down control signal UP and DN having ' HIGH'

level, for example, supplied from the phase and frequency detector 30 to

increase/decrease the output voltage level thereof. When the charge pump

40 is provided with the unconditional up or down control signal UCUP or

UCDN having ' HIGH' level, for instance, from the clock position detector

20, it charges/discharges electrical charges irrespective of the signal level of

the up/down control signal to increase/decrease the output voltage level

thereof. By doing so, the charge pump 40 prevents the delay locked loop

from operating erroneously when the quantity of delay of the voltage-

controlled delay line 10 is more than 3T/2 of the input clock signal RCLK or

less than T/2. The operation of the delay locked loop of the present invention in accordance with the quantity of delay of the voltage-controlled delay line 10

is explained in more detail with reference to waveforms shown in FIGs. 8a,

8b and 8c.

FIG. 8a shows the waveforms of output signals of the phase and

frequency detector 30 when the quantity of delay of the voltage-controlled

delay line 10 is in the range from T/2 to 3T/2. In this case, the phase and

frequency detector 30 shown in FIG. 4 detects the phases of the input clock

signal RCLK and output clock signal DCLK, and outputs the up control signal

UP having ' HIGH' level when it judges that the phase of the input clock

signal RCLK is prior to the phase of the output clock signal DCLK. The

charge pump 40 charges electrical charges to increase the output voltage

level thereof while the ' HIGH' up control signal UP is continuously applied

thereto.

The loop filter 5 shown in FIG. 4 filters high-frequency components of

the voltage signal output from the charge pump 40. The voltage-current

converter 6 outputs the delay control signals CTP and CTN according to the

filtered voltage signal to reduce the quantity of delay of the voltage-

controlled delay line 10 so as to lock the output clock signal DCLK to the

point of time corresponding to 1T of the input clock signal RCLK, thereby

obtaining desired multi-phase clocks CLKi to CLKN. The phase and frequency detector 30 outputs the down control signal

DN having ' HIGH' level when it judges that the phase of the input clock

signal RCLK follows the phase of the output clock signal DCLK. The charge

pump 40 discharges electrical charges to decrease the output voltage level

thereof while the ' HIGH' down control signal DN is continuously applied

thereto. The voltage-current converter 6 outputs the delay control signals

CTP and CTN to increase the quantity of delay of the voltage-controlled

delay line 10 so that the output clock signal DCLK is locked to the point of

time corresponding to 1T of the input clock signal RCLK, to produce desired

multi-phase clocks CLKi to CLKN.

FIG. 8b shows the waveforms of output signals of the phase and

frequency detector 30 when the quantity of delay of the voltage-controlled

delay line 10 is more than 3T/2. In the case that the rising edge of the output

clock signal DCLK is prior to the rising edge of the input clock signal RCLK,

as shown in FIG. 8b, the phase and frequency detector 30 outputs the down

control signal DN. At this time, the Jth clock signal CLKj of the voltage-

controlled delay line 10 is at ' LOW' level at the falling edge of the input

clock signal RCLK, which makes the output signal of the first D-flip flop 21

of the clock position detector 20, shown in FIG. 6, have ' LOW' level. The

inverter 24 inverts this ' LOW' level signal to output the unconditional up signal UCUP having ' HIGH' level to the charge pump 40.

The charge pump 40 charges electrical charges in response to the

unconditional up control signal irrespective of the down control signal DN

output from the phase and frequency detector 30 to increase the output

voltage level thereof. This reduces the quantity of delay of the voltage-

controlled delay line 10 so that the output clock signal DCLK of the voltage-

controlled delay line 10 comes within 3T/2 of the input clock signal RCLK.

Subsequently, the delay locked loop operates in the same manner as the

operation shown in FIG. 8a so that the output clock signal DCLK is locked to

the input clock signal RCLK (Δ=T), being delayed by 1T of the input clock

signal RCLK. The delay locked loop outputs multi-phase clocks CLKi to CLKN

at a frequency that is not locked to harmonics of the input clock signal RCLK.

In the case that the rising edge of the input clock signal RCLK is

followed by the rising edge of the output clock signal DCLK (Δ>2T) in FIG. 8b,

the phase and frequency detector 30 outputs the up control signal UP. In this

case, the Jth clock signal CLKj of the voltage-controlled delay line 10 is at

LOW' level at the falling edge of the input clock signal RCLK, which

makes the output signal of the first D-flip flop 21 of the clock position

detector 20, shown in FIG. 6, have ' LOW' level. The inverter 24 inverts this

' LOW' level signal to output the unconditional up signal UCUP having HIGH' level to the charge pump 40. Consequently, the output clock signal

DCLK of the voltage-controlled delay line 10 comes within 3T/2 of the input

clock signal RCLK so that desired multi-phase clocks CLKi to CLKN can be

obtained. FIG. 8c shows the waveforms of output signals of the clock position

detector 20 and the phase and frequency detector 30 when the quantity of

delay of the voltage-controlled delay line 10 is less than T/2. In this case,

though the phase and frequency detector 30 outputs the up control signal UP,

the Jth and Kth clock signals CLKj and CLKK of the voltage-controlled delay

line 10 are at ' HIGH' level at the falling edge of the input clock signal

RCLK, which makes the output signals of the first and second D-flip flops 22

of the clock position detector 20, shown in FIG. 6, have ' LOW' level. The

NAND gate 23 performs a logical operation to output a ' LOW' level

signal when the ' HIGH' level output signals of the first and second D-flip

flops 21 and 22 is input to its input terminals and the inverter 25 inverts this LOW' level signal to output the unconditional up signal UCUP having

' HIGH' level to the charge pump 40.

The charge pump 40 discharges electrical charges in response to the

unconditional down control signal UCDN irrespective of the up control signal

UP output from the phase and frequency detector 30 to decrease the output voltage level thereof. This reduces the quantity of current of the delay control

signals CTP and CTN to increase the quantity of delay of the voltage-

controlled delay line 10. Thus, the output clock signal DCLK of the voltage-

controlled delay line 10 is delayed by more than T/2 of the input clock signal

RCLK. Subsequently, the delay locked loop operates in the same manner as

the operation shown in FIG. 8a so that the output clock signal DCLK is

locked to the input clock signal RCLK (Δ=T), being delayed by 1T of the input

clock signal RCLK. The delay locked loop outputs multi-phase clocks CLKi

to CLKN at a frequency that is not locked to harmonics of the input clock

signal RCLK.

In the conventional PLL or D/PLL using the voltage-controlled

oscillator, noise and jitter are gradually increased due to integration

characteristic of the voltage-controlled oscillator. Furthermore, mismatch of

the voltage-controlled delay line and voltage-controlled oscillator, caused by

variations in temperature and process, prevents the delay locked loop from

being locked to the point of time corresponding to 1T of the input clock

signal RCLK to result in deterioration in jitter characteristic. This decreases

characteristic of the generated multi-phase clocks so that high-speed data

communication is difficult to perform. On the other hand, the present

invention uses the clock position detector instead of the voltage-controlled oscillator to eliminate deterioration in jitter characteristic due to variations in

temperature and process and remove noise and jitter generated when the

voltage-controlled oscillator is used, producing stabilized multi-phase clocks.

This facilitates high-speed data communication. According to experiments

carried out by the applicant, the delay locked loop of the present invention

performs stabilized synchronization operation for an input frequency variation

of maximum four times without using the voltage-controlled oscillator and

has good jitter characteristic of less than 50ps for 200MHz clock, for

example.

Industrial Applicability

As described above, the present invention constructs a delay locked

loop without a voltage-controlled oscillator and prevents multi-phase clocks

from being locked to harmonics of an input clock signal so that stabilized

multi-phase clocks can be produced. Furthermore, the present invention

improves jitter characteristic for a variation in temperature and process and

provides a delay locked loop useful to a chip that has a wide input dynamic

range and is required a large variation in data clock rate and a fast data

transmission rate. While the present invention has been described with reference to the particular illustrative embodiments, it is not to be restricted by the

embodiments but only by the appended claims. It is to be appreciated that

those skilled in the art can change or modify the embodiments without

departing from the scope and spirit of the present invention.

Claims

What Is Claimed Is:

1 . A delay locked loop for generating multi-phase clocks without a

voltage-controlled oscillator, comprising: a clock delay means having a plurality of delay means for sequentially

delaying an input clock signal, to output the multi-phase clocks; a phase detector for detecting a phase difference between the input

clock signal and an output clock signal of the clock delay means, to output a

predetermined control signal for controlling the quantity of delay of the clock

delay means; and a clock position detector for detecting a delay point of a clock signal

output from the clock delay means, to output a control signal for controlling

the quantity of delay of the clock delay prior to the phase detector.

2. The delay locked loop as claimed in claim 1 , wherein the clock

position detector receives at least two clocks among the multi-phase clocks

from the clock delay means at a specific interval within one period of the

input clock signal and detects delay points of the clocks.

3. The delay locked loop as claimed in claim 1 , wherein the quantity of delay of the clock delay means increases or decreases according to a

voltage level of the control signal output from the phase detector when the

quantity of delay is in the range of T/2 to 3T/2 of the input clock signal, and

it increases or decreases according to a voltage level of the control signal

output from the clock position detector when it is less than T/2 or more than

3T/2 of the input clock signal.

4. The delay locked loop as claimed in claim 1 , wherein the phase

detector includes predetermined delay means that is connected to the signal

input port of the phase detector to detect a phase difference between

signals input to the phase detector, which is smaller than a setup-hold time

of internal circuit elements of the phase detector.

5. A delay locked loop for generating multi-phase clocks without a

voltage-controlled oscillator, comprising: a voltage-controlled delay line for controlling the quantity of delay of

an input clock signal on the basis of the quantity of current of a first control

signal applied thereto, to output first to Nth clock signals that are sequentially

delayed; a clock position detector for performing a logical operation for at least two of the first to Nth clock signals, to output a second control signal for

controlling the quantity of delay of the voltage-controlled delay line; a phase and frequency detector for comparing the phase of one of

the output clock signals of the voltage-controlled delay line with the phase

of the input clock signal, to output a third control signal for controlling the

quantity of current of the first control signal; a charge pump for charging or discharging electrical charges

according to signal levels of the third control signal and the second control

signal prior to the third control signal and outputting a voltage signal

corresponding to the quantity charged or discharged electrical charges; a loop filter for filtering high-frequency components of the voltage

signal output from the charge pump; and a voltage-current converter for outputting the first control signal

corresponding to rising/falling state of an output voltage level of the loop

filter.

6. The delay locked loop as claimed in claim 5, wherein the clock

position detector receives at least two of the first to Nth clocks at a specific

interval within one period of the input clock signal to detect a delay point of

the Nth clock .

7. The delay locked loop as claimed in claim 6, wherein the clock

position detector detects the delay point of the Nth clock in response to the

falling edge of the input clock signal.

8. The delay locked loop as claimed in claim 5, wherein the quantity

of delay of the voltage-controlled delay line increases or decreases

according to a voltage level of the third control signal when the quantity of

delay is in the range of T/2 to 3T/2 of the input clock signal, and it increases

or decreases according to a voltage level of the second control signal when

it is less than T/2 or more than 3T/2 of the input clock signal.

9. The delay locked loop as claimed in claim 5, wherein the voltage-

controlled delay line consists of sequentially connected first to Nth inverters,

and Jth and Kth clock signals output from Jth and Kth inverters among the

first to Nth inverters are provided to the clock position detector as its input

signals, the Jth clock signal being selected within the range of T/4 to T/2 of

the input clock signal, the Kth clock signal being selected within the range of

T/2 to 3T/4 of the input clock signal.

10. The delay locked loop as claimed in claim 9, wherein the clock

position detector comprises: first and second D-flip flops that respectively receive the Jth and Kth

clock signal through their input ports and respectively accept the input clock

signal through their inverted clock input ports; a NAND gate whose input ports are respectively connected to the

output ports of the first and second D-flip flops; and inverters that are respectively connected to the output port of the first

D-flip flop and the output port of the NAND gate.

1 1. The delay locked loop as claimed in claim 5, wherein the phase

and frequency detector comprises: a third D-flip flop whose clock input port is provided with the input

clock signal, the reset terminal of the third D-flip flop being connected to the

output port of a first delay means, the signal input port of the third D-flip flop

being provided with internal operation voltage; the first delay means receiving the output clock signal of the voltage-

controlled delay line through its input port; a fourth D-flip flop whose clock input port is provided with the output

clock signal of the voltage-controlled delay line, the reset terminal of the fourth D-flip flop being connected to the output port of a second delay

means, the signal input port of the fourth D-flip flop being provided with the

internal operation power; and the second delay means accepting the input clock signal through its

input port.