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WO2005005142A1 - Conductive sheet having more than one through hole or via hole - Google Patents

Conductive sheet having more than one through hole or via hole Download PDF

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Publication number
WO2005005142A1
WO2005005142A1 PCT/JP2004/009424 JP2004009424W WO2005005142A1 WO 2005005142 A1 WO2005005142 A1 WO 2005005142A1 JP 2004009424 W JP2004009424 W JP 2004009424W WO 2005005142 A1 WO2005005142 A1 WO 2005005142A1
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WO
WIPO (PCT)
Prior art keywords
conductive layer
insulating substrate
conductive
hole
back surfaces
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2004/009424
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French (fr)
Japanese (ja)
Inventor
Shigeki Miura
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FCM Co Ltd
Original Assignee
FCM Co Ltd
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Filing date
Publication date
Application filed by FCM Co Ltd filed Critical FCM Co Ltd
Publication of WO2005005142A1 publication Critical patent/WO2005005142A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838Geometry or layout
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01QANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00Details of, or arrangements associated with, antennas
    • H01Q1/36Structural form of radiating elements, e.g. cone, spiral, umbrella; Particular materials used therewith
    • H01Q1/38Structural form of radiating elements, e.g. cone, spiral, umbrella; Particular materials used therewith formed by a conductive layer on an insulating support
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • H05K1/115Via connections; Lands around holes or via connections
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/09654Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/0979Redundant conductors or connections, i.e. more than one current path between two points

Definitions

  • the present invention relates to a conductive sheet. More specifically, the present invention relates to a conductive sheet that can be suitably used for substrates for semiconductors, circuit boards for electric and electronic components, various packaging, automobile parts, solar cells, antenna circuit boards, IC cards, and the like.
  • the conductive sheet having such a configuration needs to adhere the insulating substrate and the copper foil with high adhesiveness.
  • an adhesive is applied to the insulating substrate to bond the copper foil, Alternatively, it was manufactured by applying an adhesive to a copper foil and bonding it to an insulating substrate.
  • various adhesives are selected, or copper particles are adhered to the copper foil surface to form irregular projections. Have been tried.
  • the adhesion between the two can be improved to some extent by these methods, the following problems have been pointed out in any of the above methods with the refinement of circuit patterns.
  • the applied thickness is 1030 ⁇ m, regardless of the type of the adhesive, and the overall thickness of the conductive sheet is large. Become.
  • the adhesive layer may hinder the etching.
  • copper particles are adhered to the surface of the copper foil to form projections and depressions, the particles may prevent finer circuit patterns.
  • Patent Document 1 Japanese Patent Application Laid-Open No. 4-286394
  • Patent Document 2 JP-A-11-307933
  • Patent Document 3 JP-A-11-298104
  • Patent Document 4 JP-A-5-327229
  • Patent Document 5 JP-A-5-267806
  • Patent Document 6 JP-A-4-314395
  • Patent Document 7 JP-A-2-142198
  • Patent Document 8 JP-A-2-21507
  • Patent Document 9 JP-A-63-177586
  • Patent Document 10 JP-A-62-226689
  • Patent Document 11 JP-A-53-140570
  • Patent Document 12 JP-A-59-228789
  • Patent Document 13 JP-A-51-60997
  • the present invention has been made in view of the above situation, and an object of the present invention is to improve the adhesion between the insulating substrate and the conductive layer and make the circuit pattern finer. Another object of the present invention is to provide a conductive sheet. Means for solving the problem
  • a conductive layer is directly formed on both the front and back surfaces of an insulating substrate, and one or more conductive layers present on both the front and back surfaces are opened so as to penetrate the insulating substrate.
  • a conductive sheet electrically connected to a conductive layer present on the other surface through a through hole or via hole provided on the other surface of the insulating substrate. At least one conductive layer that is not electrically connected to the layer is formed.
  • the first conductive layer is formed by sputtering or vapor deposition.
  • a second conductive layer formed by an electroless plating method or an electroplating method.
  • a conductive layer is directly formed on both front and back surfaces of an insulating substrate, and one or more conductive layers present on both front and back surfaces are opened so as to penetrate the insulating substrate.
  • At least one conductive layer not electrically connected to another conductive layer is formed, and the conductive layer includes a conductive layer not electrically connected to a conductive layer present on the other surface.
  • At least one anchor hole that is opened so as to penetrate the insulating substrate in a substantial portion of the insulating substrate on which at least one of the conductive layers is formed; Is connected to the conductive layer on the other side With conductive layer is Hama charge connected to it nag and either a conductive layer on the wall surface or within, the second conductive layer is formed by the sputtering method or the vapor deposition method
  • It is characterized by including one conductive layer and a second conductive layer formed by an electroless plating method or an electroplating method.
  • the anchor holes have different opening areas on both the front and back surfaces of the insulating substrate.
  • an anchor layer for the purpose of improving adhesion to the insulating substrate is not provided for the purpose of electrical connection, but is provided on the other side via the anchor hole. Is preferably connected to the conductive layer on the surface.
  • the present invention also relates to a semiconductor product, an electric product, an electronic product, an automobile, a solar cell, an antenna circuit board, or an IC card using the conductive sheet.
  • the conductive sheet of the present invention has both improved adhesion between the insulating substrate and the conductive layer and finer circuit patterns, and has highly reliable electrical connectivity. It has excellent production efficiency and dimensional accuracy. [0013] Therefore, the conductive sheet of the present invention is applied to a wide range of uses such as a substrate for semiconductors, a circuit board for electric and electronic parts, various packaging, an automobile part, a solar cell, an antenna circuit board, and an IC card. be able to. That is, the conductive sheet can form a plurality of circuit patterns in a continuous form without being cut or cut into a certain size, and can be used for the above-mentioned various applications.
  • FIG. 1 is a schematic sectional view of a conductive sheet of the present invention.
  • FIG. 2 is a schematic plan view of a conductive sheet of the present invention.
  • FIG. 3A is a schematic sectional view of an anchor hole having a conductive layer on a wall surface like a through hole.
  • FIG. 3B is a schematic sectional view of an anchor hole in which a conductive layer is filled like a via hole.
  • FIG. 3C is a schematic cross-sectional view of an anchor hole having different opening areas on both front and back surfaces of an insulating substrate.
  • the conductive sheet 1 of the present invention has an insulating substrate 2 in which conductive layers 3 are directly formed on both front and back surfaces, and one or more conductive layers 3 present on both front and back surfaces are formed on the insulating substrate 2.
  • 2 is electrically connected to the conductive layer 3 present on the other surface through a through hole or a via hole 4 that is opened so as to penetrate through the through hole 2 as shown in FIG.
  • the insulating substrate 2 has a structure in which at least one or more conductive layers 3a that are not electrically connected to other conductive layers 3b and 3c on the same surface are formed on both front and back surfaces.
  • FIG. 1 is a schematic sectional view of a portion where the conductive layer 3a of FIG. 2 is formed.
  • the conductive sheet of the present invention having such a configuration is suitable for a substrate for a semiconductor, a circuit board for electric and electronic parts, various packaging, an automobile part, a solar cell, an antenna circuit board, an IC card, and the like. Can be used. Therefore, the present invention also relates to various semiconductor products, electric products, electronic products, automobiles, solar cells, antenna circuit boards, or IC cards using such a conductive sheet.
  • a conductive sheet of the present invention will be described.
  • any conventionally known substrate that can be used for this kind of application can be used without any particular limitation.
  • a film having a small thickness is preferable. This is because it is suitable for forming a conductive layer to be described later and can be processed into a long continuous material such as a roll, thereby improving production efficiency.
  • Examples of such an insulating substrate include polyesters such as PET and PEN, polyimides, aramides, polysulfones, polyetherimides, polyphenylene oxides, liquid crystal polymers, glass fiber reinforced epoxy resins, and phenols.
  • polyesters such as PET and PEN
  • polyimides such as PET and PEN
  • aramides such as PET and PEN
  • polysulfones such as polysulfones
  • polyetherimides such as polyphenylene oxides
  • liquid crystal polymers such as polyimide glass fiber reinforced epoxy resins
  • phenols phenols.
  • the ability to name films such as resins and acrylic resins.
  • the film referred to here is preferably a film having a thickness of 4-1300 ⁇ , preferably about 12-50 ⁇ m. If it is less than 4 / im, the strength may be too weak to be processed, and if it exceeds 300 / im, it may hinder the formation of a conductive layer for through holes, via holes, or anchor holes as described later. Because there is.
  • the shape of the insulating substrate is particularly suitable for a film-like force.
  • a continuous form is acceptable.
  • the through hole is such that it physically penetrates the front and back of the insulating substrate.
  • the conductive layers formed on both the front and back surfaces of the insulating substrate can be electrically connected to each other through the through holes.
  • a conductive layer described later after forming the through hole in the insulating substrate. This makes it possible to integrally form the conductive layers on both the front and back surfaces of the insulating substrate and the conductive layers in the through holes, thereby contributing to an improvement in production efficiency and a highly reliable electrical connection. Can be guaranteed.
  • the shape of such a through hole is not particularly limited as long as it penetrates the front and back surfaces of the insulating substrate.
  • the through hole may have a circular or polygonal cross section.
  • the through hole preferably has an inner diameter of 5 to 300 zm, preferably 10 to 200 zm. If the inner diameter is less than 5 xm, drilling becomes difficult and the processing cost increases, and if it exceeds 300 ⁇ m, the diameter of the through hole becomes too large with respect to the length of the conductive layer in the width direction, and effective circuit space is secured. And problems with electrical connections. Therefore, it is more advantageous in circuit design to form the through hole with a smaller inside diameter without increasing the processing cost.
  • such through holes are formed in an amount of 2 or more, preferably 2 to 5, more preferably 2 to 3, for each conductive layer present in the form of an island on the surface of the insulating substrate. It is preferably formed in a substantial part of the insulating substrate described above. If only one through hole is formed for each conductive layer present in the shape of an island, there is a problem in the adhesion between the conductive layer and the insulating substrate, and also a problem in the electrical connectivity. is there. If too many through holes are formed, the area of the through holes occupying the conductive layer becomes large, thereby reducing the degree of freedom in circuit design and the processing efficiency. It is preferable to make up to about 5 per hit.
  • an island-shaped conductive layer refers to each conductive layer that is not electrically connected to another conductive layer on the same surface on either of the front and back surfaces of the insulating substrate. ,And Umono.
  • At least on the front and back surfaces of the insulating substrate 2, at least a conductive layer 3a that is not electrically connected to other conductive layers 3b and 3c on the same surface is provided.
  • One or more of the conductive layers (in FIG. 2, at least the conductive layer 3a or the conductive layer 3a). It is preferable that two or more of the above-mentioned through holes are formed in a substantial part of the insulating substrate on which the layers 3b and 3c) are formed.
  • Such a through hole can be formed by any conventionally known hole forming method (drilling method) without any particular limitation.
  • hole forming method for example, CO laser,
  • Holes are formed so as to penetrate the insulating substrate by means of various lasers such as a YAG laser and an excimer laser, and drilling, punching, and pressing.
  • various lasers such as a YAG laser and an excimer laser
  • drilling, punching, and pressing it is preferable to open the hole by using various lasers.
  • the via hole in the present invention is a small hole provided so as to physically penetrate the front and back of the insulating substrate, and is formed on both the front and back surfaces of the insulating substrate through this via hole. Can be electrically connected to each other.
  • the via hole has the same function as the through hole, and the through hole takes a form in which a conductive layer is formed only on the wall surface and a hollow portion remains in the center.
  • the via hole is different in the form in that the inside of the hole is entirely filled with a conductive layer and has no hollow portion.
  • the conductive sheet of the present invention whether the conductive layers on the front and back surfaces of the insulating substrate are electrically connected through through holes or electrically connected through via holes depends on the shape of the circuit pattern, They can be arbitrarily selected depending on the size and the like, and both can be formed alone or in combination.
  • the via hole on the insulating substrate and then form the conductive layer described later.
  • the shape of such a via hole is not particularly limited as long as it penetrates the front and back of the insulating substrate.
  • the cross-sectional shape may be circular or polygonal.
  • the via hole has an inner diameter of 5-100 / im, preferably 10-25 / im. If the inner diameter is less than 5 / m, drilling becomes difficult and the processing cost increases, and if it exceeds 100 ⁇ , it takes a long time to fill the inside of the hole with the conductive layer, resulting in poor production efficiency. Will be. It should be noted that it is more advantageous in circuit design to form such via holes with a smaller inner diameter as long as the processing cost does not increase.
  • the number of such via holes is 2 or more, preferably 25, and more preferably 23 per conductive layer existing in the form of an island on the surface of the insulating substrate. It is preferably formed on a substantial portion of the insulating substrate. If only one via hole is formed for each conductive layer existing in the shape of an island, there is a problem in the adhesion between the conductive layer and the insulating substrate and also a problem in the electrical connectivity. is there. Also, if a large number of via holes are formed, the area of the via holes in the conductive layer becomes large, and the degree of freedom in circuit design is reduced, and the processing efficiency is also reduced. It is preferable to use up to about five per conductive layer. When the via hole is formed together with the through hole, the total number of both is preferably 2 or more, preferably 2-5, and more preferably 2-3.
  • the conductive layer existing in an island shape refers to the same conductive layer as described above. That is, as shown in FIG. 2, at least one or more conductive layers 3a that are not electrically connected to the other conductive layers 3b and 3c on the same surface are provided on both front and back surfaces of the insulating substrate 2. In a substantial portion of the insulating substrate where one or more of the conductive layers (in FIG. 2, at least the conductive layer 3a or the conductive layers 3b and 3c) are formed, two or more of the via holes are formed. It is preferable to By forming two or more via holes per conductive layer existing in an island shape in this way, the conductive layer increases the reliability with respect to the electrical connectivity and the adhesion to the insulating substrate. Enhanced.
  • Such a via hole can be opened by any conventionally known opening method (drilling method) without any particular limitation.
  • opening method for example, CO laser,
  • Holes are formed by various lasers such as a YAG laser and an excimer laser so as to penetrate the insulating substrate.
  • the conductive layer of the present invention is formed directly on both the front and back surfaces of the insulating substrate, and one or more conductive layers existing on both the front and back surfaces are opened so as to penetrate the insulating substrate. It is electrically connected to the conductive layer on the other surface via via holes (see Fig. 1). Further, at least one or more conductive layers that are not electrically connected to other conductive layers on the same surface are formed on both front and back surfaces of the insulating substrate (see FIG. 2). As described above, two or more through holes or via holes are formed in a substantial portion of the insulating substrate on which one or more are formed.
  • the conductive layer of the present invention may include a conductive layer that is not electrically connected to the conductive layer present on the other surface of the insulating substrate. Can be included. That is, the conductive layer may include those in which a through hole or a via hole is not formed in a substantial portion of the insulating substrate on which the conductive layer is formed. Therefore, both the through hole or the via hole and the anchor hole may be included. Some are formed, and some are formed only one of them.
  • Such a conductive layer is formed directly on both the front and back surfaces of the insulative substrate, and also formed on the wall surface of the through hole or the like (including an anchor hole to be described later, the same applies hereinafter). (The same applies to the following), which is formed so as to fill the inside. Further, the conductive layer is formed so as to have the same configuration on the wall surface such as the through hole or the inside of the via hole and the front and back surfaces of the insulating substrate.
  • the conductive layer is formed directly on the insulating substrate means that the conductive layer is formed so as to be in direct contact with the insulating substrate without using an adhesive or the like. It is formed so as to be in direct contact with the insulating substrate not only on the front and back surfaces but also in through holes and via holes.
  • the present invention has succeeded in solving various problems caused by the use of the adhesive in the related art, and in particular, has enabled finer circuit patterns.
  • the conductive layers on the front and back surfaces of such an insulating substrate are electrically connected to each other through through holes or via holes.
  • the term “electrically connected through through holes” specifically means In general, the conductors directly formed on the front and back surfaces of the insulating substrate This means that the conductive layer is electrically connected by the conductive layer of the same configuration formed on the wall surface of the through hole.
  • the term “electrically connected via the via hole” means that the conductive layer formed directly on the front and back surfaces of the insulating substrate is electrically connected by the conductive layer of the same configuration filled inside the via hole. It means connected.
  • the conductive layer on the wall surface of the through hole or the conductive layer filling the inside of the via hole and the conductive layer on the front and back surfaces of the insulating substrate have the same configuration, highly reliable electrical connection is possible. It becomes.
  • composition of such a conductive layer is not particularly limited as long as it has an electric conductivity function.
  • Cu, Ni, Cr, Ag, Au, Zn, Ti, Pd, Sn, Bi And at least one metal selected from the group consisting of Co and Co or an alloy containing at least one of the above metals and may be formed as a single layer, and may have the same composition or different compositions. Can be formed by laminating a plurality of layers.
  • the conductive layer has the same configuration on the wall surface such as a through hole or the inside of a via hole and on the front and back surfaces of the insulating substrate means that the above-mentioned laminated state is the same, It does not necessarily mean that the thicknesses of the layers are the same.
  • the conductive layer is formed in the same step on the wall surface of the through hole or inside the via hole and on both the front and back surfaces of the insulating substrate.
  • a method of forming in the same step will be described later.
  • Such a conductive layer can include a first conductive layer formed by a sputtering method or a vapor deposition method, and a second conductive layer formed by an electroless plating method or an electroplating method.
  • the first conductive layer and the second conductive layer may be formed as a single layer or a plurality of layers, respectively, to form a conductive layer.
  • the first conductive layer of the present invention is formed directly on the insulating substrate, and the above-mentioned metal or an alloy containing at least one metal, more preferably Cu, Ag, Sn, Ni, Cr, Co and T can be formed by sputtering or vapor deposition of at least one metal selected from Zn or an alloy containing at least one metal.
  • This first conductive layer has a function as a so-called underlayer for forming a second conductive layer described later. And has the function of improving the adhesion of the second conductive layer to the insulating substrate.
  • Such a first conductive layer is preferably formed to a thickness of 500 to 5000A, preferably 1000 to 3000A. If it is less than 500 A, the effect of improving the adhesion of the second conductive layer described later cannot be sufficiently exhibited, and even if it exceeds 5000 A, the adhesion of the second conductive layer will not be substantially different and disadvantageously in terms of cost. .
  • such a first conductive layer can be formed by forming one layer (single layer) or by laminating two or more layers (a plurality of layers). The ability to have
  • At least one metal selected from Ni, Cr, Ti, Zn, or Co or an alloy containing at least one metal on the insulating substrate Are laminated, and at least one metal selected from Cu, Ag, Sn or Zn or an alloy containing at least one metal is preferably laminated.
  • the above-mentioned at least one metal selected from Cu, Ag, Sn or Zn or an alloy containing at least one such metal has good electrical properties and excellent adhesion to the second conductive layer,
  • it is relatively inexpensive it is advantageous to use it for such an application, but it has a problem that it is easily oxidized and the electric characteristics are impaired. Therefore, in order to solve this oxidation problem, at least an oxidation-resistant metal such as Ni, Cr, Ti, Zn or Co selected under such a layer (ie, between the insulating substrate).
  • an oxidation-resistant metal such as Ni, Cr, Ti, Zn or Co selected under such a layer (ie, between the insulating substrate).
  • the thickness of such a layer made of a metal having oxidation resistance is preferably 10 to 200A, more preferably 3070A. If it is less than 10 A, the effect of oxidation resistance may not be sufficiently exhibited, and if it exceeds 200 A, etching may be difficult when forming a circuit pattern.
  • the second conductive layer of the present invention is formed on the first conductive layer, and as the conductive layer, the metal described above or an alloy containing at least one metal, more preferably Cu, Ag, Sn, Ni, and B are formed by applying at least one metal selected from Zn or an alloy containing at least one metal by an electroless plating method or an electroplating method.
  • the metal described above or an alloy containing at least one metal more preferably Cu, Ag, Sn, Ni, and B are formed by applying at least one metal selected from Zn or an alloy containing at least one metal by an electroless plating method or an electroplating method.
  • Cu is particularly preferred, and those formed by electroplating copper sulfate are particularly preferred. This is because it is inexpensive, has high reliability in electrical connection, and has excellent production efficiency.
  • Such a second conductive layer mainly has an effect of imparting electric conductivity and mechanical strength by being formed thicker than the first conductive layer.
  • the second conductive layer since the second conductive layer has electrical conductivity, it can also function as a capacitor if it is arranged so as to face both sides of the insulating substrate.
  • Such a second conductive layer is preferably formed with a thickness of 0.550 x m, preferably 4-1 38zm. If it is less than 0, there is a problem that sufficient electrical conductivity cannot be obtained and the electrical resistance becomes too large. Even if it exceeds 50 ⁇ m, there is no significant difference in electrical conductivity, which is disadvantageous in cost.
  • such a second conductive layer can be formed as a single layer (single layer) or a laminate of two or more layers (a plurality of layers). The ability to have
  • the second conductive layer is preferably formed by using an electroplating method when forming a relatively thick layer, and an electroless plating method when forming the second conductive layer relatively thin. It is preferable to adopt and form.
  • the anchor hole in the present invention is a force that is a small hole provided so as to physically penetrate the front and back of the insulating substrate. Unlike the above-described through hole or via hole, the conductive layer is formed through the anchor hole. There is no electrical connection with the conductive layer present on the other surface of the insulating substrate.
  • Such an anchor hole has a function of improving the adhesion of the conductive layer to the insulating substrate by having a conductive layer on the wall surface or filling the inside with the conductive layer.
  • the conductive layer 3 can be formed on the wall surface of the anchor hole 5 like a through hole, and as shown in FIG. 3B.
  • the inside of the anchor hole 5 can be filled with the conductive layer 3 like a via hole.
  • the conductive layer after forming the anchor hole in the insulating substrate as in the case of the through hole and the via hole described above.
  • the shape of such an anchor hole is not particularly limited as long as it penetrates the front and back surfaces of the insulating base, but preferably the opening areas of the front and back surfaces of the insulating base are different. Is preferred. That is, as shown in FIG. 3C, the insulating area of the conductive layer is reduced by making the opening area of the surface on which the conductive layer is formed smaller than the opening area of the surface on which the conductive layer is not formed. The adhesion to the conductive substrate can be further improved.
  • the inner diameter of such an anchor hole is preferably 5 to 300 ⁇ m, and more preferably 10 to 200 ⁇ m. If the inner diameter is less than 5 / m, drilling becomes difficult and the processing cost increases, and if it exceeds 300 ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ , the diameter of the anchor hole becomes too large with respect to the length in the width direction of the conductive layer. Problems may occur in securing space and electrical connection. Therefore, it is more advantageous in terms of circuit design to form the inner diameter of the anchor hole as small as possible without increasing the processing cost.
  • an anchor hole is formed in an island shape on the surface of the insulative substrate at one or more, preferably one to thirty, more preferably three to ten, and more preferably three to ten, conductive layers. It is preferable to form and form a substantial part of the insulating substrate. If an anchor hole is not formed at all for each conductive layer existing in the shape of an island, there may be a problem in the adhesion between the conductive layer and the insulating substrate, and if too many anchor holes are formed, However, since the area of the anchor hole in the conductive layer increases, the degree of freedom in circuit design decreases, and the processing efficiency also decreases.Therefore, up to about 30 conductive layers per island-shaped conductive layer Les, which you prefer.
  • the conductive layer existing in an island shape means the same conductive layer as described above. That is, as shown in FIG. 2, on both front and back surfaces of the insulating substrate 2, the same surface is provided. At least one or more conductive layers 3a not electrically connected to the other conductive layers 3b and 3c are formed, and at least one of the conductive layers (in FIG. 2, at least the conductive layer 3a or the conductive layers 3b, 3c It is preferable that one or more of the anchor holes 5 are formed in a substantial portion of the insulating substrate on which the above ()) is formed.
  • Such an anchor hole can be opened by any conventionally known opening method (drilling method) without any particular limitation.
  • holes are formed so as to penetrate the insulating substrate by means of various lasers such as a CO laser, a YAG laser, an excimer laser, and the like, drills, punches, presses, and the like.
  • various lasers such as a CO laser, a YAG laser, an excimer laser, and the like, drills, punches, presses, and the like.
  • the inner diameter force of the through hole is smaller than 3 ⁇ 40 ⁇ , it is preferable to open the hole by using various lasers.
  • the anchor layer of the present invention is formed not for the purpose of electrical connection but for the purpose of improving the adhesion of the conductive layer to the insulating substrate. As shown in FIGS. 3A and 3B, the anchor layer 6 is connected to a conductive layer existing in the same plane as the force connected to the conductive layer 3 on the other surface via the anchor hole 5. None.
  • Such an anchor layer has the same composition and the same laminated structure as the conductive layer (may have the same composition and thickness as the first conductive layer and the second conductive layer). After the anchor holes are formed, it is preferable that the holes are formed in the same step as the conductive layer, and then formed by etching or the like so as to be insulated from the conductive layer in the same plane. Note that a detailed method for forming the conductive layer will be described below.
  • the conductive layer according to the present invention is characterized in that, after a through hole, a via hole or an anchor hole is formed in the insulating substrate, the front and back surfaces of the insulating substrate and the wall surfaces of the through hole and the like (including anchor holes, the same applies hereinafter). Or via holes (including anchor holes, hereinafter the same) It is preferable that they are formed in the same step inside the same step. This makes it possible to integrally form the conductive layers on both the front and back surfaces of the insulating substrate and the conductive layers inside the wall surfaces such as through holes or via holes, thereby contributing to the improvement of production efficiency. Reliable electrical connections can be guaranteed. It also contributes to improving the adhesion between the conductive layer and the insulating substrate.
  • the conductive layer is formed in the same step means that the conductive layer is formed simultaneously and integrally on both the front and back surfaces of the insulating substrate and the wall surface such as the through hole or the inside of the via hole. It is meant that it is formed in a typical way.
  • the conductive layer includes a first conductive layer and a second conductive layer
  • first the first conductive layer is formed on both the front and back surfaces of the insulative base and the wall surface such as the through hole or the inside of the via hole.
  • a second conductive layer is formed on the first conductive layer simultaneously by an electroless plating method or an electroplating method.
  • the first conductive layer is mainly formed on the wall surface of the via hole and formed on the first conductive layer.
  • the hole is filled with the second conductive layer to be filled, and the cavity is filled.
  • each layer is formed simultaneously and integrally as described above. As far as possible, the conductive layers are formed in the same step.
  • the conductive layer is formed by a sputtering method or a vapor deposition method
  • the front and back surfaces of the insulating substrate cannot be treated at one time due to the characteristics of a processing apparatus or the like, the front and rear surfaces are different.
  • the conductive layers on both the front and back surfaces and the conductive layers inside the wall surfaces such as through holes or via holes are formed in the same process.
  • the conductive layer inside the wall such as the through hole or the via hole is considered to be formed to the middle height (depth) of the hole by each of these two operations.
  • the above operation forms a conductive layer on the entire wall surface such as a through hole or via hole. Further, even if the conductive layer is weighted and stacked at the middle height (depth) portion of the hole, It is assumed that the configuration is the same as the configuration of the conductive layer on the surface of the insulating substrate.
  • a conductive layer is first formed on both the front and back surfaces of the insulating substrate, then a through hole or a via hole is opened, and then the through hole is formed again.
  • the number of steps for forming the conductive layer can be halved, thereby greatly improving the production efficiency.
  • the resilient force is integrally formed in the same process, a highly reliable connection effect can be obtained.
  • the conductive layer is formed so as to extend over the conductive layer.
  • the thickness of the conductive layer is weighted and formed, and when the thickness of the conductive layer on the insulating substrate is increased in this manner, processing for forming a circuit is difficult and dimensional accuracy itself is deteriorated.
  • the thickness of the conductive layer can be reduced as much as possible without the weight of the conductive layer being weighted, which contributes to finer circuit patterns. Dimensional accuracy may not deteriorate.
  • the conductive layer is not formed on both the front and back surfaces of the insulating substrate via the anchor hole, the conductive layer existing on the surface where the conductive layer is not formed is removed by etching or the like. You. Alternatively, a mask may be preliminarily applied to a corresponding portion of the anchor hole so that the conductive layer is not formed at that portion. Further, as described above, the anchor layer can be formed by leaving such a conductive layer partially instead of completely removing it by etching.
  • An alignment mark can be formed on the insulating substrate of the present invention.
  • the alignment mark serves as a reference for determining a predetermined position of a through hole, a via hole, and the like, and is usually formed at both ends of the insulating substrate (where a through hole, a via hole, and the like are provided, a position, and a position). It is suitable.
  • Such an alignment mark can determine a predetermined position such as a through hole or a via hole by optical, electronic, magnetic, visual, or other reading means. Any material may be used as long as it is formed, and the method of forming the material is not particularly limited. For example, in the case of visual reading, it is preferable that the alignment mark is formed by making holes at both ends of the insulating substrate so as to penetrate the substrate. The holes (referred to as alignment holes) are more preferably continuously opened at regular intervals. By adopting such a configuration, the position of the through hole can be more easily determined.
  • the size of such an alignment hole is usually preferably about 5 ⁇ m 3 mm, and the hole can be formed by various lasers, drills, punches, presses, or the like.
  • the hole is smaller than 80 x m, it is preferable to use various lasers.
  • a conductive layer is formed on the inner wall surface of such an alignment hole.
  • a bonding layer for an integrated circuit and an oxidation preventing layer can be formed on the conductive layer.
  • the integrated circuit bonding layer has a function of facilitating the mounting of the integrated circuit (IC chip or LSI) on the insulating substrate, and directly electrically connects the conductive layer to the integrated circuit. is there.
  • the antioxidant layer has a function of preventing the conductive layer from being oxidized and exhibiting no conductivity, or preventing poor adhesion to the insulating substrate.
  • Such a layer is preferably made of at least one metal selected from the group consisting of Sn, Ni, Au, Ag, Zn, and Cr, or an alloy containing at least one metal.
  • the thickness is preferably 0.2 to 15 zm, more preferably 0.5 to 5 zm. If it is less than 0.2 zm, the effect of easy mounting of integrated circuits will not be exhibited, and even if it exceeds 15 xm, the cost will be much higher than the effect of easy mounting of integrated circuits. Not preferred.
  • the thickness is preferably 0.012 ⁇ m, and more preferably 0.051 ⁇ m. If the value is less than 0.01 zm, the above-mentioned effects will not be exhibited, and if the value exceeds 2 xm, the cost will increase rather than the above-mentioned effects. It ’s not.
  • Such a layer may be formed as a single layer or a plurality of layers on the entire surface of the conductive layer or a portion such as a bump by any one of an electroless plating method, an electroplating method, and a chromate method. The ability to generate S.
  • a polyimide finolem (trade name: Avical, manufactured by Kanebo) having a thickness of 50 ⁇ , a width of 250 mm, and a length of 100 m was set on a CO laser processing machine (manufactured by Mitsubishi Electric). .
  • a 80-meter-diameter through-hole was passed through the polyimide film at a portion corresponding to the front end 9 of the conductive layer 3a by this processing machine. Holes were formed as one set (the distance between holes was 120 ⁇ m), and through holes were also formed in portions corresponding to predetermined positions of the conductive layer 3b.
  • anchor holes 5 each having an inner diameter of 50 ⁇ m were formed at two corresponding portions of the conductive layer 3a corresponding to the bent portions 7 so as to penetrate both sides of the polyimide film.
  • the distance is 100 ⁇ m
  • an anchor hole 5 having an inner diameter of 50 / im is formed in a portion corresponding to the soldered portion 8 of the conductive layer 3a so as to penetrate both sides of the polyimide film.
  • anchor holes 5 were similarly formed in portions corresponding to predetermined positions of conductive layers 3b and 3c.
  • the insulating substrate 2 that has been subjected to the opening treatment by the CO laser as described above is
  • the following treatment was carried out in order to remove the carbide formed in the hole and its periphery during the treatment. That is, the insulating substrate 2 was set in a dismirror apparatus, immersed in an immersion bath of a 50 g / 1 aqueous solution of potassium permanganate at a liquid temperature of 60 ° C. for 60 seconds, and washed with pure water five times. .
  • a neutralization treatment was further performed by immersing in a 4% sulfuric acid immersion bath at a liquid temperature of 40 ° C. for 2 minutes, and washing with pure water was repeated five times.
  • the high-performance filter Draining was performed with dry air at 105 ° C passed through (the size of the opening of the filter was 0.5 ⁇ m or less), and the carbides generated above were removed by sufficient drying. Thereafter, the insulating substrate 2 was taken out of the dismearing device.
  • one end of the insulating substrate 2 from which the carbide had been removed as described above was set on a delivery shaft of a sputtering device, and the other end was set on a winding shaft.
  • Ni was attached as target No. 1
  • Cu was attached as target No. 24, respectively.
  • the injection amount of argon gas is the target No. 1, fitted with a Ni 180c cZ min, target current 0. 6kWZdm 2, and is for the target No. 2-4 fitted with a Cu injection volume each 250 cc / min argon gas to sputter these metals under matter conditions of the target current each 1. 2kWZdm 2
  • the first conductive layer was formed directly on one surface of the insulating substrate. Then, the vacuum state of the sputtering apparatus was released.
  • the insulating substrate 2 is turned upside down so that the same first conductive layer as described above can be formed on the surface of the insulating substrate 2 on which the first conductive layer is not formed. Then, it was set again in the sputtering apparatus. Then, the same first conductive layer as described above was directly formed on the other surface of the insulating substrate by performing sputtering under the same conditions as described above.
  • the first conductive layer is formed directly on both the front and back surfaces of the insulating substrate 2 and the wall surfaces of the through hole and the anchor hole 5, and the first conductive layer is formed by first forming the Ni layer on the insulating substrate 2. They are stacked and a Cu layer is stacked on them. This configuration has the same configuration on both the front and back surfaces of the insulating substrate and the wall surfaces of the through hole and the anchor hole 5.
  • the first guide was applied to both the front and back surfaces as described above.
  • the insulating substrate 2 on which the electric layer was formed was set in a continuous plating apparatus, and the electric plating was performed under the following conditions. That is, first, the insulating substrate is immersed continuously in an acid activation tank filled with 7% sulfuric acid at a liquid temperature of 28 ° C for 60 seconds, so that the first conductive layer is subjected to an acid activation treatment. Was performed.
  • the plating solution (copper sulfate 100 g / l, sulfuric acid 160 g / l, chlorine 60 ppm, and toppertina 380H (manufactured by Okuno Pharmaceutical Co., Ltd.)) was added to the plating bath of the above apparatus. filled ones) consisting Locc / 1, the insulating substrate 1. is continuously immersed at a moving speed of OmZ min,-out liquid temperature 28 ° C, under conditions of current density 4AZdm 2 11 minutes electrical flashes Thereby, a second conductive layer made of Cu was formed on the first conductive layer.
  • the first conductive layer is formed on both the front and back surfaces of the insulating substrate 2 and the wall surfaces of the through hole and the anchor hole 5, and the second conductive layer is formed on the first conductive layer.
  • the conductive layer 3 was formed.
  • the configuration of the second conductive layer is the same on both the front and back surfaces of the insulating substrate 2 and the wall surfaces of the through hole and the anchor hole 5.
  • the conductive layer 3 includes a first conductive layer and a second conductive layer, and has the same configuration on both the front and back surfaces of the insulating substrate 2 and the wall surfaces of the through hole and the anchor hole 5. Layer 3 has been formed.
  • the insulating substrate 2 on which the second conductive layer was formed was repeatedly washed with pure water five times.
  • the mixture was drained with dry air at 105 ° C. through a high-performance filter (the size of the opening of the filter was 0.5 / m or less) and dried sufficiently.
  • peel test apparatus have use the (MODEL 1305N, Aiko one Engineering Co., Ltd.) were measured adhesion to the insulating substrate of the conductive layer, the adhesion of 3 kg / cm 2 is where there is anchor holes Although the strength was shown, the adhesion strength was 0.9 kg / cm 2 where there was no anchor hole. Due to this, adhesion by anchor hole The effect of improvement was confirmed.
  • a dry film (trade name: NIT215, manufactured by Nichigo Morton) was applied as a resist on the entire surface of the second conductive layer of the insulating substrate 2 under the conditions of a temperature of 110 ° C. and a pressure of 2 kg / cm 2 . Then, a resist was formed on the second conductive layer.
  • a mask representing a desired circuit pattern (designed such that a portion serving as an anchor layer remains without being etched) on both the front and back surfaces of the insulating substrate 2 is overlaid on the resist.
  • exposure was performed at an amount of light of 120 mJ using an average exposure machine (manufactured by the company).
  • the conditions of sodium carbonate 0.5 gZl, temperature 28 ° C, spray pressure 1.5 kg / cm 2 were used. The resist was removed by developing underneath. Thereafter, washing with pure water was repeated 5 times.
  • a resist stripper was used to remove 100% caustic soda, a temperature of 60 ° C, and a spray pressure of 2. Okg / cm 2 .
  • the conductive sheet 1 of the present invention was obtained by removing the resist under the conditions.
  • the circuit pattern formed by the conductive layer and the positions of the through hole, the anchor hole and the anchor layer were confirmed. It was within ⁇ 5%, which was extremely excellent in dimensional accuracy and allowed fine circuit patterns. In addition, since the conductive layers were formed simultaneously and integrally, the production efficiency was excellent.
  • the conductive sheet has highly reliable electrical connectivity because two or more through holes are formed in a substantial part of the insulating substrate on which the conductive layer is formed. At the same time, the adhesion between the conductive layer and the insulating substrate was greatly enhanced by the anchor holes.
  • a conductive sheet was obtained in the same manner as in Example 1 except that the inner diameter of the through hole and the inner diameter of the anchor hole were each 20 ⁇ m.
  • the through hole in Example 1 was in the form of a via hole, and the anchor hole was also filled in the inside like a via hole.
  • the conductive sheet was extremely excellent in dimensional accuracy and allowed finer circuit patterns. In addition, it has highly reliable electrical connection, the adhesion between the conductive layer and the insulating substrate is extremely enhanced by the anchor holes, and the production efficiency is excellent.

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Abstract

A conductive sheet (1) wherein conductive layers are formed directly on both sides of an insulating substrate (2), and the one or more conductive layers existing on one side are connected electrically with conductive layers existing on the other side through a through hole or a via hole (4) opened to penetrate the insulating substrate (2). The conductive sheet (1) is characterized in that on either side of the insulating substrate (2), at least one conductive layer (3a) not connected electrically with the other conductive layers (3b, 3c) on the same side is formed, and more than one through holes or via holes (4) are formed in the parts of the insulating substrate (2) where one or more conductive layers are formed.

Description

明 細 書  Specification

スルホールまたはビアホールを 2以上形成した導電性シート  Conductive sheet with two or more through holes or via holes

技術分野  Technical field

[0001] 本発明は、導電性シートに関する。より詳細には、半導体用基板や電気、電子部品 用回路基板、各種パッケージング、自動車部品、太陽電池、アンテナ回路基板、 IC カード等に好適に用いることができる導電性シートに関する。  The present invention relates to a conductive sheet. More specifically, the present invention relates to a conductive sheet that can be suitably used for substrates for semiconductors, circuit boards for electric and electronic components, various packaging, automobile parts, solar cells, antenna circuit boards, IC cards, and the like.

背景技術  Background art

[0002] 電気、電子部品用回路基板や半導体用回路基板として使用される FPC (フレキシ ブルプリント回路基板、 Flexible Printed Circuit)や TAB (Tape Automated Bonding)基板としては、絶縁性基体に導電層となる銅箔を貼り合わせた構成の導 電性シートが用いられてきた (特許文献 1、 2)。  [0002] As an FPC (Flexible Printed Circuit Board) or TAB (Tape Automated Bonding) substrate used as a circuit board for electric and electronic parts and a circuit board for semiconductors, a conductive layer is formed on an insulating base. Conductive sheets having a configuration in which copper foil is bonded have been used (Patent Documents 1 and 2).

[0003] このような構成の導電性シートは、絶縁性基体と銅箔とを密着性高く接着させること が必要であり、たとえば絶縁性基体に接着剤を塗布して銅箔を貼り合わせたり、ある いは銅箔に接着剤を塗布したものを絶縁性基体に貼り合わせたりして製造されてい た。そして、これらの絶縁性基体と銅箔との密着性をさらに向上させるために、種々の 接着剤が選定されたり、銅箔表面に銅の粒状物を付着させて凹凸状の突起を形成さ せたりすることが試みられてきた。  [0003] The conductive sheet having such a configuration needs to adhere the insulating substrate and the copper foil with high adhesiveness. For example, an adhesive is applied to the insulating substrate to bond the copper foil, Alternatively, it was manufactured by applying an adhesive to a copper foil and bonding it to an insulating substrate. In order to further improve the adhesion between the insulating substrate and the copper foil, various adhesives are selected, or copper particles are adhered to the copper foil surface to form irregular projections. Have been tried.

[0004] これらの方法によりある程度両者の密着性を向上することができるものの、回路バタ ーンのファイン化に伴なつて上記いずれの方法においても次のような問題が指摘さ れている。すなわち、接着剤を用レ、る場合、その接着剤の種類にかかわらず塗布厚 が 10 30 μ mにおよび、導電性シート全体の厚みが厚くなることから回路パターン のファイン化に不利な要因となる。また、導電層をエッチングしてファイン化された回 路パターンを形成するとき、この接着剤層がエッチングを妨げる場合がある。さらに、 銅箔表面に銅の粒状物を付着させて凹凸状の突起を形成させる場合、該粒状物が 回路パターンのファイン化を妨げることがある。  [0004] Although the adhesion between the two can be improved to some extent by these methods, the following problems have been pointed out in any of the above methods with the refinement of circuit patterns. In other words, when using an adhesive, the applied thickness is 1030 μm, regardless of the type of the adhesive, and the overall thickness of the conductive sheet is large. Become. When the conductive layer is etched to form a fine circuit pattern, the adhesive layer may hinder the etching. Further, when copper particles are adhered to the surface of the copper foil to form projections and depressions, the particles may prevent finer circuit patterns.

[0005] 一方、上記のような接着剤や凹凸状の突起を介さずに、絶縁性基体に導電層を直 接形成する方法も種々検討されており、たとえばスパッタリング、蒸着、無電解めつき または電気めつきにより導電層を形成したものが知られている(特許文献 3— 13)。こ のような方法により導電層を形成したものは、回路パターンのファイン化に伴なう上記 のような問題は解消されるものの、逆に導電層と絶縁性基体との間の密着性という観 点からは未だ改善の余地が残されている現状にある。 [0005] On the other hand, various methods for forming a conductive layer directly on an insulating substrate without the intervention of the above-mentioned adhesive or uneven protrusions have been studied, such as sputtering, vapor deposition, and electroless plating. Alternatively, a conductive layer formed by electroplating is known (Patent Documents 3-13). In the case where the conductive layer is formed by such a method, although the above-mentioned problem associated with the finer circuit pattern is solved, the view of the adhesion between the conductive layer and the insulating substrate is conversely observed. From the point of view, there is still room for improvement.

特許文献 1:特開平 4 - 286394号公報  Patent Document 1: Japanese Patent Application Laid-Open No. 4-286394

特許文献 2:特開平 11 - 307933号公報  Patent Document 2: JP-A-11-307933

特許文献 3:特開平 11 - 298104号公報  Patent Document 3: JP-A-11-298104

特許文献 4 :特開平 5— 327229号公報  Patent Document 4: JP-A-5-327229

特許文献 5:特開平 5 - 267806号公報  Patent Document 5: JP-A-5-267806

特許文献 6 :特開平 4 - 314395号公報  Patent Document 6: JP-A-4-314395

特許文献 7:特開平 2 - 142198号公報  Patent Document 7: JP-A-2-142198

特許文献 8 :特開平 2 - 21507号公報  Patent Document 8: JP-A-2-21507

特許文献 9 :特開昭 63 - 177586号公報  Patent Document 9: JP-A-63-177586

特許文献 10 :特開昭 62 - 226689号公報  Patent Document 10: JP-A-62-226689

特許文献 11 :特開昭 53 - 140570号公報  Patent Document 11: JP-A-53-140570

特許文献 12:特開昭 59 - 228789号公報  Patent Document 12: JP-A-59-228789

特許文献 13:特開昭 51 - 60997号公報  Patent Document 13: JP-A-51-60997

発明の開示  Disclosure of the invention

発明が解決しょうとする課題  Problems to be solved by the invention

[0006] 本発明は、上述の現状に鑑みてなされたものであって、その目的とするところは、絶 縁性基体と導電層間の密着性の向上と、回路パターンのファイン化とを両立させた 導電性シートを提供することにある。 課題を解決するための手段 [0006] The present invention has been made in view of the above situation, and an object of the present invention is to improve the adhesion between the insulating substrate and the conductive layer and make the circuit pattern finer. Another object of the present invention is to provide a conductive sheet. Means for solving the problem

[0007] 本発明の導電性シートは、絶縁性基体の表裏両面に導電層が直接形成され、その 表裏両面に存在する 1以上の導電層が該絶縁性基体を貫通するようにして開孔され ているスルホールまたはビアホールを介して他方の面に存在する導電層と電気的に 接続されている導電性シートであって、該絶縁性基体の表裏両面にはその同一の表 面内の他の導電層とは電気的に接続していない導電層が少なくとも 1以上形成され ており、該導電層の 1以上が形成されている絶縁性基体の相当部分において、スル ホールまたはビアホールを 2以上形成したとともに、該導電層がスパッタリング法また は蒸着法により形成される第 1導電層と、無電解めつき法または電気めつき法により 形成される第 2導電層とを含むことを特徴としている。 [0007] In the conductive sheet of the present invention, a conductive layer is directly formed on both the front and back surfaces of an insulating substrate, and one or more conductive layers present on both the front and back surfaces are opened so as to penetrate the insulating substrate. A conductive sheet electrically connected to a conductive layer present on the other surface through a through hole or via hole provided on the other surface of the insulating substrate. At least one conductive layer that is not electrically connected to the layer is formed. In a substantial portion of the insulating substrate on which one or more of the conductive layers are formed, two or more through holes or via holes are formed, and the first conductive layer is formed by sputtering or vapor deposition. And a second conductive layer formed by an electroless plating method or an electroplating method.

[0008] また、本発明の導電性シートは、絶縁性基体の表裏両面に導電層が直接形成され 、その表裏両面に存在する 1以上の導電層が該絶縁性基体を貫通するようにして開 孔されているスルホールまたはビアホールを介して他方の面に存在する導電層と電 気的に接続されている導電性シートであって、該絶縁性基体の表裏両面にはその同 一の表面内の他の導電層とは電気的に接続していない導電層が少なくとも 1以上形 成されており、該導電層は他方の面に存在する導電層と電気的に接続していない導 電層を含み、かつ該導電層の 1以上が形成されている絶縁性基体の相当部分にお いて、該絶縁性基体を貫通するようにして開孔されているアンカーホールを 1以上形 成し、該アンカーホールはそれを介しては他方の面に存在する導電層と電気的に接 続することはなぐかつその壁面に導電層を有するかまたはその内部に導電層が充 填されているとともに、該導電層がスパッタリング法または蒸着法により形成される第In the conductive sheet of the present invention, a conductive layer is directly formed on both front and back surfaces of an insulating substrate, and one or more conductive layers present on both front and back surfaces are opened so as to penetrate the insulating substrate. A conductive sheet electrically connected to a conductive layer present on the other surface through a perforated through hole or via hole, wherein both sides of the insulating substrate have the same surface. At least one conductive layer not electrically connected to another conductive layer is formed, and the conductive layer includes a conductive layer not electrically connected to a conductive layer present on the other surface. And forming at least one anchor hole that is opened so as to penetrate the insulating substrate in a substantial portion of the insulating substrate on which at least one of the conductive layers is formed; Is connected to the conductive layer on the other side With conductive layer is Hama charge connected to it nag and either a conductive layer on the wall surface or within, the second conductive layer is formed by the sputtering method or the vapor deposition method

1導電層と、無電解めつき法または電気めつき法により形成される第 2導電層とを含 むことを特徴としている。 It is characterized by including one conductive layer and a second conductive layer formed by an electroless plating method or an electroplating method.

[0009] 上記アンカーホールは、上記絶縁性基体の表裏両面において開孔面積が異なつ たものであることが好ましレ、。 [0009] Preferably, the anchor holes have different opening areas on both the front and back surfaces of the insulating substrate.

[0010] また、上記導電性シートにおいては、電気的接続を目的とせず、上記導電層の上 記絶縁性基体への密着性の向上を目的とするアンカー層が、上記アンカーホールを 介して他方の面の導電層と接続されていることが好ましい。 [0010] Further, in the conductive sheet, an anchor layer for the purpose of improving adhesion to the insulating substrate is not provided for the purpose of electrical connection, but is provided on the other side via the anchor hole. Is preferably connected to the conductive layer on the surface.

[0011] また、本発明は、上記の導電性シートを用いた半導体製品、電気製品、電子製品、 自動車、太陽電池、アンテナ回路基板または ICカードに関する。  [0011] The present invention also relates to a semiconductor product, an electric product, an electronic product, an automobile, a solar cell, an antenna circuit board, or an IC card using the conductive sheet.

発明の効果  The invention's effect

[0012] 本発明の導電性シートは、絶縁性基体と導電層間の密着性の向上と、回路パター ンのファイン化とを両立させたとともに、信頼性の高い電気的接続性を有し、かつ優 れた生産効率と寸法精度を有するものである。 [0013] したがって、本発明の導電性シートは、半導体用基板や電気、電子部品用回路基 板、各種パッケージング、自動車部品、太陽電池、アンテナ回路基板、 ICカード等、 広範囲の用途に適用することができる。すなわち、該導電性シートは、ある大きさに力 ットする力 あるいはカットせず連続状の形態で複数の回路パターンを形成すること ができ、上記各種用途に用いることができる。 [0012] The conductive sheet of the present invention has both improved adhesion between the insulating substrate and the conductive layer and finer circuit patterns, and has highly reliable electrical connectivity. It has excellent production efficiency and dimensional accuracy. [0013] Therefore, the conductive sheet of the present invention is applied to a wide range of uses such as a substrate for semiconductors, a circuit board for electric and electronic parts, various packaging, an automobile part, a solar cell, an antenna circuit board, and an IC card. be able to. That is, the conductive sheet can form a plurality of circuit patterns in a continuous form without being cut or cut into a certain size, and can be used for the above-mentioned various applications.

図面の簡単な説明  Brief Description of Drawings

[0014] [図 1]本発明の導電性シートの概略断面図である。  FIG. 1 is a schematic sectional view of a conductive sheet of the present invention.

[図 2]本発明の導電性シートの概略平面図である。  FIG. 2 is a schematic plan view of a conductive sheet of the present invention.

[図 3A]スルホールのように壁面に導電層を有するアンカーホールの概略断面図であ る。  FIG. 3A is a schematic sectional view of an anchor hole having a conductive layer on a wall surface like a through hole.

[図 3B]ビアホールのように内部に導電層が充填されているアンカーホールの概略断 面図である。  FIG. 3B is a schematic sectional view of an anchor hole in which a conductive layer is filled like a via hole.

[図 3C]絶縁性基体の表裏両面で開孔面積が異なっているアンカーホールの概略断 面図である。  FIG. 3C is a schematic cross-sectional view of an anchor hole having different opening areas on both front and back surfaces of an insulating substrate.

符号の説明  Explanation of symbols

[0015] 1 導電性シート、 2 絶縁性基体、 3, 3a, 3b, 3c 導電層、 4 スルホールまたは ビアホール、 5 アンカーホール、 6 アンカー層、 7 屈曲部、 8 はんだ付け部、 9 先端部。  [0015] 1 conductive sheet, 2 insulating substrate, 3, 3a, 3b, 3c conductive layer, 4 through hole or via hole, 5 anchor hole, 6 anchor layer, 7 bent portion, 8 soldered portion, 9 tip portion.

発明を実施するための最良の形態  BEST MODE FOR CARRYING OUT THE INVENTION

[0016] 以下、本発明の実施の形態を図面を用いて説明する。本明細書の図面において 同一の参照符号を付したものは、同一部分または相当部分を示す。  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings of the present specification, the same reference numerals denote the same or corresponding parts.

[0017] <導電性シートおよびその用途 >  [0017] <Conductive sheet and its use>

図 1に示したように、本発明の導電性シート 1は、絶縁性基体 2の表裏両面に導電 層 3が直接形成され、その表裏両面に存在する 1以上の導電層 3が該絶縁性基体 2 を貫通するようにして開孔されているスルホールまたはビアホール 4を介して他方の 面に存在する導電層 3と電気的に接続された構成を有するものであり、また図 2に示 すように、該絶縁性基体 2の表裏両面にはその同一の表面内の他の導電層 3bおよ び 3cとは電気的に接続していない導電層 3aが少なくとも 1以上形成された構成を有 する。なお、図 1は、図 2の導電層 3aが形成されている部分の概略断面図である。 As shown in FIG. 1, the conductive sheet 1 of the present invention has an insulating substrate 2 in which conductive layers 3 are directly formed on both front and back surfaces, and one or more conductive layers 3 present on both front and back surfaces are formed on the insulating substrate 2. 2 is electrically connected to the conductive layer 3 present on the other surface through a through hole or a via hole 4 that is opened so as to penetrate through the through hole 2 as shown in FIG. The insulating substrate 2 has a structure in which at least one or more conductive layers 3a that are not electrically connected to other conductive layers 3b and 3c on the same surface are formed on both front and back surfaces. To do. FIG. 1 is a schematic sectional view of a portion where the conductive layer 3a of FIG. 2 is formed.

[0018] このような構成を有する本発明の導電性シートは、半導体用基板や電気、電子部 品用回路基板、各種パッケージング、自動車部品、太陽電池、アンテナ回路基板、 I Cカード等に好適に用いることができる。したがって、本発明は、このような導電性シ ートを用いた各種半導体製品、電気製品、電子製品、 自動車、太陽電池、アンテナ 回路基板または ICカードにも関する。以下、本発明の導電性シートの各構成につい て説明する。 The conductive sheet of the present invention having such a configuration is suitable for a substrate for a semiconductor, a circuit board for electric and electronic parts, various packaging, an automobile part, a solar cell, an antenna circuit board, an IC card, and the like. Can be used. Therefore, the present invention also relates to various semiconductor products, electric products, electronic products, automobiles, solar cells, antenna circuit boards, or IC cards using such a conductive sheet. Hereinafter, each configuration of the conductive sheet of the present invention will be described.

[0019] <絶縁性基体 > [0019] <Insulating substrate>

本発明の導電性シートの基材として用いられる絶縁性基体としては、この種の用途 に用いることができる従来公知のものであれば特に限定なくいかなるものも用いること ができる。特に、薄い厚みを有するフィルムの形状のものが好適である。後述の導電 層の形成に適しているとともに、ロールのような長尺の連続状のものとして加工するこ とが可能となり生産効率を向上させることができるからである。  As the insulating substrate used as the substrate of the conductive sheet of the present invention, any conventionally known substrate that can be used for this kind of application can be used without any particular limitation. In particular, a film having a small thickness is preferable. This is because it is suitable for forming a conductive layer to be described later and can be processed into a long continuous material such as a roll, thereby improving production efficiency.

[0020] このような絶縁性基体の一例を挙げると、たとえば PET、 PEN等のポリエステル、ポ リイミド、ァラミド、ポリスルフォン、ポリエーテルイミド、ポリフエ二レンォキシド、液晶ポ リマー、ガラス繊維強化エポキシ樹脂、フエノール樹脂、アクリル樹脂等のフィルムを 挙げること力 Sできる。これらの中でも特に柔軟性に優れ高性能化の可能なポリイミドゃ ガラス繊維強化エポキシ樹脂からなるフィルムを用いることが好ましい。  Examples of such an insulating substrate include polyesters such as PET and PEN, polyimides, aramides, polysulfones, polyetherimides, polyphenylene oxides, liquid crystal polymers, glass fiber reinforced epoxy resins, and phenols. The ability to name films such as resins and acrylic resins. Among these, it is particularly preferable to use a film made of a polyimide glass fiber reinforced epoxy resin having excellent flexibility and high performance.

[0021] なお、ここでいうフィルムとは、その厚みが 4一 300 μ ΐη、好ましくは 12— 50 μ m程 度のものが好適である。 4 /i m未満では、強度が弱く加工に耐えられない場合があり 、 300 /i mを超えると後述のようにスルホールやビアホール、またはアンカーホール に対して導電層を形成する際に支障をきたす場合があるからである。  It is to be noted that the film referred to here is preferably a film having a thickness of 4-1300 μΐη, preferably about 12-50 μm. If it is less than 4 / im, the strength may be too weak to be processed, and if it exceeds 300 / im, it may hinder the formation of a conductive layer for through holes, via holes, or anchor holes as described later. Because there is.

[0022] また、このように絶縁性基体の形状は、フィルム状のものが特に適している力 フィ ルム状の形状であれば枚葉の形態のものであってもロールのような長尺の連続状の 形態のものであっても差し支えなレ、。本発明においては、特にその製造における加 ェ効率の観点からロールのような長尺の連続状のものを用いることが好適である。  [0022] Further, as described above, the shape of the insulating substrate is particularly suitable for a film-like force. A continuous form is acceptable. In the present invention, it is preferable to use a long continuous material such as a roll from the viewpoint of the processing efficiency in the production.

[0023] <スルホール >  [0023] <Sulhole>

本発明におけるスルホールとは、前記絶縁性基体の表裏を物理的に貫通するよう に設けられてレ、る小孔であって、このスルホールを介して該絶縁性基体の表裏両面 に形成される後述の導電層を互いに電気的に接続することができる。 In the present invention, the through hole is such that it physically penetrates the front and back of the insulating substrate. The conductive layers formed on both the front and back surfaces of the insulating substrate can be electrically connected to each other through the through holes.

[0024] 本発明においては、絶縁性基体に対してこのスルホールを形成した後に後述の導 電層を形成することが好ましい。これにより、絶縁性基体の表裏両面の導電層とスル ホール内の導電層とを一体的に形成することが可能となり、生産効率の向上に資す ることができるとともに、信頼性の高い電気的接続を保証することができる。  In the present invention, it is preferable to form a conductive layer described later after forming the through hole in the insulating substrate. This makes it possible to integrally form the conductive layers on both the front and back surfaces of the insulating substrate and the conductive layers in the through holes, thereby contributing to an improvement in production efficiency and a highly reliable electrical connection. Can be guaranteed.

[0025] このようなスルホールの形状は、前記絶縁性基体の表裏を貫通する限り特に限定さ れることはなぐたとえばその断面形状を円形のものや多角形状のものとすることがで きる。該スルホールは、その内径が 5— 300 z m、好ましくは 10— 200 z mとすること が好適である。その内径が 5 x m未満である場合、開孔が困難となり加工コストが高く なるとともに、 300 μ mを超えると導電層の幅方向の長さに対するスルホールの径が 大きくなり過ぎ有効な回路スペースの確保や電気的接続に問題を生じる場合がある 。したがって、スルホールの内径は、加工コストが高くならない範囲内で小さく形成す る方が回路設計上有利である。  [0025] The shape of such a through hole is not particularly limited as long as it penetrates the front and back surfaces of the insulating substrate. For example, the through hole may have a circular or polygonal cross section. The through hole preferably has an inner diameter of 5 to 300 zm, preferably 10 to 200 zm. If the inner diameter is less than 5 xm, drilling becomes difficult and the processing cost increases, and if it exceeds 300 μm, the diameter of the through hole becomes too large with respect to the length of the conductive layer in the width direction, and effective circuit space is secured. And problems with electrical connections. Therefore, it is more advantageous in circuit design to form the through hole with a smaller inside diameter without increasing the processing cost.

[0026] また、このようなスルホールは、該絶縁性基体の表面において島状に存在する導電 層 1つ当りに 2以上、好ましくは 2— 5、更に好ましくは 2— 3、その導電層が形成され ている絶縁性基体の相当部分において形成されていることが好ましい。島状に存在 する導電層 1つ当りにスルホールを 1つだけ形成すると、導電層と絶縁性基体間の密 着性に問題があるとともに、電気的接続性にも問題を生ずる場合があるからである。 また、あまりに多数のスルホールを形成すると、導電層に占めるスルホールの面積が 大きくなり、回路設計上の自由度が低下するとともに、加工効率も低下することとなる ため、島状に存在する導電層 1つ当りに 5つ程度までとすることが好ましレ、。  [0026] In addition, such through holes are formed in an amount of 2 or more, preferably 2 to 5, more preferably 2 to 3, for each conductive layer present in the form of an island on the surface of the insulating substrate. It is preferably formed in a substantial part of the insulating substrate described above. If only one through hole is formed for each conductive layer present in the shape of an island, there is a problem in the adhesion between the conductive layer and the insulating substrate, and also a problem in the electrical connectivity. is there. If too many through holes are formed, the area of the through holes occupying the conductive layer becomes large, thereby reducing the degree of freedom in circuit design and the processing efficiency. It is preferable to make up to about 5 per hit.

[0027] ここで、島状に存在する導電層とは、該絶縁性基体の表裏いずれかの面において 、その同一表面内の他の導電層と電気的に接続していない各導電層をレ、うものとす る。  Here, an island-shaped conductive layer refers to each conductive layer that is not electrically connected to another conductive layer on the same surface on either of the front and back surfaces of the insulating substrate. ,And Umono.

[0028] すなわち、図 2に示すように、該絶縁性基体 2の表裏両面には、その同一の表面内 の他の導電層 3bおよび 3cとは電気的に接続していない導電層 3aが少なくとも 1以上 形成されており、該導電層の 1以上(図 2においては少なくとも導電層 3aまたは導電 層 3b、 3c)が形成されている絶縁性基体の相当部分において、上記スルホールが 2 以上形成されてレ、ることが好ましレ、。このように島状に存在する導電層 1つ当りに 2以 上のスルホールを形成することにより、該導電層は電気的接続性に対する信頼性が 高まるとともに、絶縁性基体に対する密着性も高められる。 That is, as shown in FIG. 2, at least on the front and back surfaces of the insulating substrate 2, at least a conductive layer 3a that is not electrically connected to other conductive layers 3b and 3c on the same surface is provided. One or more of the conductive layers (in FIG. 2, at least the conductive layer 3a or the conductive layer 3a). It is preferable that two or more of the above-mentioned through holes are formed in a substantial part of the insulating substrate on which the layers 3b and 3c) are formed. By forming two or more through-holes per one conductive layer existing in an island shape, the reliability of the conductive layer with respect to the electrical connection is increased and the adhesion to the insulating substrate is also increased.

[0029] このようなスルホールは、従来公知の開孔方法(穴開け加工方法)であれば特に限 定することなくいずれの方法によっても開孔することができる。たとえば、 COレーザ、 [0029] Such a through hole can be formed by any conventionally known hole forming method (drilling method) without any particular limitation. For example, CO laser,

2 2

YAGレーザ、エキシマレーザ等の各種レーザ、ドリル、パンチ、プレスなどの開孔手 段により絶縁性基体を貫通するようにして開孔される。特にスルホールの内径が 80 μ mよりも小さくなる場合は、各種レーザにより開孔することが好ましい。 Holes are formed so as to penetrate the insulating substrate by means of various lasers such as a YAG laser and an excimer laser, and drilling, punching, and pressing. In particular, when the inner diameter of the through hole is smaller than 80 μm, it is preferable to open the hole by using various lasers.

[0030] <ビアホーノレ >  [0030] <Beer Honoré>

本発明におけるビアホールとは、前記絶縁性基体の表裏を物理的に貫通するよう に設けられてレ、る小孔であって、このビアホールを介して該絶縁性基体の表裏両面 に形成される後述の導電層を互いに電気的に接続することができる。このようにビア ホールは、上記スルホールと同様の作用を有するものである力 上記スルホールがそ の壁面のみに導電層が形成され中心部に空洞状の部分が残る形態をとるのに対し て、このビアホールはホール内部が全て導電層により充填されて空洞状の部分を有 さなレ、点におレ、てその形態が異なってレ、る。  The via hole in the present invention is a small hole provided so as to physically penetrate the front and back of the insulating substrate, and is formed on both the front and back surfaces of the insulating substrate through this via hole. Can be electrically connected to each other. As described above, the via hole has the same function as the through hole, and the through hole takes a form in which a conductive layer is formed only on the wall surface and a hollow portion remains in the center. The via hole is different in the form in that the inside of the hole is entirely filled with a conductive layer and has no hollow portion.

[0031] 本発明の導電性シートにおいて、絶縁性基体の表裏両面の導電層をスルホールを 介して電気的に接続するか、あるいはビアホールを介して電気的に接続するかは、 回路パターンの形状や大きさ等により任意に選択することができ、これら両者を各単 独でまたは併用して形成することができる。  [0031] In the conductive sheet of the present invention, whether the conductive layers on the front and back surfaces of the insulating substrate are electrically connected through through holes or electrically connected through via holes depends on the shape of the circuit pattern, They can be arbitrarily selected depending on the size and the like, and both can be formed alone or in combination.

[0032] 本発明においては、スルホールの場合と同様、絶縁性基体に対してこのビアホー ルを形成した後に後述の導電層を形成することが好ましい。これにより、絶縁性基体 の表裏両面の導電層とビアホール内に充填される導電層とを一体的に形成すること が可能となり、生産効率の向上に資することができるとともに、信頼性の高い電気的 接続を保証することができる。  [0032] In the present invention, as in the case of the through hole, it is preferable to form the via hole on the insulating substrate and then form the conductive layer described later. This makes it possible to integrally form the conductive layer on both the front and back surfaces of the insulating substrate and the conductive layer filled in the via hole, thereby contributing to an improvement in production efficiency and providing a highly reliable electrical device. Connection can be guaranteed.

[0033] このようなビアホールの形状は、前記絶縁性基体の表裏を貫通する限り特に限定さ れることはなぐたとえばその断面形状を円形のものや多角形状のものとすることがで きる。該ビアホールは、その内径が 5— 100 /i m、好ましくは 10— 25 /i mとすることが 好適である。その内径が 5 / m未満である場合、開孔が困難となり加工コストが高くな るとともに、 100 μ ΐηを超えると導電層によりホール内部を充填するのに長時間を要 し、生産効率を悪化させることになる。なお、このようなビアホールの内径は、加工コ ストが高くならない範囲内で小さく形成する方が回路設計上有利である。 The shape of such a via hole is not particularly limited as long as it penetrates the front and back of the insulating substrate. For example, the cross-sectional shape may be circular or polygonal. Wear. The via hole has an inner diameter of 5-100 / im, preferably 10-25 / im. If the inner diameter is less than 5 / m, drilling becomes difficult and the processing cost increases, and if it exceeds 100 μΐη, it takes a long time to fill the inside of the hole with the conductive layer, resulting in poor production efficiency. Will be. It should be noted that it is more advantageous in circuit design to form such via holes with a smaller inner diameter as long as the processing cost does not increase.

[0034] また、このようなビアホールは、該絶縁性基体の表面において島状に存在する導電 層 1つ当りに 2以上、好ましくは 2 5、更に好ましくは 2 3、その導電層が形成され ている絶縁性基体の相当部分に形成されていることが好ましい。島状に存在する導 電層 1つ当りにビアホールを 1つだけ形成すると、導電層と絶縁性基体間の密着性に 問題があるとともに、電気的接続性にも問題を生ずる場合があるからである。また、あ まりに多数のビアホールを形成すると、導電層に占めるビアホールの面積が大きくな り、回路設計上の自由度が低下するとともに、加工効率も低下することとなるため、島 状に存在する導電層 1つ当りに 5つ程度までとすることが好ましい。なお、該ビアホー ルが、スルホールとともに形成される場合には、両者の合計数が、 2以上、好ましくは 2— 5、更に好ましくは 2— 3形成されていることが好ましい。  [0034] In addition, the number of such via holes is 2 or more, preferably 25, and more preferably 23 per conductive layer existing in the form of an island on the surface of the insulating substrate. It is preferably formed on a substantial portion of the insulating substrate. If only one via hole is formed for each conductive layer existing in the shape of an island, there is a problem in the adhesion between the conductive layer and the insulating substrate and also a problem in the electrical connectivity. is there. Also, if a large number of via holes are formed, the area of the via holes in the conductive layer becomes large, and the degree of freedom in circuit design is reduced, and the processing efficiency is also reduced. It is preferable to use up to about five per conductive layer. When the via hole is formed together with the through hole, the total number of both is preferably 2 or more, preferably 2-5, and more preferably 2-3.

[0035] ここで、島状に存在する導電層とは、前記同様の導電層をいうものとする。すなわち 、図 2に示すように、該絶縁性基体 2の表裏両面には、その同一の表面内の他の導 電層 3bおよび 3cとは電気的に接続していない導電層 3aが少なくとも 1以上形成され ており、該導電層の 1以上(図 2においては少なくとも導電層 3aまたは導電層 3b、 3c )が形成されている絶縁性基体の相当部分において、上記ビアホールが 2以上形成 されてレ、ることが好ましレ、。このように島状に存在する導電層 1つ当りに 2以上のビア ホールを形成することにより、該導電層は電気的接続性に対する信頼性が高まるとと もに、絶縁性基体に対する密着性も高められる。  Here, the conductive layer existing in an island shape refers to the same conductive layer as described above. That is, as shown in FIG. 2, at least one or more conductive layers 3a that are not electrically connected to the other conductive layers 3b and 3c on the same surface are provided on both front and back surfaces of the insulating substrate 2. In a substantial portion of the insulating substrate where one or more of the conductive layers (in FIG. 2, at least the conductive layer 3a or the conductive layers 3b and 3c) are formed, two or more of the via holes are formed. It is preferable to By forming two or more via holes per conductive layer existing in an island shape in this way, the conductive layer increases the reliability with respect to the electrical connectivity and the adhesion to the insulating substrate. Enhanced.

[0036] このようなビアホールは、従来公知の開孔方法(穴開け加工方法)であれば特に限 定することなくいずれの方法によっても開孔することができる。たとえば、 COレーザ、  [0036] Such a via hole can be opened by any conventionally known opening method (drilling method) without any particular limitation. For example, CO laser,

2 2

YAGレーザ、エキシマレーザ等の各種レーザにより絶縁性基体を貫通するようにし て開孔される。 Holes are formed by various lasers such as a YAG laser and an excimer laser so as to penetrate the insulating substrate.

[0037] <導電層> 本発明の導電層は、前記絶縁性基体の表裏両面に直接形成され、その表裏両面 に存在する 1以上の導電層が該絶縁性基体を貫通するようにして開孔されている前 記スルホールまたはビアホールを介して他方の面に存在する導電層と電気的に接続 されている(図 1参照)。また、該絶縁性基体の表裏両面にはその同一の表面内の他 の導電層とは電気的に接続していない導電層が少なくとも 1以上形成されており(図 2参照)、該導電層の 1以上が形成されている絶縁性基体の相当部分において、前 述の通りスルホールまたはビアホールを 2以上形成したことを特徴としている。 <Conductive layer> The conductive layer of the present invention is formed directly on both the front and back surfaces of the insulating substrate, and one or more conductive layers existing on both the front and back surfaces are opened so as to penetrate the insulating substrate. It is electrically connected to the conductive layer on the other surface via via holes (see Fig. 1). Further, at least one or more conductive layers that are not electrically connected to other conductive layers on the same surface are formed on both front and back surfaces of the insulating substrate (see FIG. 2). As described above, two or more through holes or via holes are formed in a substantial portion of the insulating substrate on which one or more are formed.

[0038] また、本発明の導電層は、絶縁性基体の他方の面に存在する導電層と電気的に接 続していない導電層を含んでいても良ぐまた後述のアンカーホールを 1以上含むこ とができる。すなわち、該導電層には、それが形成されている絶縁性基体の相当部 分にスルホールまたはビアホールが形成されていないものも含まれ得、よってスルホ ールまたはビアホールと、アンカーホールとの両者が形成されるものがあるとともに、 これら両者のうちいずれか一方のもののみが形成されるものもある。  [0038] The conductive layer of the present invention may include a conductive layer that is not electrically connected to the conductive layer present on the other surface of the insulating substrate. Can be included. That is, the conductive layer may include those in which a through hole or a via hole is not formed in a substantial portion of the insulating substrate on which the conductive layer is formed. Therefore, both the through hole or the via hole and the anchor hole may be included. Some are formed, and some are formed only one of them.

[0039] このような導電層は、前記絶縁性基体の表裏両面に直接形成されるとともに、前記 スルホール等(後述のアンカーホールを含む、以下同じ)の壁面にも形成され、また ビアホール等(後述のアンカーホールを含む、以下同じ)に対してはその内部を充填 するようにして形成されるものである。また、該導電層は、該スルホール等の壁面また は該ビアホール等の内部と、該絶縁性基体の表裏両面とにおいて同一の構成を有 するようにして形成される。  [0039] Such a conductive layer is formed directly on both the front and back surfaces of the insulative substrate, and also formed on the wall surface of the through hole or the like (including an anchor hole to be described later, the same applies hereinafter). (The same applies to the following), which is formed so as to fill the inside. Further, the conductive layer is formed so as to have the same configuration on the wall surface such as the through hole or the inside of the via hole and the front and back surfaces of the insulating substrate.

[0040] ここで、該導電層が絶縁性基体上に直接形成されるとは、接着剤などを介さずに直 接絶縁性基体と接するようにして形成されることを意味し、絶縁性基体の表裏両面だ けではなくスルホールやビアホール等においても絶縁性基体と直接接するようにして 形成されるものである。これにより、従来接着剤を使用することに起因して発生してい た諸問題を解消することに成功したものであり、特に回路パターンのファイン化を可 能としたものである。  Here, that the conductive layer is formed directly on the insulating substrate means that the conductive layer is formed so as to be in direct contact with the insulating substrate without using an adhesive or the like. It is formed so as to be in direct contact with the insulating substrate not only on the front and back surfaces but also in through holes and via holes. As a result, the present invention has succeeded in solving various problems caused by the use of the adhesive in the related art, and in particular, has enabled finer circuit patterns.

[0041] このような絶縁性基体の表裏両面の導電層は、スルホールまたはビアホールを介し て互いに電気的に接続されるものである力 ここでスルホールを介して電気的に接続 されるとは、具体的にはこのように絶縁性基体の表裏両面に直接形成されている導 電層がスルホールの壁面に形成される同一構成の導電層により電気的に接続されて レ、ることを意味している。また、ビアホールを介して電気的に接続されるとは、このよう に絶縁性基体の表裏両面に直接形成されている導電層力 ビアホールの内部に充 填される同一構成の導電層により電気的に接続されていることを意味している。この ように、スルホールの壁面の導電層またはビアホールの内部に充填される導電層と、 絶縁性基体の表裏両面の導電層とが同一の構成を有することにより、信頼性の高い 電気的接続が可能となる。 The conductive layers on the front and back surfaces of such an insulating substrate are electrically connected to each other through through holes or via holes. Here, the term “electrically connected through through holes” specifically means In general, the conductors directly formed on the front and back surfaces of the insulating substrate This means that the conductive layer is electrically connected by the conductive layer of the same configuration formed on the wall surface of the through hole. The term “electrically connected via the via hole” means that the conductive layer formed directly on the front and back surfaces of the insulating substrate is electrically connected by the conductive layer of the same configuration filled inside the via hole. It means connected. As described above, since the conductive layer on the wall surface of the through hole or the conductive layer filling the inside of the via hole and the conductive layer on the front and back surfaces of the insulating substrate have the same configuration, highly reliable electrical connection is possible. It becomes.

[0042] このような導電層は、電気導電性の作用を有する限りその組成が特に限定されるも のではないが、 Cu、 Ni、 Cr、 Ag、 Au、 Zn、 Ti、 Pd、 Sn、 Biおよび Coからなる群から 選ばれた少なくとも一種の金属または前記金属を少なくとも一種含む合金により構成 されることが好ましぐ単一層として形成することができるとともに、同一組成のものあ るいは異なった組成のものを複数層積層して形成することもできる。 [0042] The composition of such a conductive layer is not particularly limited as long as it has an electric conductivity function. However, Cu, Ni, Cr, Ag, Au, Zn, Ti, Pd, Sn, Bi And at least one metal selected from the group consisting of Co and Co or an alloy containing at least one of the above metals, and may be formed as a single layer, and may have the same composition or different compositions. Can be formed by laminating a plurality of layers.

[0043] 上記導電層がスルホール等の壁面またはビアホール等の内部と、絶縁性基体の表 裏両面とにおいて同一の構成を有するとは、上記のような積層状態が同一であること を意味し、必ずしもその層の厚さまでもが同一であることを意味するものではない。  [0043] The fact that the conductive layer has the same configuration on the wall surface such as a through hole or the inside of a via hole and on the front and back surfaces of the insulating substrate means that the above-mentioned laminated state is the same, It does not necessarily mean that the thicknesses of the layers are the same.

[0044] また、上記導電層は、前記スルホールの壁面または前記ビアホールの内部と、前記 絶縁性基体の表裏両面とにおいて、同一の工程で形成されることが好ましい。なお、 同一の工程で形成する方法については、後述する。  Further, it is preferable that the conductive layer is formed in the same step on the wall surface of the through hole or inside the via hole and on both the front and back surfaces of the insulating substrate. In addition, a method of forming in the same step will be described later.

[0045] このような導電層は、スパッタリング法または蒸着法により形成される第 1導電層と、 無電解めつき法または電気めつき法により形成される第 2導電層とを含むことができる 。本発明においては、これらの第 1導電層および第 2導電層がそれぞれ単層または 複数層積層されて、導電層を構成することができる。  [0045] Such a conductive layer can include a first conductive layer formed by a sputtering method or a vapor deposition method, and a second conductive layer formed by an electroless plating method or an electroplating method. In the present invention, the first conductive layer and the second conductive layer may be formed as a single layer or a plurality of layers, respectively, to form a conductive layer.

[0046] <第 1導電層 >  <First conductive layer>

本発明の第 1導電層は、前記絶縁性基体上に直接形成されるものであり、上記に 示した金属または該金属を少なくとも一種含む合金、より好ましくは Cu、 Ag、 Sn、 Ni 、 Cr、 Co、 Tほたは Znから選ばれる少なくとも一種の金属または該金属を少なくとも 一種含む合金をスパッタリング法または蒸着法により形成することができる。この第 1 導電層は、後述の第 2導電層を形成するための言わば下地層としての作用を有する ものであり、第 2導電層の絶縁性基体に対する密着性を向上させる作用を有するもの である。 The first conductive layer of the present invention is formed directly on the insulating substrate, and the above-mentioned metal or an alloy containing at least one metal, more preferably Cu, Ag, Sn, Ni, Cr, Co and T can be formed by sputtering or vapor deposition of at least one metal selected from Zn or an alloy containing at least one metal. This first conductive layer has a function as a so-called underlayer for forming a second conductive layer described later. And has the function of improving the adhesion of the second conductive layer to the insulating substrate.

[0047] このような第 1導電層は、 500— 5000A、好ましくは 1000— 3000Aの厚みで形 成することが好適である。 500 A未満では、後述の第 2導電層の密着性を向上させる 作用を十分に示すことができず、また 5000Aを超えても第 2導電層の密着性に大差 なく却ってコスト的に不利となる。  [0047] Such a first conductive layer is preferably formed to a thickness of 500 to 5000A, preferably 1000 to 3000A. If it is less than 500 A, the effect of improving the adhesion of the second conductive layer described later cannot be sufficiently exhibited, and even if it exceeds 5000 A, the adhesion of the second conductive layer will not be substantially different and disadvantageously in terms of cost. .

[0048] このような第 1導電層は、前述の通り 1層(単層)または 2層以上 (複数層)積層して 形成することができ、 2層以上積層される場合は全体として上記厚みを有するものと すること力 Sできる。  [0048] As described above, such a first conductive layer can be formed by forming one layer (single layer) or by laminating two or more layers (a plurality of layers). The ability to have

[0049] なお、この第 1導電層を 2層以上積層する場合は、絶縁性基体上にまず Ni、 Cr、 Ti 、Znまたは Coから選ばれる少なくとも一種の金属または該金属を少なくとも一種含 む合金を積層し、その上に Cu、 Ag、 Snまたは Znから選ばれる少なくとも一種の金属 または該金属を少なくとも一種含む合金を積層させることが好ましい。  When two or more first conductive layers are stacked, first, at least one metal selected from Ni, Cr, Ti, Zn, or Co or an alloy containing at least one metal on the insulating substrate Are laminated, and at least one metal selected from Cu, Ag, Sn or Zn or an alloy containing at least one metal is preferably laminated.

[0050] 前記 Cu、 Ag、 Snまたは Znから選ばれる少なくとも一種の金属または該金属を少な くとも一種含む合金は、良好な電気特性を有しかつ第 2導電層との密着性にも優れ、 また比較的安価であることからこのような用途に用いることが有利であるが、容易に酸 化され電気特性が害されるという問題を有している。そこで、この酸化の問題を解消 するためにこのような層の下に(すなわち絶縁性基体との間に)耐酸化性を有する金 属、たとえば Ni、 Cr、 Ti、 Znまたは Coから選ばれる少なくとも一種の金属または該金 属を少なくとも一種含む合金を形成すれば、酸化による経時的な密着力の劣化を防 止すること力 Sできる。  [0050] The above-mentioned at least one metal selected from Cu, Ag, Sn or Zn or an alloy containing at least one such metal has good electrical properties and excellent adhesion to the second conductive layer, In addition, since it is relatively inexpensive, it is advantageous to use it for such an application, but it has a problem that it is easily oxidized and the electric characteristics are impaired. Therefore, in order to solve this oxidation problem, at least an oxidation-resistant metal such as Ni, Cr, Ti, Zn or Co selected under such a layer (ie, between the insulating substrate). By forming one kind of metal or an alloy containing at least one such metal, it is possible to prevent the deterioration of the adhesive force over time due to oxidation.

[0051] このような耐酸化性を有する金属からなる層は、その厚みを 10— 200A、好ましく は 30 70Aとすることが好適である。 10A未満の場合は、耐酸化性の作用を十分 に示さない場合があり、また 200Aを超えると回路パターンを形成する際にエツチン グが困難となる場合がある。  [0051] The thickness of such a layer made of a metal having oxidation resistance is preferably 10 to 200A, more preferably 3070A. If it is less than 10 A, the effect of oxidation resistance may not be sufficiently exhibited, and if it exceeds 200 A, etching may be difficult when forming a circuit pattern.

[0052] <第 2導電層 >  [0052] <Second conductive layer>

本発明の第 2導電層は、前記第 1導電層上に形成されるものであり、導電層として 上記に示した金属または該金属を少なくとも一種含む合金、より好ましくは Cu、 Ag、 Sn、 Ni、 Bほたは Znから選ばれる少なくとも一種の金属または該金属を少なくとも一 種含む合金を無電解めつき法または電気めつき法により適用することにより形成され るものである。これらの金属または合金の中でも、特に好ましくは Cuであり、硫酸銅を 電気めつきして形成するものが特に好ましい。コスト的に安価であり、電気的接続の 信頼度が高ぐまた生産効率にも優れるからである。 The second conductive layer of the present invention is formed on the first conductive layer, and as the conductive layer, the metal described above or an alloy containing at least one metal, more preferably Cu, Ag, Sn, Ni, and B are formed by applying at least one metal selected from Zn or an alloy containing at least one metal by an electroless plating method or an electroplating method. Among these metals or alloys, Cu is particularly preferred, and those formed by electroplating copper sulfate are particularly preferred. This is because it is inexpensive, has high reliability in electrical connection, and has excellent production efficiency.

[0053] このような第 2導電層は、前記第 1導電層よりも厚く形成することにより主として電気 導電性および機械的強度を付与する作用を奏するものである。また、この第 2導電層 は、電気導電性を示すことから絶縁性基体の表裏両面で対向するように配置すれば コンデンサとしての作用も示すことができる。  [0053] Such a second conductive layer mainly has an effect of imparting electric conductivity and mechanical strength by being formed thicker than the first conductive layer. In addition, since the second conductive layer has electrical conductivity, it can also function as a capacitor if it is arranged so as to face both sides of the insulating substrate.

[0054] このような第 2導電層は、 0. 5 50 x m、好ましくは 4一 38 z mの厚みで形成する ことが好適である。 0. 未満では、十分な電気導電性が得られず電気抵抗が大 きくなり過ぎるという問題があり、また 50 μ mを超えても電気導電性に大差なく却って コスト的に不利となる。  [0054] Such a second conductive layer is preferably formed with a thickness of 0.550 x m, preferably 4-1 38zm. If it is less than 0, there is a problem that sufficient electrical conductivity cannot be obtained and the electrical resistance becomes too large. Even if it exceeds 50 μm, there is no significant difference in electrical conductivity, which is disadvantageous in cost.

[0055] このような第 2導電層は、前述の通り 1層(単層)または 2層以上 (複数層)積層して 形成することができ、 2層以上積層される場合は全体として上記厚みを有するものと すること力 Sできる。  As described above, such a second conductive layer can be formed as a single layer (single layer) or a laminate of two or more layers (a plurality of layers). The ability to have

[0056] なお、この第 2導電層は、比較的厚く形成させる場合には電気めつき法を採用して 形成することが好ましぐまた比較的薄く形成させる場合には、無電解めつき法を採 用して形成することが好ましレ、。  The second conductive layer is preferably formed by using an electroplating method when forming a relatively thick layer, and an electroless plating method when forming the second conductive layer relatively thin. It is preferable to adopt and form.

[0057] <アンカーホーノレ >  [0057] <Anchor Honoré>

本発明におけるアンカーホールとは、前記絶縁性基体の表裏を物理的に貫通する ように設けられている小孔である力 前述のスルホールまたはビアホールと異なりこの アンカーホールを介しては、前記導電層は絶縁性基体の他方の面に存在する導電 層と電気的に接続することはない。  The anchor hole in the present invention is a force that is a small hole provided so as to physically penetrate the front and back of the insulating substrate. Unlike the above-described through hole or via hole, the conductive layer is formed through the anchor hole. There is no electrical connection with the conductive layer present on the other surface of the insulating substrate.

[0058] このようなアンカーホールは、その壁面に導電層を有するか、またはその内部に導 電層が充填されていることにより、前記導電層の前記絶縁性基体に対する密着性を 向上させる作用を奏するものである。たとえば、図 3Aに示すようにアンカーホール 5 の壁面には、スルホールのように導電層 3を形成することができ、また図 3Bに示すよ うにアンカーホール 5の内部には、ビアホールのように導電層 3を充填することもでき る。 [0058] Such an anchor hole has a function of improving the adhesion of the conductive layer to the insulating substrate by having a conductive layer on the wall surface or filling the inside with the conductive layer. To play. For example, as shown in FIG. 3A, the conductive layer 3 can be formed on the wall surface of the anchor hole 5 like a through hole, and as shown in FIG. 3B. As described above, the inside of the anchor hole 5 can be filled with the conductive layer 3 like a via hole.

[0059] 本発明においては、前述のスルホールやビアホールと同様、絶縁性基体に対して このアンカーホールを形成した後に前記導電層を形成することが好ましい。これによ り、絶縁性基体の表裏両面の導電層とアンカーホール内の導電層とを一体的に形成 することが可能となり、生産効率の向上に資することができるとともに、導電層と絶縁 性基体間の密着性をさらに向上させることができる。  [0059] In the present invention, it is preferable to form the conductive layer after forming the anchor hole in the insulating substrate as in the case of the through hole and the via hole described above. This makes it possible to integrally form the conductive layers on both the front and back surfaces of the insulating substrate and the conductive layer in the anchor hole, thereby contributing to an improvement in production efficiency, as well as improving the efficiency of the conductive layer and the insulating substrate. Adhesion between them can be further improved.

[0060] このようなアンカーホールの形状は、前記絶縁性基体の表裏を貫通する限り特に限 定されることはないが、好ましくは前記絶縁性基体の表裏両面において開孔面積が 異なっていることが好ましい。すなわち、図 3Cに示したように前記導電層が形成され る方の面の開孔面積を、導電層が形成されていない方の面の開孔面積よりも小さく することにより、導電層の絶縁性基体に対する密着性を更に向上させることができる。  [0060] The shape of such an anchor hole is not particularly limited as long as it penetrates the front and back surfaces of the insulating base, but preferably the opening areas of the front and back surfaces of the insulating base are different. Is preferred. That is, as shown in FIG. 3C, the insulating area of the conductive layer is reduced by making the opening area of the surface on which the conductive layer is formed smaller than the opening area of the surface on which the conductive layer is not formed. The adhesion to the conductive substrate can be further improved.

[0061] このようなアンカーホールの内径は、 5— 300 μ m、好ましくは 10— 200 μ mとする ことが好適である。その内径が 5 / m未満である場合、開孔が困難となり加工コストが 高くなるとともに、 300 μ ΐηを超えると導電層の幅方向の長さに対するアンカーホー ルの径が大きくなり過ぎ有効な回路スペースの確保や電気的接続に問題を生じる場 合がある。したがって、アンカーホールの内径は、加工コストが高くならない範囲内で 小さく形成する方が回路設計上有利である。  [0061] The inner diameter of such an anchor hole is preferably 5 to 300 µm, and more preferably 10 to 200 µm. If the inner diameter is less than 5 / m, drilling becomes difficult and the processing cost increases, and if it exceeds 300 μ ア ン カ ー η, the diameter of the anchor hole becomes too large with respect to the length in the width direction of the conductive layer. Problems may occur in securing space and electrical connection. Therefore, it is more advantageous in terms of circuit design to form the inner diameter of the anchor hole as small as possible without increasing the processing cost.

[0062] また、このようなアンカーホールは、該絶縁性基体の表面において島状に存在する 導電層 1つ当りに 1以上、好ましくは 1一 30、更に好ましくは 3— 10、その導電層が形 成されてレ、る絶縁性基体の相当部分にぉレ、て形成されてレ、ることが好ましレ、。島状 に存在する導電層 1つ当りにアンカーホールを全く形成しなレ、と、導電層と絶縁性基 体間の密着性に問題が生じる場合があり、またあまりに多数のアンカーホールを形成 すると、導電層に占めるアンカーホールの面積が大きくなり、回路設計上の自由度が 低下するとともに、加工効率も低下することとなるため、島状に存在する導電層 1つ当 りに 30個程度までとすることが好ましレ、。  [0062] Further, such an anchor hole is formed in an island shape on the surface of the insulative substrate at one or more, preferably one to thirty, more preferably three to ten, and more preferably three to ten, conductive layers. It is preferable to form and form a substantial part of the insulating substrate. If an anchor hole is not formed at all for each conductive layer existing in the shape of an island, there may be a problem in the adhesion between the conductive layer and the insulating substrate, and if too many anchor holes are formed, However, since the area of the anchor hole in the conductive layer increases, the degree of freedom in circuit design decreases, and the processing efficiency also decreases.Therefore, up to about 30 conductive layers per island-shaped conductive layer Les, which you prefer.

[0063] ここで、島状に存在する導電層とは、前記で説明したのと同様の導電層を意味する 。すなわち、図 2に示すように、該絶縁性基体 2の表裏両面には、その同一の表面内 の他の導電層 3bおよび 3cとは電気的に接続していない導電層 3aが少なくとも 1以上 形成されており、該導電層の 1以上(図 2においては少なくとも導電層 3aまたは導電 層 3b、 3c)が形成されている絶縁性基体の相当部分において、上記アンカーホール 5が 1以上形成されていることが好ましい。 Here, the conductive layer existing in an island shape means the same conductive layer as described above. That is, as shown in FIG. 2, on both front and back surfaces of the insulating substrate 2, the same surface is provided. At least one or more conductive layers 3a not electrically connected to the other conductive layers 3b and 3c are formed, and at least one of the conductive layers (in FIG. 2, at least the conductive layer 3a or the conductive layers 3b, 3c It is preferable that one or more of the anchor holes 5 are formed in a substantial portion of the insulating substrate on which the above ()) is formed.

[0064] また、このようなアンカーホール 5は、絶縁性基体 2において上記導電層の屈曲部 7 や、長い直線状の場所に相当する部分に形成することが特に有効である。また、導 電層の幅が狭い場所や、はんだ付け部 8等に相当する部分に形成することも有効で ある。導電層のそのような場所において、絶縁性基体との密着性が不足する傾向に あるからである。 Further, it is particularly effective to form such an anchor hole 5 in the insulating substrate 2 at the bent portion 7 of the conductive layer or at a portion corresponding to a long linear place. It is also effective to form the conductive layer in a place where the width is small, or in a portion corresponding to the soldered portion 8 or the like. This is because, in such a place of the conductive layer, the adhesion to the insulating substrate tends to be insufficient.

[0065] このようなアンカーホールは、従来公知の開孔方法(穴開け加工方法)であれば特 に限定することなくいずれの方法によっても開孔することができる。たとえば、 COレ 一ザ、 YAGレーザ、エキシマレーザ等の各種レーザ、ドリル、パンチ、プレスなどの 開孔手段により絶縁性基体を貫通するようにして開孔される。特にスルホールの内径 力 ¾0 μ ΐηよりも小さくなる場合は、各種レーザにより開孔することが好ましい。  [0065] Such an anchor hole can be opened by any conventionally known opening method (drilling method) without any particular limitation. For example, holes are formed so as to penetrate the insulating substrate by means of various lasers such as a CO laser, a YAG laser, an excimer laser, and the like, drills, punches, presses, and the like. In particular, when the inner diameter force of the through hole is smaller than ¾0 μΐη, it is preferable to open the hole by using various lasers.

[0066] <アンカー層 >  [0066] <Anchor layer>

本発明のアンカー層は、電気的接続を目的とせず、導電層の絶縁性基体への密 着性の向上を目的として形成されるものである。図 3A、図 3Bに示したように、該アン カー層 6は、アンカーホール 5を介して他方の面の導電層 3と接続されている力 同 一の面内に存在する導電層と接続することはない。  The anchor layer of the present invention is formed not for the purpose of electrical connection but for the purpose of improving the adhesion of the conductive layer to the insulating substrate. As shown in FIGS. 3A and 3B, the anchor layer 6 is connected to a conductive layer existing in the same plane as the force connected to the conductive layer 3 on the other surface via the anchor hole 5. Never.

[0067] このようなアンカー層は、前記導電層と同様の組成および同様の積層構成(第 1導 電層および第 2導電層と同様の組成および厚みのものを含み得る)を有するものであ つて、上記アンカーホールが開孔された後に導電層と同一の工程で形成後、エッチ ング等されることにより同一面内の導電層と絶縁されるようにして形成することが好ま しい。なお、導電層の詳細な形成方法については、次に説明する。  [0067] Such an anchor layer has the same composition and the same laminated structure as the conductive layer (may have the same composition and thickness as the first conductive layer and the second conductive layer). After the anchor holes are formed, it is preferable that the holes are formed in the same step as the conductive layer, and then formed by etching or the like so as to be insulated from the conductive layer in the same plane. Note that a detailed method for forming the conductive layer will be described below.

[0068] ぐ導電層の形成方法 >  [0068] Method of forming conductive layer>

本発明の前記導電層は、前記絶縁性基体にスルホール、ビアホールまたはアンカ 一ホールが開孔された後、該絶縁性基体の表裏両面と該スルホール等(アンカーホ ールを含む、以下同じ)の壁面またはビアホール等(アンカーホールを含む、以下同 じ)の内部とにおいて同一工程で形成されるものとすることが好ましい。これにより、絶 縁性基体の表裏両面の導電層とスルホール等の壁面またはビアホール等の内部の 導電層とを一体的に形成することが可能となり、生産効率の向上に資することができ るとともに、信頼性の高い電気的接続を保証することができる。また、導電層と絶縁性 基体との密着性の向上にも資するものとなる。 The conductive layer according to the present invention is characterized in that, after a through hole, a via hole or an anchor hole is formed in the insulating substrate, the front and back surfaces of the insulating substrate and the wall surfaces of the through hole and the like (including anchor holes, the same applies hereinafter). Or via holes (including anchor holes, hereinafter the same) It is preferable that they are formed in the same step inside the same step. This makes it possible to integrally form the conductive layers on both the front and back surfaces of the insulating substrate and the conductive layers inside the wall surfaces such as through holes or via holes, thereby contributing to the improvement of production efficiency. Reliable electrical connections can be guaranteed. It also contributes to improving the adhesion between the conductive layer and the insulating substrate.

[0069] ここで、導電層が同一工程で形成されるとは、該絶縁性基体の表裏両面と、該スル ホール等の壁面または該ビアホール等の内部とにおいて該導電層が同時的かつ一 体的に形成されることを意味している。  Here, that the conductive layer is formed in the same step means that the conductive layer is formed simultaneously and integrally on both the front and back surfaces of the insulating substrate and the wall surface such as the through hole or the inside of the via hole. It is meant that it is formed in a typical way.

[0070] すなわち、たとえば該導電層が第 1導電層と第 2導電層とを含む場合、まず第 1導 電層が該絶縁性基体の表裏両面と該スルホール等の壁面または該ビアホール等の 内部とに対してスパッタリング法または蒸着法により同時的かつ一体的に形成され、 続いて第 2導電層が該第 1導電層上に対して無電解めつき法または電気めつき法に より同時的かつ一体的に形成されるような場合が含まれる。なお、該ビアホール等の 内部を該絶縁性基体の表裏両面と同時的かつ一体的に導電層により充填する場合 、第 1導電層は主としてビアホールの壁面に形成され、その第 1導電層上に形成され る第 2導電層によりホール内が充填され、空洞部が坦められることになる。  [0070] That is, for example, when the conductive layer includes a first conductive layer and a second conductive layer, first, the first conductive layer is formed on both the front and back surfaces of the insulative base and the wall surface such as the through hole or the inside of the via hole. And a second conductive layer is formed on the first conductive layer simultaneously by an electroless plating method or an electroplating method. The case where it is formed integrally is included. When the inside of the via hole or the like is simultaneously and integrally filled with the conductive layer on the front and back surfaces of the insulating substrate, the first conductive layer is mainly formed on the wall surface of the via hole and formed on the first conductive layer. The hole is filled with the second conductive layer to be filled, and the cavity is filled.

[0071] このように、導電層が第 1導電層と第 2導電層を含む場合や、それぞれの層が複数 層積層される場合には、各層が上記のように同時的かつ一体的に形成される限り、 導電層が同一工程で形成されるものとする。  As described above, when the conductive layer includes the first conductive layer and the second conductive layer, or when the respective layers are stacked in a plurality of layers, each layer is formed simultaneously and integrally as described above. As far as possible, the conductive layers are formed in the same step.

[0072] なお、該導電層がスパッタリング法や蒸着法により形成される場合であって、加工 装置の特性等により絶縁性基体の表裏両面を一度に処理することができない場合に おいて、表と裏それぞれについて二回の操作で導電層が形成されるとしても、表裏 両面の導電層と、スルホール等の壁面またはビアホール等の内部の導電層とは同一 工程で形成されるものとする。またこの場合、スルホール等の壁面またはビアホール 等の内部の導電層は、この二回の操作のそれぞれの操作によりホールの中位の高さ (深さ)まで形成されると考えられ、結局二回の操作によりスルホール等の壁面または ビアホール等の内部全体に導電層が形成されるものと考えられる。また、該ホールの 中位の高さ(深さ)部分において導電層が加重的に積層されていたとしても、その部 分の構成は絶縁性基体の表面部の導電層の構成と同一の構成とみなすものとする。 In the case where the conductive layer is formed by a sputtering method or a vapor deposition method, and when the front and back surfaces of the insulating substrate cannot be treated at one time due to the characteristics of a processing apparatus or the like, the front and rear surfaces are different. Even if a conductive layer is formed by performing two operations on each of the back surfaces, the conductive layers on both the front and back surfaces and the conductive layers inside the wall surfaces such as through holes or via holes are formed in the same process. In this case, the conductive layer inside the wall such as the through hole or the via hole is considered to be formed to the middle height (depth) of the hole by each of these two operations. It is considered that the above operation forms a conductive layer on the entire wall surface such as a through hole or via hole. Further, even if the conductive layer is weighted and stacked at the middle height (depth) portion of the hole, It is assumed that the configuration is the same as the configuration of the conductive layer on the surface of the insulating substrate.

[0073] このように導電層を同一工程で形成することにより、従来、絶縁性基体の表裏両面 にまず導電層を形成させた後、スルホールまたはビアホールを開孔させ、その後改 めてそのスルホールの壁面またはビアホールの内部に対して導電層を形成させてい た方法と比較して、導電層の形成工程の回数を半減化することができるため、生産効 率を大きく向上させることが可能となった。し力、も、同一工程で一体的に形成されるた め、信頼性の高い接続効果が得られる。  As described above, by forming the conductive layer in the same step, conventionally, a conductive layer is first formed on both the front and back surfaces of the insulating substrate, then a through hole or a via hole is opened, and then the through hole is formed again. Compared to the method in which the conductive layer is formed on the wall surface or inside the via hole, the number of steps for forming the conductive layer can be halved, thereby greatly improving the production efficiency. . Since the resilient force is integrally formed in the same process, a highly reliable connection effect can be obtained.

[0074] また、上記のような従来法においては、スルホールの壁面またはビアホールの内部 のみに対して選択的に導電層を形成させることは困難であり、どうしても絶縁性基体 上に予め形成されている導電層の上にまで回り込む形で導電層が形成されてしまう 。しかし、これでは導電層の厚みが加重されて形成されることとなり、このように絶縁性 基体上の導電層の厚みが厚くなると、回路を形成する加工が困難となり寸法精度そ のものも悪化する。これに対して、本発明の上記形成方法によれば、導電層の厚み が加重されることがなぐもって可能な限り導電層の厚みを薄くすることが可能となり、 回路パターンのファイン化に資するとともに寸法精度を悪化することもなレ、。  In the conventional method as described above, it is difficult to selectively form the conductive layer only on the wall surface of the through hole or inside the via hole, and it is inevitably formed in advance on the insulating substrate. The conductive layer is formed so as to extend over the conductive layer. However, in this case, the thickness of the conductive layer is weighted and formed, and when the thickness of the conductive layer on the insulating substrate is increased in this manner, processing for forming a circuit is difficult and dimensional accuracy itself is deteriorated. . On the other hand, according to the forming method of the present invention, the thickness of the conductive layer can be reduced as much as possible without the weight of the conductive layer being weighted, which contributes to finer circuit patterns. Dimensional accuracy may not deteriorate.

[0075] なお、前記アンカーホールを介して絶縁性基体の表裏両面に導電層が形成される ことはないため、導電層を形成しない方の表面に存在する導電層は、エッチング等に より除去される。あるいは、アンカーホールの該当箇所に予めマスクをしておき、その 箇所に導電層が形成されないようにすることもできる。また、そのような導電層をエツ チングにより完全に除去するのではなぐ一部残存させることによりアンカー層が形成 できることは前述の通りである。  Since the conductive layer is not formed on both the front and back surfaces of the insulating substrate via the anchor hole, the conductive layer existing on the surface where the conductive layer is not formed is removed by etching or the like. You. Alternatively, a mask may be preliminarily applied to a corresponding portion of the anchor hole so that the conductive layer is not formed at that portion. Further, as described above, the anchor layer can be formed by leaving such a conductive layer partially instead of completely removing it by etching.

[0076] くその他〉  [0076] Others>

本発明の絶縁性基体には、ァライメントマークを形成することができる。当該ァライメ ントマークはスルホールやビアホール等の所定の位置を決定する基準となるものであ り、通常絶縁性基体の両端 (スルホールやビアホール等の設けられてレ、なレ、位置)に 形成するのが好適である。  An alignment mark can be formed on the insulating substrate of the present invention. The alignment mark serves as a reference for determining a predetermined position of a through hole, a via hole, and the like, and is usually formed at both ends of the insulating substrate (where a through hole, a via hole, and the like are provided, a position, and a position). It is suitable.

[0077] このようなァライメントマークは光学的、電子的、磁気的、 目視的あるいはその他の 読み取り手段によりスルホールやビアホール等の所定の位置を決定できるものであ ればいかなるものであっても差し支えなぐまたその形成方法としても特に限定される ものではない。たとえば、 目視的に読み取る場合にはこのァライメントマークとして絶 縁性基体の両端にこの基体を貫通させるようにしてホールを開けたものが好適である 。そしてこのホール (ァライメントホールと呼ぶ)はさらに好ましくは一定の間隔を持って 連続的に開孔させるのが好適である。このような構成を取ることによりスルホールの位 置をさらに簡単に決定することができるようになるからである。 [0077] Such an alignment mark can determine a predetermined position such as a through hole or a via hole by optical, electronic, magnetic, visual, or other reading means. Any material may be used as long as it is formed, and the method of forming the material is not particularly limited. For example, in the case of visual reading, it is preferable that the alignment mark is formed by making holes at both ends of the insulating substrate so as to penetrate the substrate. The holes (referred to as alignment holes) are more preferably continuously opened at regular intervals. By adopting such a configuration, the position of the through hole can be more easily determined.

[0078] このようなァライメントホールの大きさとしては、通常 5 μ m 3mm程度とするのが好 ましぐ各種レーザ、ドリル、パンチ、プレスなどにより開孔させることが可能である。こ のようなァライメントホールが、 80 x mよりも小さレ、場合には、各種レーザを用いること が好ましい。  The size of such an alignment hole is usually preferably about 5 μm 3 mm, and the hole can be formed by various lasers, drills, punches, presses, or the like. When such an alignment hole is smaller than 80 x m, it is preferable to use various lasers.

[0079] また、このようなァライメントホールは上記のスルホールと同様、その内壁面に導電 層が形成されてレ、ても差し支えなレ、。  [0079] Further, like the above-mentioned through hole, a conductive layer is formed on the inner wall surface of such an alignment hole.

[0080] 一方、前記導電層上には、集積回路用結合層や酸化防止層を形成することができ る。該集積回路用結合層は、集積回路 (ICチップや LSI)を絶縁性基体に搭載させる ことを容易化する作用を有するものであり、上記導電層と集積回路を直接電気的に 接続するものである。また、該酸化防止層は、導電層が酸化され導電性が示されなく なったり、絶縁性基体との密着性が不良となることを防止する作用を有するものであ る。  On the other hand, a bonding layer for an integrated circuit and an oxidation preventing layer can be formed on the conductive layer. The integrated circuit bonding layer has a function of facilitating the mounting of the integrated circuit (IC chip or LSI) on the insulating substrate, and directly electrically connects the conductive layer to the integrated circuit. is there. The antioxidant layer has a function of preventing the conductive layer from being oxidized and exhibiting no conductivity, or preventing poor adhesion to the insulating substrate.

[0081] このような層は、 Sn、 Ni、 Au、 Ag、 Znおよび Crからなる群から選ばれた少なくとも 一種の金属または前記金属を少なくとも一種含む合金により構成することが好ましい  [0081] Such a layer is preferably made of at least one metal selected from the group consisting of Sn, Ni, Au, Ag, Zn, and Cr, or an alloy containing at least one metal.

[0082] また、その厚みは、集積回路用結合層の場合、 0. 2— 15 z m、好ましくは 0. 5-5 z mとすることが好適である。 0. 2 z m未満の場合には、集積回路の搭載容易化と レ、う効果が示されなくなるとともに、 15 x mを超えても集積回路の搭載容易化という 効果に大差なぐ却ってコストが高くなるため好ましくない。 [0082] In the case of a coupling layer for an integrated circuit, the thickness is preferably 0.2 to 15 zm, more preferably 0.5 to 5 zm. If it is less than 0.2 zm, the effect of easy mounting of integrated circuits will not be exhibited, and even if it exceeds 15 xm, the cost will be much higher than the effect of easy mounting of integrated circuits. Not preferred.

[0083] また、酸化防止層の場合、その厚みは 0. 01 2 μ m、好ましくは 0. 05 1 μ mと すること力 S好適である。 0. 01 z m未満の場合には、上記のような作用が示されなくな るとともに、 2 x mを超えても上記作用に大差なぐ却ってコストが高くなるため好まし くない。 In the case of the antioxidant layer, the thickness is preferably 0.012 μm, and more preferably 0.051 μm. If the value is less than 0.01 zm, the above-mentioned effects will not be exhibited, and if the value exceeds 2 xm, the cost will increase rather than the above-mentioned effects. It ’s not.

[0084] このような層は、無電解めつき法、電気めつき法またはクロメート法のいずれかの方 法により、導電層上の全面またはバンプのように部分に、単層または複数層として形 成すること力 Sできる。  [0084] Such a layer may be formed as a single layer or a plurality of layers on the entire surface of the conductive layer or a portion such as a bump by any one of an electroless plating method, an electroplating method, and a chromate method. The ability to generate S.

[0085] 以下、実施例を挙げて本発明をより詳細に説明するが、本発明はこれらに限定され るものではない。  Hereinafter, the present invention will be described in more detail with reference to Examples, but the present invention is not limited thereto.

[0086] ぐ実施例 1 > [0086] Example 1

本発明の導電性シートについて図 1および 2を用いて説明する。  The conductive sheet of the present invention will be described with reference to FIGS.

[0087] まず、絶縁性基体 2として、厚み 50 μ πι、幅 250mm、長さ 100mのポリイミドフィノレ ム(商品名:アビカル、カネボウ製)を、 COレーザ加工機(三菱電機製)にセットした。 First, as an insulating substrate 2, a polyimide finolem (trade name: Avical, manufactured by Kanebo) having a thickness of 50 μππ, a width of 250 mm, and a length of 100 m was set on a CO laser processing machine (manufactured by Mitsubishi Electric). .

2  2

そして、この加工機により図 1および 2に示したように、導電層 3aの先端部 9に相当す る部分に該ポリイミドフィルムの表裏両面を貫通するようにして内径 80 mのスルホ ールを 3ホール 1セット(各ホール間の距離は 120 μ m)として開孔させるとともに、導 電層 3bの所定位置に相当する部分にもスルホールを開孔させた。  Then, as shown in FIGS. 1 and 2, a 80-meter-diameter through-hole was passed through the polyimide film at a portion corresponding to the front end 9 of the conductive layer 3a by this processing machine. Holes were formed as one set (the distance between holes was 120 μm), and through holes were also formed in portions corresponding to predetermined positions of the conductive layer 3b.

[0088] また同時に、導電層 3aの屈曲部 7となる相当部分 2箇所に、該ポリイミドフィルムの 表裏両面を貫通するようにして内径 50 μ mのアンカーホール 5を 2ホール 1セット(各 ホール間の距離は 100 β m)としてそれぞれ開孔させるとともに、導電層 3aのはんだ 付け部 8に相当する部分に、同じく該ポリイミドフィルムの表裏両面を貫通するように して内径 50 /i mのアンカーホール 5を 3ホール 1セット(各ホール間の距離は 100 μ m)として開孔させた。また、導電層 3b、 3cの所定位置に相当する部分にも同じよう にしてアンカーホール 5を開孔させた。 At the same time, two sets of anchor holes 5 each having an inner diameter of 50 μm were formed at two corresponding portions of the conductive layer 3a corresponding to the bent portions 7 so as to penetrate both sides of the polyimide film. The distance is 100 βm ), and an anchor hole 5 having an inner diameter of 50 / im is formed in a portion corresponding to the soldered portion 8 of the conductive layer 3a so as to penetrate both sides of the polyimide film. Was opened as one set of three holes (the distance between each hole was 100 μm). Further, anchor holes 5 were similarly formed in portions corresponding to predetermined positions of conductive layers 3b and 3c.

[0089] 続いて、上記のようにして COレーザにより開孔処理がされた絶縁性基体 2に対し  Subsequently, the insulating substrate 2 that has been subjected to the opening treatment by the CO laser as described above is

2  2

て、該処理時に開孔部およびその周辺に生成した炭化物を取除くため以下の処理 を行なった。すなわち、該絶縁性基体 2をデイスミヤ装置にセットし、液温 60°Cの 50g /1の過マンガン酸カリウム水溶液の浸漬浴に 60秒間浸漬した後、純水による洗浄を 5回繰り返して行なった。  Then, the following treatment was carried out in order to remove the carbide formed in the hole and its periphery during the treatment. That is, the insulating substrate 2 was set in a dismirror apparatus, immersed in an immersion bath of a 50 g / 1 aqueous solution of potassium permanganate at a liquid temperature of 60 ° C. for 60 seconds, and washed with pure water five times. .

[0090] その後さらに、液温 40°Cの 4%の硫酸の浸漬浴に 2分間浸漬させることにより中和 処理した後、再度純水による洗浄を 5回繰り返して行なった。続いて、高性能フィルタ (フィルタの開孔部の大きさが 0· 5 μ m以下)を通した 105°Cの乾燥エアにより水切り を行ない、充分に乾燥させることにより、上記で生成した炭化物を除去した。その後、 絶縁性基体 2をデイスミヤ装置から取出した。 After that, a neutralization treatment was further performed by immersing in a 4% sulfuric acid immersion bath at a liquid temperature of 40 ° C. for 2 minutes, and washing with pure water was repeated five times. Next, the high-performance filter Draining was performed with dry air at 105 ° C passed through (the size of the opening of the filter was 0.5 μm or less), and the carbides generated above were removed by sufficient drying. Thereafter, the insulating substrate 2 was taken out of the dismearing device.

[0091] 次いで、このように炭化物が除去された絶縁性基体 2の一端をスパッタリング装置の 送出しシャフトにセットし、他端を卷取りシャフトにセットした。一方、このスパッタリング 装置の 4つのターゲットには、ターゲット No. 1として Niを、ターゲット No. 2 4として Cuをそれぞれ取付けた。  [0091] Next, one end of the insulating substrate 2 from which the carbide had been removed as described above was set on a delivery shaft of a sputtering device, and the other end was set on a winding shaft. On the other hand, to the four targets of this sputtering apparatus, Ni was attached as target No. 1 and Cu was attached as target No. 24, respectively.

[0092] その後該スパッタリング装置のチャンバ一を閉じ、真空ポンプにより真空度を 1 X 10 — 4Paとした後、 Niを取付けたターゲット No. 1に対してはアルゴンガスの注入量 180c cZ分、ターゲット電流 0. 6kWZdm2、および Cuを取付けたターゲット No. 2— 4に 対してはアルゴンガスの注入量各 250cc/分、ターゲット電流各 1. 2kWZdm2の条 件下でこれらの金属をスパッタリングさせることにより、絶縁性基体の一方の表面上に 第 1導電層を直接形成した。その後、該スパッタリング装置の真空状態を解除した。 [0092] Then close the chamber one said sputtering apparatus, a vacuum degree of 1 X 10 by the vacuum pump - After a 4 Pa, the injection amount of argon gas is the target No. 1, fitted with a Ni 180c cZ min, target current 0. 6kWZdm 2, and is for the target No. 2-4 fitted with a Cu injection volume each 250 cc / min argon gas to sputter these metals under matter conditions of the target current each 1. 2kWZdm 2 Thus, the first conductive layer was formed directly on one surface of the insulating substrate. Then, the vacuum state of the sputtering apparatus was released.

[0093] 続いて、上記の絶縁性基体 2の第 1導電層が形成されていない方の表面に対して 上記と同様の第 1導電層が形成できるように、上記絶縁性基体の表裏を逆にして再 度該スパッタリング装置にセットしなおした。そして、上記と同一の条件でスパッタリン グを行なうことにより絶縁性基体のもう一方の表面に上記と同じ第 1導電層を直接形 成した。  Subsequently, the insulating substrate 2 is turned upside down so that the same first conductive layer as described above can be formed on the surface of the insulating substrate 2 on which the first conductive layer is not formed. Then, it was set again in the sputtering apparatus. Then, the same first conductive layer as described above was directly formed on the other surface of the insulating substrate by performing sputtering under the same conditions as described above.

[0094] これにより、絶縁性基体 2の表裏両面とスルホールおよびアンカーホール 5の壁面 に対して第 1導電層が直接形成され、この第 1導電層は絶縁性基体 2上に Ni層がま ず積層されその上に Cu層が積層された構成となっている。そしてこの構成は絶縁性 基体上の表裏両面とスルホールおよびアンカーホール 5の壁面とにおいて同一の構 成となっている。  As a result, the first conductive layer is formed directly on both the front and back surfaces of the insulating substrate 2 and the wall surfaces of the through hole and the anchor hole 5, and the first conductive layer is formed by first forming the Ni layer on the insulating substrate 2. They are stacked and a Cu layer is stacked on them. This configuration has the same configuration on both the front and back surfaces of the insulating substrate and the wall surfaces of the through hole and the anchor hole 5.

[0095] また、上記の絶縁性基体 2の一方の端から 10m、 50mおよび 90mの地点において サンプリングを行なレ、、 FIB装置を用いて断面をカットしその厚みを測定したところ、 各地点とも絶縁性基体の表裏両面共通で、 Ni層が 70A、 Cu層は 2900Aであった  [0095] Sampling was performed at 10m, 50m, and 90m from one end of the insulating substrate 2, and the cross section was cut using a FIB device to measure the thickness. Both the front and back sides of the insulating substrate were 70 A for the Ni layer and 2900 A for the Cu layer

[0096] 続いて、数回の純水による洗浄を行なった後、表裏両面に上記のようにして第 1導 電層を形成した絶縁性基体 2を連続めつき装置にセットし、以下の条件で電気めつき を行なった。すなわち、まず 7%の硫酸が充填されている液温 28°Cの酸活性化槽に 上記絶縁性基体を 60秒間連続的に浸漬することにより、上記第 1導電層に対して酸 活性化処理を行なった。 [0096] Subsequently, after washing with pure water several times, the first guide was applied to both the front and back surfaces as described above. The insulating substrate 2 on which the electric layer was formed was set in a continuous plating apparatus, and the electric plating was performed under the following conditions. That is, first, the insulating substrate is immersed continuously in an acid activation tank filled with 7% sulfuric acid at a liquid temperature of 28 ° C for 60 seconds, so that the first conductive layer is subjected to an acid activation treatment. Was performed.

[0097] 次いで、純水による水洗を 3回繰り返した後、上記装置のめっき浴にめっき液 (硫酸 銅 100g/l、硫酸 160g/l、塩素 60ppmおよびトツプルチナ 380H (奥野製薬工業( 株)製) lOcc/1からなるもの)を充填し、上記絶縁性基体を 1. OmZ分の移動速度 で連続的に浸漬させ、液温 28°C、電流密度 4AZdm2の条件下で 11分間電気めつ きすることにより、前記第 1導電層上に Cuからなる第 2導電層を形成した。 [0097] Next, after the washing with pure water was repeated three times, the plating solution (copper sulfate 100 g / l, sulfuric acid 160 g / l, chlorine 60 ppm, and toppertina 380H (manufactured by Okuno Pharmaceutical Co., Ltd.)) was added to the plating bath of the above apparatus. filled ones) consisting Locc / 1, the insulating substrate 1. is continuously immersed at a moving speed of OmZ min,-out liquid temperature 28 ° C, under conditions of current density 4AZdm 2 11 minutes electrical flashes Thereby, a second conductive layer made of Cu was formed on the first conductive layer.

[0098] これにより、絶縁性基体 2の表裏両面とスルホールおよびアンカーホール 5の壁面 に対して第 1導電層が形成され、その第 1導電層上に第 2導電層が形成されることに より導電層 3が形成された。なお、第 2導電層の構成は絶縁性基体 2上の表裏両面と スルホールおよびアンカーホール 5の壁面とにおいて同一の構成となっている。した がって、該導電層 3は第 1導電層と第 2導電層とを含み、該絶縁性基体 2の表裏両面 と該スルホールおよび該アンカーホール 5の壁面とにおいて同一の構成を有する導 電層 3が形成されていることになる。  [0098] Thereby, the first conductive layer is formed on both the front and back surfaces of the insulating substrate 2 and the wall surfaces of the through hole and the anchor hole 5, and the second conductive layer is formed on the first conductive layer. The conductive layer 3 was formed. The configuration of the second conductive layer is the same on both the front and back surfaces of the insulating substrate 2 and the wall surfaces of the through hole and the anchor hole 5. Accordingly, the conductive layer 3 includes a first conductive layer and a second conductive layer, and has the same configuration on both the front and back surfaces of the insulating substrate 2 and the wall surfaces of the through hole and the anchor hole 5. Layer 3 has been formed.

[0099] 続いて、このように第 2導電層が形成された絶縁性基体 2に対して純水による水洗 を 5回繰り返して行なった。次いで、高性能フィルタ(フィルタの開孔部の大きさが 0. 5 / m以下)を通した 105°Cの乾燥エアにより水切りを行なレ、、充分に乾燥させた。  [0099] Subsequently, the insulating substrate 2 on which the second conductive layer was formed was repeatedly washed with pure water five times. Next, the mixture was drained with dry air at 105 ° C. through a high-performance filter (the size of the opening of the filter was 0.5 / m or less) and dried sufficiently.

[0100] また、このようにして得られた導電層 3を形成した絶縁性基体 2の一方の端から 10m 、 50mおよび 90mの地点においてサンプリングを行なレ、、 FIB装置を用いて断面を カットし第 2導電層の厚みを測定したところ、各地点(絶縁性基体の表面およびスル ホール、アンカーホールの壁面)とも絶縁性基体の表裏両面共通で、 10 μ πι± 5% 以内であった。  [0100] Sampling was performed at 10m, 50m, and 90m from one end of the insulating substrate 2 on which the conductive layer 3 thus obtained was formed, and the cross section was cut using a FIB device. Then, when the thickness of the second conductive layer was measured, it was within 10 μπι ± 5% at both points (the surface of the insulating substrate and the wall surfaces of the through holes and anchor holes) for both the front and back surfaces of the insulating substrate.

[0101] また、ピール試験装置(MODEL 1305N、アイコ一エンジニアリング (株)製)を用 いて、導電層の絶縁性基体に対する密着性を測定したところ、アンカーホールのある ところでは 3kg/cm2の密着強度が示されたのに対して、アンカーホールのないとこ ろでは 0. 9kg/cm2の密着強度であった。これにより、アンカーホールによる密着性 の向上効果が確認された。 [0101] In addition, peel test apparatus have use the (MODEL 1305N, Aiko one Engineering Co., Ltd.) were measured adhesion to the insulating substrate of the conductive layer, the adhesion of 3 kg / cm 2 is where there is anchor holes Although the strength was shown, the adhesion strength was 0.9 kg / cm 2 where there was no anchor hole. Due to this, adhesion by anchor hole The effect of improvement was confirmed.

[0102] 次いで、上記の絶縁性基体 2の第 2導電層上の全面にレジストとしてドライフィルム( 商品名: NIT215、二チゴーモートン製)を、温度 110°C、圧力 2kg/cm2の条件下で ラミネートさせたることにより、第 2導電層上にレジストを形成した。 Next, a dry film (trade name: NIT215, manufactured by Nichigo Morton) was applied as a resist on the entire surface of the second conductive layer of the insulating substrate 2 under the conditions of a temperature of 110 ° C. and a pressure of 2 kg / cm 2 . Then, a resist was formed on the second conductive layer.

[0103] 続いて、上記の絶縁性基体 2の表裏両面において所望の回路パターン(アンカー 層となる部分もエッチングされずに残るようにデザインされている)をあらわしたマスク を上記のレジスト上に重ね合わせた後、平均露光機(自社製)を用いて光量 120mJ で露光した。次いで、回路を形成しない部分(マスクにより露光されなかった部分)の レジストを除去するため、現像装置を用いて炭酸ソーダ 0. 5gZl、温度 28°C、スプレ 一圧 1. 5kg/cm2の条件下で現像することによりレジストを除去した。その後、純水 による水洗を 5回繰り返して行なった。 Subsequently, a mask representing a desired circuit pattern (designed such that a portion serving as an anchor layer remains without being etched) on both the front and back surfaces of the insulating substrate 2 is overlaid on the resist. After the alignment, exposure was performed at an amount of light of 120 mJ using an average exposure machine (manufactured by the company). Next, in order to remove the resist in the area where the circuit is not formed (the area not exposed by the mask), using a developing device, the conditions of sodium carbonate 0.5 gZl, temperature 28 ° C, spray pressure 1.5 kg / cm 2 were used. The resist was removed by developing underneath. Thereafter, washing with pure water was repeated 5 times.

[0104] 次いで、レジストを除去した部分の導電層(第 1導電層と第 2導電層を含む)をエツ チングにより除去するため、エッチング装置を用いて塩ィ匕第 2鉄 47%、温度 50°C、ス プレー圧 2. 5kg/cm2の条件下でエッチングすることにより導電層を除去した。その 後、純水による水洗を 5回繰り返して行なった。 Next, in order to remove the conductive layer (including the first conductive layer and the second conductive layer) at the portion where the resist was removed by etching, 47% ferric chloride and 50% temperature were used using an etching apparatus. The conductive layer was removed by etching under the conditions of ° C and a spray pressure of 2.5 kg / cm 2 . After that, washing with pure water was repeated 5 times.

[0105] そして、上記でエッチングされていない導電層およびアンカー層上のレジストを剥 離するため、レジスト剥離装置を用いて苛性ソーダ 100g/l、温度 60°C、スプレー圧 2. Okg/cm2の条件下でレジストを剥離することにより、本発明の導電性シート 1を得 た。 [0105] Then, in order to remove the resist on the conductive layer and the anchor layer that were not etched as described above, a resist stripper was used to remove 100% caustic soda, a temperature of 60 ° C, and a spray pressure of 2. Okg / cm 2 . The conductive sheet 1 of the present invention was obtained by removing the resist under the conditions.

[0106] このようにして得られた導電性シート 1について、導電層により形成される回路パタ ーンと、スルホール、アンカーホールおよびアンカー層の位置確認を行なったところ、 いずれも設計寸法に対して ± 5%以内であり、極めて寸法精度に優れるとともに回路 パターンのファイン化が可能なものであった。また、導電層が同時的かつ一体的に形 成されるものであるため、生産効率にも優れていた。  With respect to the conductive sheet 1 thus obtained, the circuit pattern formed by the conductive layer and the positions of the through hole, the anchor hole and the anchor layer were confirmed. It was within ± 5%, which was extremely excellent in dimensional accuracy and allowed fine circuit patterns. In addition, since the conductive layers were formed simultaneously and integrally, the production efficiency was excellent.

[0107] また、該導電性シートは、導電層が形成されている絶縁性基体の相当部分におい て 2以上のスルホールが形成されていることにより信頼性の高い電気的接続性を有し ているとともに、導電層と絶縁性基体との密着性がアンカーホールにより極めて高め られたものであった。 [0108] <実施例 2 > [0107] Further, the conductive sheet has highly reliable electrical connectivity because two or more through holes are formed in a substantial part of the insulating substrate on which the conductive layer is formed. At the same time, the adhesion between the conductive layer and the insulating substrate was greatly enhanced by the anchor holes. <Example 2>

実施例 1におレ、て、スルホールの内径とアンカーホールの内径をそれぞれ 20 μ m とすることを除き、他は全て実施例 1と同様にして導電性シートを得た。  A conductive sheet was obtained in the same manner as in Example 1 except that the inner diameter of the through hole and the inner diameter of the anchor hole were each 20 μm.

[0109] このようにして得られた導電性シートにおいては、実施例 1でスルホールであったも のがビアホールの形態を呈するとともに、アンカーホールにおいてもビアホールのよう にその内部が充填されていた。 [0109] In the conductive sheet thus obtained, the through hole in Example 1 was in the form of a via hole, and the anchor hole was also filled in the inside like a via hole.

[0110] 該導電性シートは、実施例 1のものと同様、極めて寸法精度に優れているとともに 回路パターンのファイン化を可能とするものであった。また、信頼性の高い電気的接 続性を有し、導電層と絶縁性基体との密着性もアンカーホールにより極めて高められ たものであるとともに、生産効率にも優れていた。 [0110] As in the case of Example 1, the conductive sheet was extremely excellent in dimensional accuracy and allowed finer circuit patterns. In addition, it has highly reliable electrical connection, the adhesion between the conductive layer and the insulating substrate is extremely enhanced by the anchor holes, and the production efficiency is excellent.

Claims

請求の範囲 The scope of the claims [1] 絶縁性基体(2)の表裏両面に導電層(3)が直接形成され、その表裏両面に存在 する 1以上の導電層(3)が該絶縁性基体(2)を貫通するようにして開孔されているス ルホールまたはビアホール (4)を介して他方の面に存在する導電層(3)と電気的に 接続されている導電性シート(1)であって、該絶縁性基体(2)の表裏両面にはその 同一の表面内の他の導電層(3b, 3c)とは電気的に接続していない導電層(3a)が 少なくとも 1以上形成されており、該導電層(3)の 1以上が形成されている絶縁性基 体(2)の相当部分にぉレ、て、スルホールまたはビアホール (4)を 2以上形成したととも に、該導電層(3)がスパッタリング法または蒸着法により形成される第 1導電層と、無 電解めつき法または電気めつき法により形成される第 2導電層とを含むことを特徴と する導電性シート(1)。  [1] A conductive layer (3) is directly formed on both the front and back surfaces of the insulating substrate (2), and one or more conductive layers (3) existing on both the front and back surfaces penetrate the insulating substrate (2). A conductive sheet (1) that is electrically connected to a conductive layer (3) on the other surface through a through hole or via hole (4) that has been opened. At least one or more conductive layers (3a) not electrically connected to other conductive layers (3b, 3c) on the same surface are formed on both front and back surfaces of 2). ), Two or more through holes or via holes (4) are formed in a substantial portion of the insulating substrate (2) on which one or more of the conductive layers (3) are formed. It comprises a first conductive layer formed by a vapor deposition method and a second conductive layer formed by an electroless plating method or an electroplating method. Conductive sheets (1). [2] 絶縁性基体(2)の表裏両面に導電層(3)が直接形成され、その表裏両面に存在 する 1以上の導電層(3)が該絶縁性基体(2)を貫通するようにして開孔されているス ルホールまたはビアホール (4)を介して他方の面に存在する導電層(3)と電気的に 接続されている導電性シート(1)であって、該絶縁性基体(2)の表裏両面にはその 同一の表面内の他の導電層(3b, 3c)とは電気的に接続していない導電層(3a)が 少なくとも 1以上形成されており、該導電層(3)は他方の面に存在する導電層(3)と 電気的に接続していない導電層を含み、かつ該導電層(3)の 1以上が形成されてい る絶縁性基体(2)の相当部分にぉレ、て、該絶縁性基体(2)を貫通するようにして開 孔されているアンカーホール(5)を 1以上形成し、該アンカーホール(5)はそれを介 しては他方の面に存在する導電層(3)と電気的に接続することはなぐかつその壁面 に導電層(3)を有するかまたはその内部に導電層(3)が充填されているとともに、該 導電層(3)がスパッタリング法または蒸着法により形成される第 1導電層と、無電解め つき法または電気めつき法により形成される第 2導電層とを含むことを特徴とする導電 性シート(1)。  [2] The conductive layer (3) is directly formed on both the front and back surfaces of the insulating substrate (2), and one or more conductive layers (3) present on both the front and back surfaces penetrate the insulating substrate (2). A conductive sheet (1) that is electrically connected to a conductive layer (3) on the other surface through a through hole or via hole (4) that has been opened. At least one or more conductive layers (3a) not electrically connected to other conductive layers (3b, 3c) on the same surface are formed on both front and back surfaces of 2). ) Includes a conductive layer that is not electrically connected to the conductive layer (3) on the other surface, and a substantial part of the insulating substrate (2) on which one or more of the conductive layer (3) is formed. In addition, at least one anchor hole (5) is formed so as to penetrate the insulating substrate (2), and the anchor hole (5) is formed through the anchor hole (5). Electrically connected to the conductive layer (3) existing on the other side and having the conductive layer (3) on the wall surface or the inside filled with the conductive layer (3). A conductive sheet (1), wherein the layer (3) includes a first conductive layer formed by a sputtering method or a vapor deposition method, and a second conductive layer formed by an electroless plating method or an electroplating method. 1). [3] 前記アンカーホール(5)は、前記絶縁性基体(2)の表裏両面において開孔面積が 異なったものであることを特徴とする請求項 2記載の導電性シート(1)。  3. The conductive sheet (1) according to claim 2, wherein the anchor holes (5) have different opening areas on both front and back surfaces of the insulating substrate (2). [4] 電気的接続を目的とせず、前記導電層(3)の前記絶縁性基体(2)への密着性の 向上を目的とするアンカー層(6) 、前記アンカーホール(5)を介して他方の面の導 電層(3)と接続されていることを特徴とする請求項 2記載の導電性シート(1)。 [4] Adhesion of the conductive layer (3) to the insulating substrate (2) without aiming for electrical connection The conductive sheet (1) according to claim 2, wherein the anchor layer (6) for the purpose of improvement is connected to the conductive layer (3) on the other surface via the anchor hole (5). ). [5] 前記第 1導電層が、 2層以上積層されていることを特徴とする請求項 1記載の導電 性シート(1)。 [5] The conductive sheet (1) according to claim 1, wherein two or more first conductive layers are laminated. [6] 前記第 1導電層が、 2層以上積層されていることを特徴とする請求項 2記載の導電 性シート(1)。  6. The conductive sheet (1) according to claim 2, wherein two or more first conductive layers are laminated. [7] 請求項 1に記載の導電性シート(1)を用いた半導体製品、電気製品、電子製品、 自動車、太陽電池、アンテナ回路基板または ICカード。  [7] A semiconductor product, an electric product, an electronic product, an automobile, a solar cell, an antenna circuit board, or an IC card using the conductive sheet (1) according to claim 1. [8] 請求項 2に記載の導電性シート(1)を用いた半導体製品、電気製品、電子製品、 自動車、太陽電池、アンテナ回路基板または ICカード。 [8] A semiconductor product, an electric product, an electronic product, an automobile, a solar cell, an antenna circuit board or an IC card using the conductive sheet (1) according to claim 2.
PCT/JP2004/009424 2003-07-10 2004-07-02 Conductive sheet having more than one through hole or via hole Ceased WO2005005142A1 (en)

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CN105766069B (en) * 2013-11-20 2019-04-16 株式会社村田制作所 Multilayer wiring board and probe card including the same
JP5807670B2 (en) * 2013-12-19 2015-11-10 株式会社豊田自動織機 Wiring board
JP6662569B2 (en) * 2015-01-07 2020-03-11 Nttエレクトロニクス株式会社 Flexible printed wiring board and mounting method thereof
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JP7385365B2 (en) * 2019-03-14 2023-11-22 株式会社日立国際電気 Sales support system

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