WO2005001842A1 - Ferroelectric storage device - Google Patents

Abstract

A booster circuit generates a boosting voltage higher than a power source voltage. A rewrite control circuit performs rewrite operation, i.e., writing data read from the ferroelectric capacitor consisting of a plurality of memory cells continuously to the previous ferroelectric capacitor by using the boosting voltage. By this rewriting operation, the residual polarization value of the ferroelectric capacitor is increased and the read out margin is increased. By rewriting data continuously to the plurality of memory cells, the rewrite operation is executed within a predetermined period. Thus, it is possible to minimize the operation period of the booster circuit. As a result, it is possible to minimize increase of the power consumption of the ferroelectric storage device and improve the read out margin.

Description

 Description Ferroelectric storage device Technical field

 The present invention relates to a ferroelectric memory device having a ferroelectric capacitor for holding data. In particular, the present invention relates to a low power consumption technology for a ferroelectric memory device. Background art

 A ferroelectric memory device such as FeRAM can hold data even when power is not supplied. The non-volatility of data is achieved by using a ferroelectric capacitor that uses a ferroelectric as an insulating material to operate as a variable capacitor, and that residual polarization remains even when the voltage applied to the ferroelectric capacitor is zero. Is achieved.

 By applying a high voltage when rewriting data, the ferroelectric capacitor improves its data retention characteristics. For example, Japanese Patent Application Laid-Open No. H10-112190 discloses a technique for improving a subsequent read margin by applying a boosted voltage higher than a power supply voltage to a ferroelectric capacitor when rewriting data. .

 However, if the boosted voltage is used for each write operation that is randomly performed in response to an external access request, the booster circuit that generates the boosted voltage must always be operated. Alternatively, the booster circuit must be started for each write operation. As a result, there is a problem that the power consumption of the ferroelectric memory device increases. Hereinafter, prior art documents related to the present invention are listed.

 (Patent Document)

 (1) Japanese Patent Application Laid-Open No. H10-111210-Disclosure of the Invention

 An object of the present invention is to minimize the increase in power consumption, increase the residual polarization value of a ferroelectric capacitor, and improve the read margin.

In one embodiment of the ferroelectric storage device of the present invention, the memory array holds data It is composed of a plurality of memory cells each including a ferroelectric capacitor. The boost circuit generates a boost voltage higher than the power supply voltage. The rewrite control circuit performs a rewrite operation of continuously writing data read from a plurality of ferroelectric capacitors to the original ferroelectric capacitor using the boosted voltage. The rewrite operation increases the remanent polarization value of the ferroelectric capacitor, and increases the read margin in subsequent access. By continuously rewriting data to a plurality of memory cells, the rewriting operation is performed within a predetermined period. Therefore, the operation period of the booster circuit can be minimized. As a result, it is possible to minimize the increase in power consumption of the ferroelectric memory device and improve the read margin.

 In another embodiment of the ferroelectric memory device according to the present invention, the rewrite control circuit continuously rewrites data held in all the memory cells in the memory array. Therefore, the read margin of all memory cells can be improved by the rewrite operation.

 In another embodiment of the ferroelectric memory device according to the present invention, the rewrite control circuit executes a rewrite operation when power to the memory array is cut off. For this reason, the data can be reliably retained while the power is off, and the data can be reliably read after the power is turned on again.

 In another embodiment of the ferroelectric memory device according to the present invention, the controller accesses the memory array and outputs a power cutoff signal when the supply of power to the memory array is cut off. The booster circuit starts the boosting operation in response to the power cutoff signal. The rewrite control circuit starts a rewrite operation in response to the power cutoff signal. By using a controller that controls access to the memory array, the rewrite operation can be performed with a simple circuit.

 In another embodiment of the ferroelectric memory device according to the present invention, the rewrite control circuit executes a rewrite operation when power is supplied to the memory array. For this reason, data can be read reliably after the power is turned on.

In another embodiment of the ferroelectric memory device according to the present invention, the controller accesses the memory array and outputs a power-on signal when starting to supply power to the memory array. The booster circuit starts the boosting operation in response to the power-on signal. The rewrite control circuit starts a rewrite operation in response to the power-on signal. By using a controller that controls access to the memory array, the rewrite operation can be performed with a simple circuit.

 In another embodiment of the ferroelectric memory device of the present invention, the controller accesses the memory array and outputs a rewrite request signal for executing a rewrite operation. The rewrite control circuit starts rewriting in response to a rewrite request signal from the controller. By using a controller that controls access to the memory array, rewrite operations can be performed at any timing.

 In another embodiment of the ferroelectric memory device of the present invention, the booster circuit performs the boost operation only during the rewrite operation. Therefore, the operation period of the booster circuit can be minimized, and power consumption can be reduced. Brief Description of Drawings

 FIG. 1 is a block diagram illustrating a ferroelectric memory device according to a first embodiment of the present invention. FIG. 2 is a timing chart showing a rewrite operation according to the first embodiment.

 FIG. 3 is a block diagram showing a ferroelectric memory device according to a second embodiment of the present invention. FIG. 4 is a timing chart showing a rewrite operation according to the second embodiment.

 FIG. 5 is a block diagram illustrating a ferroelectric memory device according to a third embodiment of the present invention. FIG. 6 is a block diagram showing a fourth embodiment of the ferroelectric memory device according to the present invention. BEST MODE FOR CARRYING OUT THE INVENTION

 Hereinafter, embodiments of the present invention will be described with reference to the drawings. Double circles in the figure indicate terminals. In the figure, the signal lines indicated by bold lines are composed of a plurality of lines. Some of the blocks to which the thick lines are connected are composed of a plurality of circuits. Use the same symbols as the terminal names for signals supplied via external terminals. Also, the same symbols as the signal names are used for the signal lines through which the signals are transmitted.

 FIG. 1 shows a first embodiment of the present invention.

The ferroelectric storage device of this embodiment is formed as a system LSI mounted on an IC card, for example, by using a CMOS process on a silicon substrate. Cis The system LSI has a controller CPU (CPU core) and a ferroelectric memory core FeRAM.

 The controller CPU receives the external power supply voltage VDD, operates in synchronization with the clock signal CLK, and outputs a command signal CMD and an address signal AD for accessing the ferroelectric memory core FeRAM. The controller CPU has a power cutoff control circuit 2. The power cutoff control circuit 2 outputs a power cutoff signal P0FF when the supply of the power supply voltage VDD to the ferroelectric memory core FeRAM is stopped. Specifically, the controller CPU causes the power cutoff control circuit 2 to output a power cutoff signal P0FF when the data processing in the IC card is completed. The power-off signal P0FF is transmitted to the ferroelectric memory core FeRAM via an external terminal. The controller CPU has a control circuit (not shown) for controlling the operation of the entire IC card.

 The ferroelectric memory core FeEAM has a booster circuit 10, an operation control circuit 12, a command input circuit 14, an address counter 16, an address input circuit 18, a data input / output circuit 20, and a memory core 22. are doing. The memory core 22 has a word driver WD, a plate driver PD, a sense amplifier SA, a column switch CSW, and a memory array ARY. The operation control circuit 12 continuously writes data read from the ferroelectric capacitors FC1 and FC2 of the plurality of memory cells MC to the original ferroelectric capacitors FC1 and FC2 using the boosted voltage VDDF, and rewrites the data. It also operates as a rewrite control circuit that performs the operation.

 When receiving the power cutoff signal P0FF (positive pulse), the booster circuit 10 uses the power supply voltage VDD to generate the boosted voltage VDDF for a predetermined period.

 The operation control circuit 12 receives the operation control signal 0PR from the command input circuit 14, and outputs a timing signal TIM for controlling the operation of the memory core 20 and the like. The operation control circuit 12 continuously outputs the internal address generation signal AGEN (positive pulse) when receiving the power supply cutoff signal P0FF from the controller CPU, and further executes a rewrite operation described later. TIM is output repeatedly in synchronization with the internal address generation signal AGE.

The command input circuit 14 receives the command signal CMD via the command terminal CMD, and decodes the received command signal CMD. Command input circuit 14 The result is output to the operation control circuit 12 as the operation control signal OPR.

 The address counter 16 counts up in synchronization with the internal address generation signal AGEN, and generates an internal address signal IRAD. Address counter 16 is reset when the power is turned on.

 The address input circuit 18 receives the address signal AD via the address terminal AD during a normal operation accessed by the controller CPU, decodes the upper bit and the lower bit of the received address signal AD, respectively, and performs row decoding. Output as signal RDEC and column decode signal CDEC. The address input circuit 18 decodes the internal address signal IRAD and outputs it as a row decode signal RDEC at the time of a rewrite operation described later.

 The data input / output circuit 20 operates during normal operation accessed by the controller CPU. In a write operation, the data input / output circuit 20 outputs write data from the controller CPU to the memory core 22 via the data bus line DB in accordance with the timing signal TIM from the operation control circuit 12. The data input / output circuit 20 outputs read data from the memory core 22 to the controller CPU via the data terminal I / O in a read operation.

 The word driver WD has a word driver circuit (triangle in the figure) corresponding to each word line ViL. During a write operation, a read operation, or a rewrite operation described later, one of the word driver circuits is selected according to the row decode signal RDEC.

 It has plate driver circuits (triangles in the figure) corresponding to the plate driver PD and the plate line PL, respectively. During a write operation, a read operation, or a rewrite operation to be described later, one of the plate driver circuits is selected according to the row decode signal RDEC.

 The sense amplifier SA is formed for each pair of bit lines BL and XBL, and amplifies a voltage difference between the bit lines BL and XBL.

The column switch CSW operates during normal operation accessed by the controller CPU. The column switch CSW is formed for each pair of bit lines BL and XBL, and one of them is selected according to the column decode signal CDEC. For more details, read In a read operation or a write operation, the number of column switches CSW corresponding to the number of bits of the data input / output terminal I / O (for example, 8 bits) is simultaneously turned on, and the read data is transmitted to the data bus line DB. , Write data is transmitted to bit lines BL and XBL.

 The memory array ARY includes a plurality of memory cells MC arranged in a matrix, a plurality of read lines ffL, a plurality of plate lines PL, and a plurality of bit lines BL and XBL connected to the memory cells MC. . The memory cell MC is a 2T2C type memory cell, and has a pair of ferroelectric capacitors FC1, FC2 and a pair of transfer transistors TR1, TR2. One end of the ferroelectric capacitors FC1 and FC2 is connected to the bit lines BL and XBL via the transfer transistors TR1 and TR2, respectively, and the other end is connected to the plate line PL. The gates of the transfer transistors TR1 and TR2 are connected to a common word line. '

 FIG. 2 shows a rewrite operation of the first embodiment.

 When the controller CPU detects that the data processing in the IC card is completed and the power is turned off during normal operation, it causes the power cutoff control circuit 2 to output the power cutoff signal P0FF (high-level pulse) ( Figure 2 (a)). The booster circuit 10 of the ferroelectric memory core FeRAM starts the boosting operation to generate the boosted voltage VDDF in synchronization with the rising edge of the power cutoff signal P0FF (FIG. 2 (b)).

 After the boosted voltage VDDF reaches a predetermined voltage, the operation control circuit 12 repeatedly outputs the internal address generation signal AGEN at a predetermined cycle (FIG. 2 (c)). The address counter 16 counts in response to the internal address generation signal AGEN, and sequentially generates the internal row address signal IRAD (FIG. 2 (d)). The number of generations of the internal address generation signal AGEN and the internal row address signal IRAD is set to be equal to the number of the lead lines WL.

The mode driver TO sequentially selects one of the word lines WL in accordance with the input decode signal RDEC output from the address input circuit 18 (FIG. 2 (e)). The word line WL is not selected successively, but different word lines WL are sequentially selected according to the internal row address signal IRAD. Row decode signal RDEC (F>) as in the case of the word line, the waveform of the plate line PL in the figure is different depending on the internal row address signal IRAD. This indicates that the items are sequentially selected.

 By selecting the plate line PL, complementary data is read from the memory cell MC to the bit lines BL and XBL. The data on the bit lines BL and XBL is amplified by the sense amplifier SA and rewritten to the original memory cell MC. Reading and rewriting of data from the memory cell MC are performed for all the word lines WL. That is, during the rewrite operation period, rewrite is performed on all the memory cells MC. After the rewrite operation, the booster circuit 10 stops the boost operation in response to, for example, a control signal from the operation control circuit 12, and the boost voltage VDDF falls (FIG. 2 (g)). After that, the supply of the power supply voltage VDD to the system LSI stops. That is, the power is shut off.

 The rewrite operation period is a period from when the boost voltage VDDF reaches a predetermined voltage to when the boost circuit 10 stops the boost operation. During this period, as described above, the data of the ferroelectric capacitors FC1 and FC2 of the memory cells MC connected to all the read lines are sequentially rewritten by the boosted voltage VDDF. That is, when the power is turned off, the data held in all the memory cells MC in the memory array ARY is strongly written to the original memory cell MC, and the remanent polarization values of the ferroelectric capacitors FC1 and FC2 are large. Become. For this reason, the ferroelectric capacitors FC1 and FC2 can reliably retain data while the power is turned off. After the power is turned on again, data can be reliably read from the ferroelectric capacitors FC1 and FC2.

 Since it is not necessary to increase the residual polarization value of the ferroelectric capacitors FC1 and FC2 for each rewriting operation, the operation period of the booster circuit 10 is minimized. Here, the rewriting operation is a rewriting after a writing operation and a broken read. As a result, the power consumption of the system LSI can be reduced. In particular, power consumption during operation can be reduced.

As described above, in the present embodiment, the operation control circuit 12 continuously outputs the pulse of the internal address generation signal AGEN a plurality of times, so that the rewrite operation can be performed within a predetermined period. Therefore, the operation period of the booster circuit 10 can be minimized. As a result, the increase in power consumption of the system LSI is minimized, and the reading of the ferroelectric memory core FeRAM Margin can be improved.

 By outputting the pulse of the internal address generation signal AGEN as many times as the number of the code lines, the data held in all the memory cells MC in the memory array ARY can be continuously rewritten. Therefore, the read margin of all memory cells MC can be improved.

 Executing the rewrite operation when the power is turned off ensures that data is retained while the power is turned off. Also, data can be read reliably after the power is turned on again.

 A power cutoff control circuit 2 is formed in the controller CPU mounted on the system LSI together with the ferroelectric memory core FeRAM. Therefore, the power cutoff signal P0FF, which is the start signal of the rewrite operation, can be easily generated by using the controller CPU that controls the access of the ferroelectric memory core FeRAM.

 By performing the boosting operation of the booster circuit 10 only during the rewrite operation, the operation period of the booster circuit 10 can be minimized, and the power consumption can be reduced.

 FIG. 3 shows a second embodiment of the ferroelectric memory device of the present invention. The same reference numerals are given to the circuits described in the first embodiment that are the same as those of the circuit “signal”, and detailed description thereof will be omitted.

 In this embodiment, the controller CPU has a power-on control circuit 4 instead of the power-off control circuit 2 of the first embodiment. Other configurations are almost the same as those of the first embodiment. That is, a ferroelectric memory device is formed on a silicon substrate by using a CMOS process, for example, as a system LSI mounted on an IC card.

 The power-on control circuit 4 outputs a power-on signal P0N when power is supplied to the ferroelectric memory core FeRAM. Specifically, when the IC card is inserted into a card reader or the like and the power supply voltage TOD is supplied to the IC card, the controller CPU detects the power-on by a power-on reset circuit (not shown), and the power-on control circuit 4 Output the power-on signal P0N.

When receiving the power-on signal P0N (positive pulse), the booster circuit 10 uses the power supply voltage VDD to generate the boosted voltage VDDF for a predetermined period. Ferroelectric memory core FeRAM After that, a rewrite operation is performed in the same manner as in the first embodiment. Thus, in this embodiment, the rewrite operation is performed during the power-on reset sequence.

 FIG. 4 shows a rewrite operation of the second embodiment. Detailed description of the same operation as in FIG. 2 is omitted.

 When the controller CPU detects that the IC card is powered on, it causes the power-on control circuit 4 to output a power-on signal P0N (high-level pulse) (FIG. 4 (a)). The boost circuit 10 of the ferroelectric memory core FeRAM starts the boost operation in order to generate the boost voltage VDDF in synchronization with the rising edge of the power-on signal P0N (@ 4 (b)).

 Next, the ferroelectric memory core FeRAM performs a rewrite operation as in the first embodiment (FIG. 4 (c)). By the rewrite operation, the data held in all the memory cells MC in the memory array ARY is strongly written to the original memory cell MC, and the remanent polarization values of the ferroelectric capacitors FC1 and FC2 increase. . The operations up to this point are performed during the power-on reset sequence (during initialization).

 After the execution of the rewrite operation, the operation control circuit 12 causes the booster circuit 10 to stop the boosting operation (FIG. 4 (d)). Thereafter, a normal operation in which a read operation and a write operation are performed by the controller CPU is performed.

 By performing the rewrite operation during the power-on reset sequence immediately after the power is turned on, data can be reliably read from the ferroelectric capacitors FC1 and FC2 in the subsequent normal operation.

 In this embodiment, the same effects as in the first embodiment can be obtained. Further, in this embodiment, by performing the rewrite operation when the power is turned on, the data can be reliably read after the power is turned on.

 A power-on control circuit 4 is formed in the controller CPU mounted on the system LSI together with the ferroelectric memory core FeRAM. Therefore, the power-on signal P0N, which is the start signal of the rewrite operation, can be easily generated by using the controller CPU that controls the access of the ferroelectric memory core FeRAM.

FIG. 5 shows a third embodiment of the ferroelectric memory device of the present invention. First and Circuits and signals that are the same as the circuits and signals described in the second embodiment are denoted by the same reference numerals, and detailed descriptions thereof are omitted.

 In this embodiment, the controller CPU has a power cutoff control circuit 2 of the first embodiment and a power on control circuit 4 of the second embodiment. Other configurations are almost the same as those of the first embodiment. That is, a ferroelectric memory device is formed on a silicon substrate by using a CMOS process, for example, as a system LSI mounted on an IC card.

 The controller CPU uses the OR logic of the power-off signal P0FF generated when the power is turned off and the power-on signal P0N generated when the power is turned on as the rewrite signal REW as the ferroelectric memory core FeRAM Output to

 When receiving the rewrite signal REW (positive pulse), the booster circuit 10 generates the boosted voltage VDDF for a predetermined period using the power supply voltage VDD. Thereafter, the ferroelectric memory core FeRAM executes a rewrite operation similarly to the first and second embodiments.

 In this embodiment, the same effects as those of the first and second embodiments can be obtained. Furthermore, in this embodiment, by performing the rewrite operation both when the power is turned off and when the power is turned on, data can be reliably read after the power is turned on again even when the power supply is turned off for a long time. .

 FIG. 6 shows a fourth embodiment of the ferroelectric memory device of the present invention. Circuits described in the first and second embodiments. Circuits that are the same as the signals are denoted by the same reference numerals, and detailed descriptions thereof are omitted.

 In this embodiment, the controller CPU has a rewrite request circuit 6 instead of the power cutoff control circuit 2 of the first embodiment. Other configurations are almost the same as those of the first embodiment. That is, a ferroelectric memory device is formed on a silicon substrate by using a CMOS process, for example, as a system LSI mounted on an IC card.

When the controller CPU determines that rewriting of the ferroelectric memory core FeRAM is necessary, it causes the rewriting request circuit 6 to output a rewriting request signal WREQ. When the booster circuit 10 receives the rewrite request signal WREQ (positive pulse), Using the voltage VDD, the boost voltage VDDF is generated for a predetermined period. Thereafter, the ferroelectric memory core FeRAM executes a rewrite operation as in the first embodiment.

 In this embodiment, the same effects as in the first embodiment can be obtained. Further, in this embodiment, the controller CPU can output a rewrite request signal WREQ as needed. Therefore, during the power-on period, the rewrite operation can be performed at an arbitrary timing. As a result, even when the power-on period is long, it is possible to prevent the read margin from being lowered by executing the rewrite operation halfway, and to read the data reliably.

 In the above-described embodiment, the example in which the booster circuit 10 is formed in the ferroelectric memory core FeRAM has been described. The present invention is not limited to such an embodiment. For example, a booster circuit may be formed outside the ferroelectric memory core FeRAM.

 In the embodiment described above, the example in which the controller CPU and the ferroelectric memory core FeRAM are formed on the same chip has been described. The present invention is not limited to such an embodiment. For example, the controller CPU and the ferroelectric memory core FeRAM may be formed on separate chips.

 In the above-described embodiment, an example has been described in which the present invention is applied to a system LSI on which a ferroelectric memory core FeRAM composed of 2T2C memory cells is mounted. The present invention is not limited to such an embodiment. For example, the present invention may be applied to a system LSI equipped with a ferroelectric memory core FeRAM composed of 1T1C type memory cells.

 As described above, the present invention has been described in detail. However, the above-described embodiment and its modifications are merely examples of the present invention, and the present invention is not limited thereto. Obviously, modifications can be made without departing from the present invention.

 Industrial potential

 In the ferroelectric memory device according to the present invention, the operation period of the booster circuit can be minimized. As a result, it is possible to improve the read margin by minimizing an increase in power consumption of the ferroelectric memory device. The rewriting operation can improve the read margin of all memory cells.

According to the ferroelectric memory device of the present invention, data can be reliably retained while the power is turned off. Data can be read reliably after the source is turned on again.

 In the ferroelectric memory device of the present invention, the rewrite operation can be executed by a simple circuit by using the controller for controlling the access to the memory array.

 In the ferroelectric memory device according to the present invention, data can be reliably read by performing a rewrite operation after turning on the power.

 In the ferroelectric memory device of the present invention, a rewrite operation can be executed at an arbitrary timing by using a controller for controlling access to the memory array. In the ferroelectric memory device according to the present invention, the boosting operation of the booster circuit is performed only during the rewrite operation, so that the operation period of the booster circuit can be minimized and power consumption can be reduced.

Claims

The scope of the claims  (1) a memory array composed of a plurality of memory cells each including a ferroelectric capacitor for holding data,  A booster circuit that generates a boosted voltage higher than the power supply voltage; '' A rewrite control circuit for performing a rewrite operation of continuously writing data read from the plurality of ferroelectric capacitors to the original ferroelectric capacitor using the boosted voltage. Ferroelectric memory device.  (2) In the ferroelectric memory device according to claim 1,  The ferroelectric memory device, wherein the rewrite control circuit continuously rewrites data held in all the memory cells in the memory array.  (3) In the ferroelectric memory device according to claim 1,  The ferroelectric memory device, wherein the rewrite control circuit executes the rewrite operation when power to the memory array is cut off.  (4) The ferroelectric memory device according to claim 3,  A controller that accesses the memory array and that outputs a power shutoff signal when shutting off power supply to the memory array;  The booster circuit starts a boosting operation in response to the power cutoff signal,  The ferroelectric memory device, wherein the rewrite control circuit starts the rewrite operation in response to the power-off signal.  (5) The ferroelectric memory device according to claim 1,  The ferroelectric memory device, wherein the rewrite control circuit executes the rewrite operation when power is supplied to the memory array.  (6) In the ferroelectric storage device according to claim 5,  A controller that accesses the memory array and outputs a power-on signal when starting to supply power to the memory array;  The booster circuit starts a boosting operation in response to the power-on signal, The ferroelectric memory device, wherein the rewrite control circuit starts the rewrite operation in response to the power-on signal. (7) In the ferroelectric memory device according to claim 1,  A controller that accesses the memory array and outputs a rewrite request signal for executing the rewrite operation;  The ferroelectric memory device, wherein the rewrite control circuit starts the rewrite in response to the rewrite request signal from the controller.  (8) In the ferroelectric storage device according to claim 1,  The booster circuit performs a boost operation only during the rewrite operation.