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WO2005057662A3 - Method and apparatus for fabricating ultra-shallow junction metal-oxide semiconductor integrated circuit devices. - Google Patents

Method and apparatus for fabricating ultra-shallow junction metal-oxide semiconductor integrated circuit devices. Download PDF

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Publication number
WO2005057662A3
WO2005057662A3 PCT/IB2004/003991 IB2004003991W WO2005057662A3 WO 2005057662 A3 WO2005057662 A3 WO 2005057662A3 IB 2004003991 W IB2004003991 W IB 2004003991W WO 2005057662 A3 WO2005057662 A3 WO 2005057662A3
Authority
WO
WIPO (PCT)
Prior art keywords
source
integrated circuit
oxide semiconductor
semiconductor integrated
drain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/IB2004/003991
Other languages
French (fr)
Other versions
WO2005057662A2 (en
Inventor
Frederic Salvetti
Etienne Robilliart
Alexandre Dray
Francois Wacquant
Damien Lenoble
Ramiro Palla
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Publication of WO2005057662A2 publication Critical patent/WO2005057662A2/en
Publication of WO2005057662A3 publication Critical patent/WO2005057662A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/015—Manufacture or treatment removing at least parts of gate spacers, e.g. disposable spacers

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A method and apparatus for fabricating a metal oxide semiconductor integrated circuit device, the method comprising sequentially: (a) providing a gate (106) on a substrate (100); (b) providing a spacer (108) on a sidewall of said gate (106); (c) forming a source/drain region (110) in said substrate (100); (d) substantially completely removing said spacer (108); (e) forming a source/drain extension region (114) in said substrate (100); (f) forming a source drain pocket region (116) in said substrate (100), beneath said gate (106); and (g) performing an annealing process to substantially simultaneously electrically activate said source/drain region (110), said source/drain extension region (114) and said source/drain pocket region (116).
PCT/IB2004/003991 2003-12-10 2004-12-03 Method and apparatus for fabricating ultra-shallow junction metal-oxide semiconductor integrated circuit devices. Ceased WO2005057662A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP03300257 2003-12-10
EP03300257.7 2003-12-10

Publications (2)

Publication Number Publication Date
WO2005057662A2 WO2005057662A2 (en) 2005-06-23
WO2005057662A3 true WO2005057662A3 (en) 2005-10-13

Family

ID=34673636

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2004/003991 Ceased WO2005057662A2 (en) 2003-12-10 2004-12-03 Method and apparatus for fabricating ultra-shallow junction metal-oxide semiconductor integrated circuit devices.

Country Status (2)

Country Link
TW (1) TW200534339A (en)
WO (1) WO2005057662A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107104051B (en) * 2016-02-22 2021-06-29 联华电子股份有限公司 Semiconductor device and method of making the same

Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6180472B1 (en) * 1998-07-28 2001-01-30 Matsushita Electrons Corporation Method for fabricating semiconductor device
US6211027B1 (en) * 1999-11-19 2001-04-03 United Microelectronics Corp. Method for manufacturing PMOS transistor
US20010025994A1 (en) * 2000-03-23 2001-10-04 Kazuhiko Yoshino Process for producing semiconductor device and semiconductor device
US6319798B1 (en) * 1999-09-23 2001-11-20 Advanced Micro Devices, Inc. Method for reducing lateral dopant gradient in source/drain extension of MOSFET
US6335252B1 (en) * 1999-12-06 2002-01-01 Mitsubishi Denki Kabushiki Kaisha Semiconductor device manufacturing method
US20020001910A1 (en) * 1999-02-24 2002-01-03 Chin-Lai Chen Method of forming a mos transistor of a semiconductor
US6429084B1 (en) * 2001-06-20 2002-08-06 International Business Machines Corporation MOS transistors with raised sources and drains
US20030098486A1 (en) * 2001-11-26 2003-05-29 Fujitsu Limited Semiconductor device manufacture method including process of implanting impurity into gate electrode independently from source /drain and semiconductor device manufactured by the method
US20030170958A1 (en) * 2002-03-05 2003-09-11 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing semiconductor device
US6630385B1 (en) * 2001-04-27 2003-10-07 Advanced Micro Devices, Inc. MOSFET with differential halo implant and annealing strategy
US20030193066A1 (en) * 2002-04-16 2003-10-16 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
US6642122B1 (en) * 2002-09-26 2003-11-04 Advanced Micro Devices, Inc. Dual laser anneal for graded halo profile
US6660605B1 (en) * 2002-11-12 2003-12-09 Texas Instruments Incorporated Method to fabricate optimal HDD with dual diffusion process to optimize transistor drive current junction capacitance, tunneling current and channel dopant loss

Patent Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6180472B1 (en) * 1998-07-28 2001-01-30 Matsushita Electrons Corporation Method for fabricating semiconductor device
US20020001910A1 (en) * 1999-02-24 2002-01-03 Chin-Lai Chen Method of forming a mos transistor of a semiconductor
US6319798B1 (en) * 1999-09-23 2001-11-20 Advanced Micro Devices, Inc. Method for reducing lateral dopant gradient in source/drain extension of MOSFET
US6211027B1 (en) * 1999-11-19 2001-04-03 United Microelectronics Corp. Method for manufacturing PMOS transistor
US6335252B1 (en) * 1999-12-06 2002-01-01 Mitsubishi Denki Kabushiki Kaisha Semiconductor device manufacturing method
US20010025994A1 (en) * 2000-03-23 2001-10-04 Kazuhiko Yoshino Process for producing semiconductor device and semiconductor device
US6630385B1 (en) * 2001-04-27 2003-10-07 Advanced Micro Devices, Inc. MOSFET with differential halo implant and annealing strategy
US6429084B1 (en) * 2001-06-20 2002-08-06 International Business Machines Corporation MOS transistors with raised sources and drains
US20030098486A1 (en) * 2001-11-26 2003-05-29 Fujitsu Limited Semiconductor device manufacture method including process of implanting impurity into gate electrode independently from source /drain and semiconductor device manufactured by the method
US20030170958A1 (en) * 2002-03-05 2003-09-11 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing semiconductor device
US20030193066A1 (en) * 2002-04-16 2003-10-16 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
US6642122B1 (en) * 2002-09-26 2003-11-04 Advanced Micro Devices, Inc. Dual laser anneal for graded halo profile
US6660605B1 (en) * 2002-11-12 2003-12-09 Texas Instruments Incorporated Method to fabricate optimal HDD with dual diffusion process to optimize transistor drive current junction capacitance, tunneling current and channel dopant loss

Also Published As

Publication number Publication date
TW200534339A (en) 2005-10-16
WO2005057662A2 (en) 2005-06-23

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