WO2004030089A1

WO2004030089A1 - Method of forming a copper interconnect with concentrated alloy atoms at copper-passivation interface

Info

Publication number: WO2004030089A1
Application number: PCT/US2003/029510
Authority: WO
Inventors: Larry Zhao; Paul R. Besser; Connie Wang
Original assignee: Advanced Micro Devices Inc
Current assignee: Advanced Micro Devices Inc
Priority date: 2002-09-26
Filing date: 2003-09-18
Publication date: 2004-04-08
Anticipated expiration: 2005-03-26
Also published as: TW200405513A; AU2003272573A1

Abstract

A method of forming a copper interconnect (62) provides a copper seed layer (54) in a recess (52) of a dielectric layer (50), this copper seed layer (54) having alloy atoms (56) that tend to improve electromigration performance of copper. After formation of the copper seed layer (54), copper (58) is formed on the copper seed layer (54), followed by chemical mechanical polishing of the copper (58). The polished copper (58) is then annealed, which drives the alloy atoms (56) to the top surface (60) of the copper (58) to improve the electromigration performance at the copper-passivation interface, while keeping low the concentration of the alloy atoms (56) within the interior of the copper line (62) to prevent increasing the resistance in the copper line (62).

Description

METHOD OF FORMING A COPPER INTERCONNECT WITH CONCENTRATED ALLOY ATOMS AT COPPER-PASSIVATION INTERFACE

BACKGROUND OF THE INVENTION

[01] The escalating requirements for high density and performance associated with ultra large scale integration (ULSI) semiconductor device wiring are difficult to satisfy in terms of providing submicron- sized, low resistance-capacitance (RC) metallization patterns. This is particularly applicable when the submicron features, such as vias, contact areas, lines, trenches, and other shaped openings or recesses have high aspect ratios (depth-to-width) due to miniaturization. Conventional semiconductor devices typically comprise a semiconductor substrate, usually a doped monocrystalline silicon (Si), and plurality of sequentially formed interlayer dielectrics and electrically conductive patterns. An integrated circuit is formed therefrom containing a plurality of patterns of conductive lines separated by inter- wiring spacings. Typically, the conductive patterns of vertically spaced metallization layers are electrically connected by vertically oriented conductive plugs filling via holes formed in the interlayer dielectric layer separating the metallization layers, while other conductive plugs filling contact holes establish electrical contact with active device regions, such as a source/drain region of a transistor, formed in or on a semiconductor substrate. Conductive lines formed in trench-like openings typically extend substantially parallel to the semiconductor substrate. Semiconductor devices of such type according to current technology may comprise five or more levels of metallization to satisfy device geometry and micro-miniaturization requirements. [02] A commonly employed method for forming conductive plugs for electrically interconnecting vertically spaced metallization layers is known as "damascene" -type processing. Generally, this processing involves forming an opening (or via) in the dielectric interlayer, which will subsequently separate the vertically spaced metallization layers. The via is typically formed using conventional lithographic and etching techniques. After the via is formed, the via is filled with conductive material, such as tungsten or copper, using conventional techniques. Excess conductive material on the surface of the dielectric interlayer is then typically removed by chemical mechanical planarization (CMP). [03] High performance microprocessor applications require rapid speed of semiconductor circuitry, and the integrated circuit speed varies inversely with resistance and capacitance of the interconnection pattern. As integrated circuits become more complex and feature sizes and spacings become smaller, the integrated circuit speed becomes less dependent upon the transistor itself and more dependent upon the interconnection pattern. If the interconnection node is routed over a considerable distance, e.g., hundreds of microns or more, as in submicron technologies, the interconnection capacitance limits the circuit node capacitance loading and, hence, the circuit speed. As integration density increases and feature size decreases, in accordance with submicron design rules, the rejection rate due to integrated circuit speed delays significantly reduces manufacturing throughput and increases manufacturing costs. [04] One way to increase the circuit speed is to reduce the resistance of a conductive pattern. Aluminum is conventionally employed because it is relatively inexpensive, exhibits low resistivity, and is relatively easy to etch. However, as the size for openings for vias/contacts and trenches is scaled down to the submicron ranges, step coverage problems result from the use of aluminum. Poor step coverage causes high current density and enhanced electromigration. Moreover, low dielectric constant polyamide material, when employed as dielectric interlayers, create moisture/bias reliability problems when in contact with aluminum, and these problems have decreased the reliability of interconnections formed between various metallization layers. [05] Copper (Cu) and Cu-based alloys are particularly attractive for use in VLSI and ULSI ^{" "}semiconductor devices, which require multi-level metallization layers. Copper and copper-based alloy metallization systems have very low resistivities, which are significantly lower than tungsten and even lower than those of previously preferred systems utilizing aluminum and its alloys. Additionally, copper has a higher resistance to electromigration. Furthermore, copper and its alloys enjoy a considerable cost advantage over a number of other conductive materials, notably silver and gold. Also, in contrast to aluminum and refractory-type metals, copper and its alloys can be readily deposited at low temperatures formed by well-known (wet) plating techniques, such as electroless and electroplating techniques, at deposition rates fully compatible with requirements of manufacturing throughput. [06] Figure 1 depicts a schematic cross-section of a portion of a metal interconnect structure employing copper damascene technology. The lower level metal layer 10 (including a copper line), also referred to as Ml, is connected to a higher level metal layer 16 (including a copper line) through a via 14. Barrier layers 18 and 20, formed of nitride, for example, cover the metal layers 10, 16. The metal layers 10, 16 are separated by a dielectric layer 12, such as formed by an oxide, for example. The via 14 is filled with metal to form a conductive plug 15. [07] The formation of the via 14 involves performing a via etch through the dielectric layer 12 and the barrier layer 20, stopping on the underlying metal layer 10. A pre-sputter etch process, using argon, for example, is normally employed prior to the via barrier and copper deposition. [08] A higher current/current density usually results in better device performance. On the other hand, a higher current density also requires better electromigration (EM) performance to ensure long device lifetime. Electromigration performance usually can be improved through process/integration optimization. Also, copper alloys have been found to be an effective way to improve electromigration performance. The copper alloys slow the copper diffusion during electromigration and therefore improve the lifetime of the device. In reality, most alloys operate to increase the copper resistance. This prevents copper alloys from being used in actual products. [09] Electromigration (EM) has been defined as the transport of metal atoms by momentum exchange between electrons, moving under the influence of a field, and metal ions. Two of the critical interfaces for electromigration in the copper damascene structure of Figure 1 are the interface V1M1 at 22 and V1M2 at 24. Electromigration testing of the V1M1 interface 22 involves flowing electrons from the upper copper line in metal layer 16 (M2) through the conductive plug 15 and the via 14 and into the lower copper line in metal layer 10 (Ml). Electromigration testing of the V1M2 interface 24 involves electrons flowing in the opposite direction. In the case of the V1M1 interface 22, electromigration voids typically generate at the copper/nitride or (copper/barrier) interface at the via 14. This is depicted in Figure 2, where the electromigration void 26 is shown. The presence of an electromigration void 26 reduces the reliability of the device.

[10] When aluminum is used as the interconnect material, it is well known that many alloy elements may be employed to improve the aluminum resistance to electromigration. One of the most widely used alloy elements is copper in aluminum. When copper is added in small concentrations to aluminum, the electromigration reliability increases by orders of magnitude. Similarly, alloy elements for copper have been under study. However, there are process differences between aluminum and copper that render the insertion of an alloy in the copper process flow a challenging proposition. For example, aluminum is a deposition, pattern and etch process, while copper is typically a damascene process with a physical vapor deposition (PVD) seed and electrochemical fill process. [11] Attempts have been made to introduce the alloy into the copper lines during electrochemical deposition, but many alloys of copper are not electrically active in aqueous solution. Another potential solution is to sputter the copper alloys during the PVD copper seed deposition. As will be described below, the provision of the alloy atoms in the copper seed presents problems in the further processing. [12] Figure 3 shows a procedure for forming copper interconnects during one stage of the processing. In Figure 3, a recess 32 has been formed in a dielectric layer. The recess 32 can be a via, or a trench, for example. A copper seed layer 34 has been deposited by PVD, for example. The copper seed layer 34, when deposited, includes copper alloy atoms, such as tin (Sn). A copper fill is made through electrochemical plating (ECP), for example, the copper fill being referred to by reference numeral 36. [13] Referring to Figure 4, an annealing is typically performed, which causes most of the alloy atoms 38 to migrate to the copper surface 40 during the annealing process. Some alloy atoms 40 will segregate to the grain boundaries of the copper, and less will stay inside the grains. Figure 4 schematically depicts the increased concentration of the alloy atoms 40 at the copper surface. [14] Figure 5 depicts the structure of Figure 4 after a chemical mechanical polishing. As can be seen, the polishing process removes the top copper surface, where most of the alloy atoms 40 segregated. This produces a concentration of alloy atoms at the top of the copper surface 42, (the copper-passivation interface) that is approximately the same as deeper within the copper line 44. If the alloy concentration at the copper-passivation interface 42 were to be increased to improve electromigration performance, utilizing the method depicted in Figures 3-5 would require increasing the concentration inside the metal line. However, an increase of alloy atoms inside the metal line 44 would lead to higher resistance. Hence, the metallization procedure of Figures 3-5 does not utilize the alloy elements in an efficient manner. SUMMARY OF THE INVENTION

[15] There is a need for providing improved electromigration performance of a copper interconnect through the use of alloy atoms, but in an efficient manner that does not substantially increase the concentration of the alloy atoms inside the metal line that would lead to higher resistance. [16] These and other needs are met by embodiments of the present invention which provide a method of forming a copper interconnect comprising the steps of forming a copper seed layer on a surface, this copper seed layer comprising alloy atoms. Copper is formed on the copper seed layer, and chemical mechanical polishing is performed on the copper to form a top surface. The chemically mechanical polished copper is then annealed to drive the alloy atoms towards the top surface of the copper.

[17] By performing the annealing only after the chemical mechanical polishing has been performed, the alloy atoms that are driven to the top surface of the copper will remain there, and not be removed by a chemical mechanical polishing operation. This allows for efficient use of the alloy atoms, which are not wasted by the removal in a planarization process. Also, the invention allows for a lower concentration of the alloy atoms within the copper line itself, thereby maintaining a lower resistance of the copper line.

[18] The earlier stated needs are also met by embodiments of the present invention which provide a method for improving electromigration performance in a copper interconnect, comprising the steps of depositing a seed layer within a recess in a dielectric layer, the seed layer containing alloy atoms. Copper fill is electrochemically plated on the seed layer to fill the recess with copper. The copper in the dielectric layer is planarized to form a planarized copper interconnect surface. After the planarizing, annealing is performed to concentrate the alloy atoms towards the planarized copper interconnect surface. [19] The earlier stated needs are also met by embodiments of the present invention which provide a copper arrangement comprising a dielectric layer having a top surface, and a recess in the dielectric layer. A copper interconnect is provided within the recess with an interconnect top surface that is co- planar with the dielectric layer top surface. Copper electromigration reducing alloy atoms are within the copper interconnect, the concentration of alloy atoms being greater nearest the interconnect top surface than the remainder of the copper interconnect. [20] The foregoing and other features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[21] Figure 1 is a cross-section of a metal interconnect structure constructed in accordance with prior art methodologies. [22] Figure 2 depicts the structure of Figure 1, with an electromigration void in a structure formed by metal interconnect processing methodologies of the prior art.

[23] Figure 3 depicts the formation of a metal interconnect after one step in a prior art methodology. [24] Figure 4 shows the structure of Figure 3 following annealing of the structure. [25] Figure 5 shows the structure of Figure 4 following a chemical mechanical polishing operation. [26] Figure 6 shows a cross-section of a copper interconnect structure after a step in a copper interconnect formation process in accordance with embodiments of the present invention. [27] Figure 7 shows the structure of Figure 6 after copper fill has been provided by an electrochemical process, in accordance with embodiments of the present invention. [28] Figure 8 shows the structure of Figure 7 following a planarization process in accordance with embodiments of the present invention.

[29] Figure 9 depicts the structure of Figure 8 after an annealing step has been performed in accordance with embodiments of the present invention.

DETAILED DESCRIPTION OF THE INVENTION [30] The present invention addresses problems related to electromigration and potentially increased resistance in copper interconnects. The invention solves these problems, in part, by providing alloy atoms in a copper seed layer, and forming the copper fill on the copper seed layer. However, instead of annealing and then performing planarization by polishing, the invention performs planarization after the copper fill process, and only then performs the annealing step to drive alloy atoms towards the copper surface. This prevents a wasting of the alloy atoms that would otherwise be removed in the chemical mechanical polishing process after annealing, and also avoids increasing the resistance in the copper line that would accompany increasing the concentration of alloy atoms in the seed layer. [31] Figure 6 shows the copper interconnect formation process during one step of the process in accordance with the embodiments of the present invention. A cross-section of a portion of the wafer is depicted in schematic fashion. The dimensions are only representative, and are not meant to accurately depict the scale or the relative dimensions of the copper interconnect.

[32] The copper interconnect formation includes dielectric layer 50, made of a dielectric material, such as a low k dielectric material or other type of dielectric material. Within this dielectric layer 50 is a recess 52 that is typically formed by etching, for example. The recess 52 may be a via hole, or a trench, for example. When filled, a via hole will form an interconnection via, while a trench will form a line.

[33] A copper seed layer 54 is deposited on the dielectric layer 50 and in the recess 52. The copper seed layer 54 may be deposited by physical vapor deposition (PVD), for example, or other conventional deposition processes. The thickness of the copper seed layer 54 may be between about 400 A and about 1500 A, for example, but will depend upon the deposition technique and the desired thickness. [34] Figure 6 does not show a separate barrier layer in addition to the copper seed layer 54. However, a separate barrier layer may be provided between the copper seed layer 54 and the dielectric layer 50, or the barrier layer may be formed as part of the copper seed layer 54. Separate barrier layers or integrated barrier/seed layers are known to those of ordinary skill in the art. [35] The copper seed layer 54 is deposited with alloy atoms 56 that may be considered to be copper electromigration reducing alloy atoms. Candidate elements include Sn, Pd, C, Ca, Mg, Al, and Hf. Of these candidate elements, Sn is currently considered to be the preferred alloying element. However, other alloying elements may be employed without departing from the scope of the present invention. The following description of the invention will assume that Sn is used as the alloying atoms 56. [36] In the exemplary embodiments of the invention, the" concentration of the ^"alloy atoms 56 is between about 0.1 and about 0.8 atomic percent of the copper seed layer 54. Such a concentration provides for a desirable concentration of the alloy elements at the top surface of the copper interconnect, but without increasing the resistance of the copper line excessively. However, other concentrations of the alloy atoms 56 may be used without departing from the scope of the present invention.

[37] Referring to Figure 7, a copper fill process is then performed to provide copper or copper based alloy within the recess 52. The copper fill process may be a conventional process, such as electrochemical plating (ECP) or chemical vapor deposition, as examples. The copper 58 fills the recess 52 and covers the top of dielectric layer 50. In the prior art processes, an annealing is then performed that drives the alloy atoms 56 towards the top surface of the copper 58. These alloy atoms 56 would then have been removed by a copper mechanical polishing, as described earlier with respect to prior art Figures 4 and 5.

[38] The present invention presents this wasting of the alloy atoms 56 by avoiding annealing at this stage. Instead, the copper 58 is planarized. Referring now to Figure 8, a planarization process is performed, such as by chemical mechanical polishing. Other planarization techniques may be employed without departing from the scope of the invention. The planarization is performed until the structure of Figure 8 is achieved. This removes the excess copper 58 and the copper seed layer 54 that is on the top surface of the dielectric layer 50. Hence, the top surface 60 of the copper 58 is co-planar with the top surface of the dielectric layer 50. The copper 58 forms a copper line 62, or via, but will be referred to as the copper line 62 in the following description.

[39] The alloy atoms 56 remain in place in the copper seed layer 54 since the planarization process is not generally a thermal process sufficient to drive the alloy atoms 56 out of the copper seed layer 54. Hence, the polishing (or planarization) does not remove any of the alloy atoms from the copper line or via 58. [40] Following the planarization of the copper 58 and the dielectric layer 50, an anneal step is performed, which causes the alloy atoms 56 to migrate to the top surface 60 of the copper line 62. This is schematically represented in Figure 9. Hence, the concentration near or at the top surface 60 of the copper line 62 of the alloy atoms 56 is greater than the concentration of the alloy atoms 56 throughout the remainder of the copper line 62. The electromigration at the copper-passivation interface (i.e., at the top surface 60 of the copper line 62) is sufficient to substantially improve the electromigration performance of the copper interconnect. At the same time, however, since the alloy atoms 56 were not wasted by annealing followed by planarization, a lower overall concentration of the alloy atoms 56 throughout the remainder of the copper lines 62 is provided. This avoided undesirably increasing the electrical resistance of the copper line 62 by adding excessive amounts of the alloy atoms 56 in the copper seed layer 54, in an attempt to increase the concentration of the alloy atoms 56 at the top surface 60. [41] The annealing may be a rapid thermal annealing, for example, with temperatures between about 100°C and about 350°C, and for a period ranging from between about 10 seconds to about 200 seconds. Increasing the annealing temperature above typical anneals also serves to drive more alloy atoms 56 to the copper-passivation interface 60 and leave less alloy atoms 56 inside the interior of the metal line 62. This makes even more effective use of the alloy atoms 56 in improving electromigration performance. Hence, in certain preferred embodiments of the invention, the anneal temperature is greater than about 200°C.

[42] As an alternative embodiment, the anneal can also be performed in a furnace, at between about 150°C to about 350°C, for between about 15-90 minutes, with a reducing ambient of N₂Hτ and Ar or N. [43] In certain preferred embodiments, annealing is performed after an SiN_x barrier layer and oxide are provided on the top of the copper line 62. Alternatively, the annealing can be performed after all of the metal layers are fabricated, i.e., at the end of the back end of line processes.

[44] The method of the present invention provides for a copper interconnect that has improved electromigration performance, but without a substantially increased electrical resistance. This is achieved in an efficient and elegant manner in the embodiments of the present invention. [45] Although the present invention has been described and illustrated in detail, it is to be clearly understood that the same is by way of illustration and example only and is not to be take by way of limitation, the scope of the present invention being limited only by the terms of the appended claims.

Claims

WHAT IS CLAIMED IS:

1. A method of forming a copper interconnect, comprising the steps of: forming a copper seed layer (54) on a surface (52), the copper seed layer (54) comprising alloy atoms (56); forming copper (58) on the copper seed layer (54): chemical mechanical polishing the copper (58) to form a top surface (60); and annealing the chemically mechanical polished copper (58) to drive the alloy atoms (56) towards the top surface (60) of the copper (58).

2. The method of claim 1, wherein the alloy atoms (56) are copper electromigration reducing atoms (56).

3. The method of claim 2, wherein the copper electromigration reducing atoms (56) are Sn atoms (56).

4. The method of claim 2, wherein the step of annealing includes subjecting the chemically mechanical polished copper (58) to a temperature of between about 100°C and about 350°C.

5. The method of claim 4, wherein the annealing is performed for between about 10 to about 200 seconds.

6. The method of claim 2, wherein the step of annealing includes subjecting the chemically mechanical polished copper (58) to a temperature above about 200°C.

7. The method of claim 1, wherein the surface on which the copper seed layer (54) is formed is a recess (52).

8. The method of claim 7, wherein the recess (52) is a via (52).

9. The method of claim 7, wherein the recess (52) is a trench (52).

10. A copper interconnect arrangement comprising: a dielectric layer (50) having a top surface (60); a recess (52) in the dielectric layer (50); a copper interconnect (62) formed within the recess (52) with an interconnect top surface (60) that is co-planar with the dielectric layer (50) top surface; copper electromigration reducing alloy atoms (56) within the copper interconnect (62), with a concentration of alloy atoms (56) being greater nearest the interconnect top surface (60) than the remainder of the copper interconnect (62).