WO2004023559A1 - Semiconductor storage device and its manufacturing method - Google Patents

Abstract

A tunnel insulating film (3) is formed in an element region demarcated by an element isolation insulating film (2). For each memory cell, a floating gate (4), an ONO film (5), and a control gate (6) are formed, and then a plasma insulating film (7) is formed on the surface of a stacked gate. The plasma insulating film is immune to the direction of crystal plane of the base film. Therefore, the thickness of the plasma insulating film (7) is substantially uniform as a whole. As a result, hydrogen is prevented from entering when an insulating film is formed even though the maximum thickness needs not to be as great as that of the thermal oxide film. Further, electrons are prevented from emerging. By decreasing the thickness of the insulating film, the size of the bird’s beak can be decreased, and the efficiency of erase/write of data can be enhanced.

Description

 Description: Semiconductor storage device and manufacturing method thereof

 The present invention relates to a semiconductor memory device suitable for a flash memory and a method for manufacturing the same. Background art

A flash memory is a non-volatile semiconductor storage device that stores data by retaining charges in a floating film or a storage film such as a nitride film below a gate electrode. When accumulating charges in the floating gate, charges are transferred between the channel and the floating gate via the gate insulating film. Also, when charges are stored in the nitride film in the ONO film as a storage film, the charges are stored in the insulating film itself. Therefore, the electrical characteristics of these insulating films need to be stable. If the characteristics of these insulating films are unstable, even if the same control voltage is applied, one memory cell will store “1” data, while other memory cells will store “1” data. There is a possibility that a state where data of “0” is stored in the cell may occur, and the reliability is extremely low. In addition to these insulating films, stable characteristics are required for the insulating film formed around the floating gate or the gate electrode. This insulating film is formed for the following purpose. After the floating gate or gate electrode is formed, a side wall insulating film for forming an LDD structure is formed on the side of these, and an interlayer insulating film covering the floating gate or gate electrode is formed. A film is formed. At this time, if the floating gate or the gate electrode is in direct contact with the side wall insulating film or the interlayer insulating film, electrons may escape from the floating gate or the gate electrode to the side wall insulating film or the like. . As a result, the electrical characteristics of the floating gate or the gate electrode fluctuate. Also, the side In a process for forming the wall insulating film and the interlayer insulating film, a gas containing hydrogen may be used. At this time, if the hydrogen reaches the gate insulating film or the storage film, the deterioration of the hydrogen occurs, and the characteristics of the gate insulating film or the storage film fluctuate. In order to prevent such fluctuations, an insulating film is formed around the gate electrode. In order to achieve such a purpose, the insulating film is formed by thermal oxidation at about 900 ° C. so that the thickest part has a thickness of 12 nm or more. You. The reason why the thickness of this insulating film is set to 12 nm or more at the thickest portion is that when an oxide film is formed by thermal oxidation, the underlying film, for example, the silicon constituting the gate electrode is formed. The growth rate of the oxide film differs depending on the plane orientation of the film. Therefore, the thickness of this thermal oxide film is not uniform, and this thickness is necessary to sufficiently prevent hydrogen from entering even the thinnest part. FIG. 13 is a cross-sectional view illustrating a method of manufacturing a conventional floating gate type memory. In this conventional manufacturing method, a stack gate comprising a tunnel oxide film 52, a floating gate 53, an inter-gate insulating film 54, and a control gate 55 is provided on a semiconductor head plate 51. After the formation of the heat treatment, thermal oxidation is performed. As a result, as shown in FIG. 13, a thermal oxide film 56 having large unevenness and an uneven thickness is formed. FIG. 14 is a cross-sectional view illustrating a method for manufacturing a conventional SONOS type memory. In this conventional manufacturing method, a bit line diffusion layer 62 is formed on the surface of a semiconductor substrate 61, and a tunnel oxide film 63, a nitride film 64, and a top film 65 are formed thereon. A storage insulating film 66 is formed. Further, a gate electrode 67 is formed on the storage insulating film 66, and thereafter, thermal oxidation is performed. As a result, as shown in FIG. 14, a large unevenness exists, and a thermal oxide film 68 having an uneven thickness is formed. However, in a semiconductor memory device formed by the method described above, The parse beak is large and the coupling is reduced. Such a decrease in coupling leads to a problem of a decrease in erasure efficiency. In particular, in a memory in which erasing is performed near the end of the gate electrode and in a memory in which erasing is performed in the entire channel, the erasure efficiency is remarkably reduced. In addition, due to the occurrence of a parse beak, the thickness of the insulating film at that portion becomes thicker, so that not only the erase efficiency but also the data write efficiency is reduced. Further, there is another problem that it is difficult to stabilize the characteristics of the finally manufactured semiconductor memory device. One of the reasons is that when performing thermal oxidation, multiple wafers are processed simultaneously, but it is extremely difficult to keep the temperature inside the heating furnace constant at this time. And the like. Another factor is that impurities such as phosphorus introduced into the floating gate and the like as a result of thermal oxidation are segregated and screened at the peripheral edge thereof. The present invention has been made in view of the above problems, and provides a semiconductor memory device capable of improving the efficiency of data erasing and writing and stabilizing characteristics and a method of manufacturing the same. aimed to. Disclosure of the invention

As a result of intensive studies, the present inventor has found that in a conventional method of manufacturing a semiconductor memory device, an oxide film covering a stack gate and the like is formed by thermal oxidation. Was found to have occurred. The inventor of the present application seeks to solve the above-mentioned problems by searching for plasma treatment as a method for forming a good and dense insulating film without performing thermal oxidation. The inventors have found that the following can be achieved, and have reached various aspects of the invention described below. A first method for manufacturing a semiconductor memory device according to the present invention provides a method of manufacturing a semiconductor device including a tunnel insulating film, a floating gate, an inter-gate insulating film, and a control gate sequentially stacked on a semiconductor substrate. After forming the stack gate, on the surface of the stack gate, A coating insulating film is formed by a plasma oxidation method, a plasma nitriding method, or a series of steps including any of these methods, and further, an interlayer insulating film that embeds the stack gate covered with the coating insulating film is formed. It is characterized by forming. A first semiconductor memory device according to the present invention manufactured by such a method includes a semiconductor substrate, a tunnel insulating film, a floating gate, and a gate, which are sequentially stacked on the semiconductor substrate. A stack gate including an inter-gate insulating film and a control gate, a covering insulating film covering the above-described stack gate, and embedding the stack gate covered by the covering insulating film. And an interlayer insulating film. The semiconductor memory device is characterized in that the covering insulating film is made of one kind of insulating film selected from the group consisting of a plasma oxide film, a plasma nitride film, and a plasma oxynitride film. Further, in the second method for manufacturing a semiconductor memory device according to the present invention, a storage insulating film including a nitride film having a charge trapping function is formed on a semiconductor substrate, and the storage insulating film is formed on the semiconductor substrate. After the gate electrode is formed through the insulating film, the insulating film is formed on the surface of the storage insulating film and the gate electrode by a plasma oxidation method, a plasma nitriding method, or a series of steps including any of these methods. And forming the storage insulating film covered with the coating insulating film and an interlayer insulating film burying the gate electrode. A second semiconductor memory device according to the present invention manufactured by such a method includes a semiconductor substrate and a storage insulating device including a nitride film formed on the semiconductor substrate and having a charge trapping function. A film, a gate electrode formed on the semiconductor substrate via the storage insulating film, a coating insulating film covering the storage insulating film and the gate electrode, And an interlayer insulating film burying the storage insulating film and the gate electrode. The semiconductor memory device is characterized in that the covering insulating film is made of one kind of insulating film selected from the group consisting of a plasma oxide film, a plasma nitride film, and a plasma oxynitride film. · BRIEF DESCRIPTION OF THE FIGURES

 1A and 1B are cross-sectional views illustrating a method for manufacturing a semiconductor memory device according to the first embodiment of the present invention.

 FIGS. 2A and 2B are views showing the method for manufacturing the semiconductor memory device according to the first embodiment of the present invention, and are cross-sectional views showing steps subsequent to the steps shown in FIGS. 1A and 1B 1. It is. FIGS. 3A and 3B are views showing the method for manufacturing the semiconductor memory device according to the first embodiment of the present invention, and are cross-sectional views showing steps subsequent to the steps shown in FIGS. 2A and 2B. is there. FIGS. 4A and 4B are views showing the method for manufacturing the semiconductor memory device according to the first embodiment of the present invention, and are cross-sectional views showing steps subsequent to the steps shown in FIGS. 3A and 3B. is there. 5A and 5B are views showing the method for manufacturing the semiconductor memory device according to the first embodiment of the present invention, and are cross-sectional views showing the steps subsequent to the steps shown in FIGS. 4A and 4B. is there. 6A and 6B are views showing the method for manufacturing the semiconductor memory device according to the first embodiment of the present invention, and are cross-sectional views showing the next step of the steps shown in FIGS. 5A and 5B. is there. FIG. 7 is a cross-sectional view illustrating a state of the plasma insulating film 7 according to the first embodiment of the present invention.

 8A and 8B are cross-sectional views illustrating a method for manufacturing a semiconductor memory device according to the second embodiment of the present invention.

 FIGS. 9A and 9B are views showing the method for manufacturing the semiconductor memory device according to the second embodiment of the present invention, and are cross-sectional views showing the steps subsequent to the steps shown in FIGS. 8A and 8B. is there. FIGS. 10A and 10B are views showing the method for manufacturing the semiconductor memory device according to the second embodiment of the present invention, and are cross-sectional views showing the steps subsequent to the steps shown in FIGS. 9A and 9B. FIG. FIG. 11 is a cross-sectional view showing the state of the plasma insulating film according to the second embodiment of the present invention.

 FIG. 12 is a schematic diagram showing a schematic configuration of a plasma processing apparatus including a radial line lot antenna that can be used in the embodiment of the present invention.

 FIG. 13 is a cross-sectional view illustrating a method of manufacturing a conventional floating gate type memory.

FIG. 14 is a cross-sectional view illustrating a method for manufacturing a conventional SONOS type memory. Best shape bear for carrying out the invention

 Hereinafter, a semiconductor memory device and a method of manufacturing the same according to an embodiment of the present invention will be specifically described with reference to the accompanying drawings. For the sake of convenience, the structure of the semiconductor memory device will be described together with its formation method.

(First Embodiment)

First, a first embodiment of the present invention will be described. In the first embodiment, the present invention is applied to a semiconductor memory device having a stack gate structure. 1A, 1B to 6A, and 6B are cross-sectional views illustrating a method of manufacturing the semiconductor memory device according to the first embodiment of the present invention in the order of steps. In the semiconductor memory device according to the first embodiment, a plurality of lead lines and bit lines are formed in a lattice shape so as to be orthogonal to each other. In addition, one memory cell is formed “′” in the vicinity of each grid point. FIGS. 1B to 6A correspond to the cross sections orthogonal to the bit lines, and FIGS. 1B to 6B 1A and 1B show cross sections orthogonal to each other, and other cross sections are shown in FIGS. In the present embodiment, when manufacturing a semiconductor memory device having the layout configuration as described above, first, as shown in FIGS. An element isolation insulating film 2 is formed, for example, by the LOCOS method on the surface of a semiconductor substrate 1 such as a substrate, etc. Next, in order to prevent punch-through below the element isolation insulating film 2, boron or the like is used. The impurity is ion-implanted over the entire surface to form a diffusion layer 1a. In order to adjust the threshold voltage of the diffusion layer, a diffusion layer 1b is formed by ion-implanting an impurity such as boron into an element region partitioned by the element isolation insulating film 2. In forming word lines, bit lines, and LOCOS, the smaller the minimum line width, the more the effect of the present invention can be exhibited. If it is effective, it is particularly remarkable if it is 0.25 μm or less. Because, when the line width is narrow, the width of the parse beak cannot be ignored. This is the same in the second embodiment. Next, a tunnel insulating film 3 made of, for example, a silicon oxide film is formed in the element region partitioned by the element isolation insulating film 2. Thereafter, a floating gate 4 is formed for each memory cell, and an ONO film (inter-gate insulating film) 5 and a control gate (word line) 6 are formed. When forming the floating gate 4, for example, after forming a polysilicon film, an impurity such as boron is introduced into the polysilicon film by, for example, ion implantation. The ONO film 5 is composed of a silicon nitride film, a silicon oxide film, and a silicon nitride film that are sequentially stacked. A stack gate is composed of a stack of the tunnel insulating film 3, the floating gate 4, the ONO film 5, and the control gate 6. At this time, the higher the impurity concentration in the floating gate, the more the effect of the present invention is exhibited. Specifically, it is effective if it is 1 XI 0 ¹⁸ / cm ³ or more, and it is particularly remarkable if it is about 1 X ^{10 19} Z cm ³ . This is because the high-temperature heat treatment causes segregation of impurities and lowers the quality of the insulating film around the floating gate. Because it does not happen. This segregation is particularly remarkable when the impurity is phosphorus. Further, in forming the ONO film 5, the effect of the present invention is exerted as the thickness becomes smaller. Specifically, it is effective if the total physical film thickness is 40 nm or less,

This is particularly remarkable when it is 20 nm or less. This is because if the ONO film is thin, the bird's beak cannot be ignored compared to the thickness of the ONO film itself. More specifically, the bottom oxide film of the ONO film is remarkable at 10 nm or less, particularly 7 nm or less, and the nitride film is 20 nm or less, particularly 10 nm or less. The top oxide film

It is remarkable below 10 nm, especially below 7 nm. This is the second embodiment The same is true for Next, as shown in FIGS. 2A and 2B, the top and side surfaces of the control gate 6 and the side surfaces of the NO film 5, the floating gate 4, and the tunnel insulating film 3 are immediately stacked. A plasma insulating film (coating insulating film) 7 is formed on the surface of the gate. At this time, the plasma insulating film 7 is also formed on the surface of the semiconductor substrate 1. As the plasma insulating film 7, a plasma oxide film, a plasma nitride film, or a plasma oxynitride film can be formed. The formation of the plasma insulating film 7 is preferably performed in a temperature range of 65 ° C. or lower, for example, may be performed at about 450 ° C. The thickness of the plasma insulating film 7 is preferably 9 nm or less, for example, about 8 nm. Subsequently, ion implantation is performed using the stack gate as a mask, and a heat treatment is further performed to form a self-aligned low-concentration diffusion layer 9 as shown in FIGS. 3A and 3B. Is formed. At this time, the low-concentration diffusion layer is diffused below the gate by heat treatment, but the distance from the edge of the gate must at least exceed the parse beak. In the present invention, by suppressing the bird's beak, it is possible to reduce the sneaking of the low concentration diffusion layer under the gate. Since the miniaturization of the device is limited by the punch-through current from the diffusion layer, the present invention greatly contributes to the miniaturization of the device. Next, as shown in FIGS. 4A and 4B, a side wall insulating film 10 is formed on the side surface of the stack gate. The side wall insulating film 10 is formed, for example, by forming an HTO film (high-temperature oxide film) and then performing isotropic etching on the HTO film. By this isotropic etching, a portion of the plasma insulating film 7 formed on the surface of the semiconductor substrate 1 that is not finally covered with the side wall insulating film 10 is removed, and the surface of the semiconductor substrate 1 is removed. Part of is exposed. Then, as shown in Fig. 5A and Fig. 5B, the stack gate and side wall Using the insulating film 10 as a mask, ion implantation is performed at a higher concentration than when the low concentration diffusion layer 9 is formed, and heat treatment is further performed to form the high concentration diffusion layer 11. I do. Next, as shown in FIGS. 6A and 6B, an interlayer insulating film 12 is formed on the entire surface. The inter-layer insulating film 12 is formed, for example, by depositing a silicon oxide film by a CVD method. Subsequently, a contact hole and a wiring are formed to complete the semiconductor memory device. In such a first embodiment, as shown in FIGS. 2A and 2B, the insulating film covering the starter gate is the plasma insulating film 7. Unlike the thermal oxide film, the plasma insulating film is not affected by the plane orientation of the underlying film. Accordingly, as shown in FIG. 7, since the thickness of the plasma insulating film 7 is substantially uniform throughout, the thickness of the side wall insulating film 10 or 10 can be increased even if the maximum thickness is not as large as that of the thermal oxide film. In addition to preventing the intrusion of hydrogen when forming the interlayer insulating film 12, the escape of electrons can be prevented. By reducing the thickness of the insulating film, the parse beak can be reduced, and the efficiency in erasing and writing data can be improved. In a floating gate type semiconductor memory device, charges are transferred between the floating gate and the semiconductor substrate in writing and erasing data, and the data is transferred depending on whether or not the charges are captured by the floating gate. Information is read out. Accordingly, as described above, by reducing the size of the parse beak, it becomes easier to transfer charges, thereby improving the efficiency of erasing and the like. In forming the plasma insulating film 7, a plurality of wafers are not processed in one heating furnace. Therefore, it is not affected by the non-uniformity of the furnace temperature. Further, the plasma insulating film 7 is formed at an extremely low temperature as compared with the thermal oxide film. You can. Therefore, segregation of impurities in the floating gate 4, such as phosphorus, is extremely unlikely to occur. Therefore, it is possible to obtain a semiconductor storage device having stable characteristics between a plurality of devices.

(Second embodiment)

Next, a second embodiment of the present invention will be described. In the second embodiment, the present invention is applied to a semiconductor memory device having a so-called SONOS structure. 8A, 8B to 1OA, and 1OB are cross-sectional views illustrating a method of manufacturing a semiconductor memory device according to the second embodiment of the present invention in the order of steps. The SONOS structure is a structure of a nitride film charge storage memory having a source Z drain also serving as a buried bit line and having a channel parallel to a word line (gate electrode). It has a train structure. Also in the second embodiment, a plurality of word lines and bit lines are formed in a lattice shape so as to be orthogonal to each other. One memory cell is formed near each grid point. As in the first embodiment, FIGS. 8A to 10A correspond to the cross section orthogonal to the bit line, and FIGS. 8B to 10B correspond to the cross section orthogonal to the word line. Equivalent to. Therefore, FIGS. 8A and 8B show cross sections orthogonal to each other. The same applies to the other FIGS. 9A, 9B, 10A, and 10B. In the present embodiment, when manufacturing the semiconductor memory device having the layout configuration as described above, first, as shown in FIGS. 8A and 8B, a semiconductor substrate 2 such as a silicon substrate is used. A bit line diffusion layer (bit line) 22 is formed on the surface of 1 by ion implantation using a resist film as a mask. Next, a silicon oxide film, a silicon nitride film, a silicon oxide film, and a polysilicon film are sequentially stacked, and these are patterned to form a sequentially stacked tunnel insulating film 23 and a silicon oxide film. A laminated body composed of the control nitride film 24, the top film 25, and the control gate (gate line (gate electrode)) 26 is formed. Control gate 26 In the formation, for example, after forming a polysilicon film, an impurity such as boron is introduced into the polysilicon film by, for example, ion implantation. Tunnel insulating film 23 is made of a silicon oxide film, and top film 25 is made of a silicon oxide film. A storage insulating film 29 is composed of the tunnel insulating film 23, the silicon nitride film 24, and the top film 25. The control gate 26 is made of a polysilicon film. Then, as shown in FIGS. 9A and 9B, the top and side surfaces of the control gate 26 and the side surfaces of the tunnel insulating film 23, the storage film 24, and the top film 25 are formed. Next, a plasma insulating film (coating insulating film) 27 is formed. At this time, the plasma insulating film 27 is also formed on the surface of the semiconductor substrate 21. As the plasma insulating film 27, a plasma oxide film, a plasma nitride film, or a plasma oxynitride film can be formed as in the case of the plasma insulating film 7 in the first embodiment. The formation of the plasma insulating film 27 is preferably performed in a temperature range of 65 ° C. or lower, for example, may be performed at about 450 ° C. The thickness of the plasma insulating film 27 is preferably 9 nm or less, for example, about 8 nm. The heat treatment at this time causes impurities in the buried bit line to diffuse toward the center of the channel. However, in the present invention, the low-temperature treatment reduces the diffusion of impurities in the buried bit line. Can be. Since the miniaturization of the device is limited by the punch-through current from the diffusion layer, the present invention greatly contributes to the miniaturization of the device. Subsequently, as shown in FIGS. 10A and 10B, an interlayer insulating film 28 is formed on the entire surface. The interlayer insulating film 28 is formed, for example, by depositing a silicon oxide film by a CVD method. Then, a contact hole and wiring are formed to complete the semiconductor memory device. - Also in the second embodiment, as shown in FIGS. 9A and 9B, the insulating film covering the side surface of the storage film 24 is the plasma insulating film 27. Therefore, as shown in FIG. 11, since the thickness of the plasma insulating film 27 is substantially uniform throughout, as in the first embodiment, the maximum thickness of the plasma insulating film 27 becomes larger as the thermal oxide film becomes thicker. Even if it is not necessary, it is possible to prevent intrusion of hydrogen and escape of electrons when forming the interlayer insulating film 28. As a result, it is possible to improve the efficiency in erasing and writing data by suppressing the parse beak to a small value.

In a SONOS type semiconductor memory device, when writing and erasing data, charge is transferred between a storage film made of a silicon nitride film and a semiconductor substrate, and the storage film is Information is read depending on whether or not electric charges are captured at the interface with the tunnel insulating film thereunder and in the vicinity thereof. Therefore, as described above, by making the noise beak smaller, it becomes easier to transfer charges, so that the efficiency of erasing and the like is improved. ^¾ As in the first embodiment, it is a child avoid destabilization characteristics caused by non-uniformity and segregation of re down the deposition temperature. In the second embodiment, the side wall insulating film is not formed on the side of the control gate 26, but a side wall insulating film may be formed. Such a side wall insulating film may be formed simultaneously with, for example, a side wall insulating film of a transistor included in a peripheral circuit. In forming the plasma oxide film, for example, radical 0 *, radical N *, or radical NH * is generated in a plasma atmosphere of a gas containing 〇 ₂ , N _2, or NH ₃ . This and can, plasma raw material gas to be used during the growth of the insulating film, for example, contain a rare gas such as K r or A r rather it may also may contain a H _2. Also, a method for forming a plasma oxynitride film and a plasma nitride film and a method for forming the same are used. Although the plasma processing apparatus is not particularly limited, a plasma oxynitride film or a plasma nitride film may be formed by using the following apparatus. Specifically, a plasma oxynitride film or a plasma nitride film is formed by using a plasma processing apparatus having a radial line slot antenna as shown in FIG. The plasma processing apparatus 100 has a gate valve 102 connected to a cluster tool 101 and a workpiece W (semiconductor substrate 1 in this embodiment) mounted thereon, and the plasma processing apparatus 100 has a A processing chamber 105 capable of accommodating a susceptor 104 provided with a cooling jacket 103 for cooling W, a high vacuum pump 106 connected to the processing chamber 105, and a micro wave source 110, an antenna member 120, a high-frequency power supply 107 for bias and a box box 108 that constitutes ion plating together with the antenna member 120, and a gas supply ring 13 A gas supply system 130, 140 having 1, 14 1, and a temperature control unit 150 controlling the temperature of the object W to be processed are provided. The micro-wave source 110 is composed of, for example, a magnetron, and can generate a micro-wave (for example, 5 kW) of usually 2.45 GHz. Thereafter, the transmission form of the microwave is converted by the mode converter 112 into a TM, TE or TEM mode. 'The antenna member 120 has a temperature control plate 122, a storage member 123, and a (dielectric plate 230). 'The temperature control plate 122 is connected to the temperature controller 122, and the storage member 123 is a slot electrode (not shown) that contacts the slow wave member 124 and the slow wave member 124. ) Store and review. This slot electrode is called a radial line slot antenna (RLSA) or an ultra-high efficiency planar antenna. However, in the present embodiment, other types of antennas, for example, a single-layer structured waveguide planar antenna, a parallel plate slot plate of a dielectric substrate, and the like may be applied. When a film is formed using a plasma processing apparatus equipped with such a radial line slot antenna, it is preferable that the ion irradiation energy of the plasma be 7 eV or less. It is more preferable that the potential energy of the plasma be 10 eV or less. The plasma insulating film can be formed by using the above-described plasma processing apparatus by a plasma oxidation method, a plasma nitridation method, or a series of steps including at least one of these methods. In the above-described embodiment, the present invention is applied to a floating gate type or a SONOS type, but the form to which the present invention can be applied is not limited to these. For example, the present invention can be applied to an MNOS type semiconductor memory device. When the present invention is applied to an MNOS type semiconductor memory device, a silicon oxide film and a silicon nitride film are sequentially stacked on a semiconductor substrate to form a storage insulating film, and then a storage insulating film is formed thereon. A gate electrode is formed. Subsequently, a plasma insulating film is formed on the surfaces of the storage insulating film and the gate electrode. Industrial applicability

 According to the present invention, since the covering insulating film covering the floating gate or the gate electrode is formed by plasma processing, a high-temperature heat treatment is not required, and a purse beak is suppressed, and writing and writing are prevented. Erasing efficiency is high and stable characteristics can be obtained.

Claims

The scope of the claims 1. Semiconductor tombboard and  A stack gate including a tunnel insulating film, a floating gate, an inter-gate insulating film, and a control gate sequentially laminated on the semiconductor substrate;  A coating insulating film covering the stack gate;  An interlayer insulating film burying the stack gate covered with the covering insulating film.  A semiconductor memory device, wherein the covering insulating film is made of one kind of insulating film selected from the group consisting of a plasma oxide film, a plasma nitride film, and a plasma oxynitride film. 2. The semiconductor memory device according to claim 1, wherein a phosphorus is introduced into the floating gate.  3. The semiconductor memory device according to claim 1, wherein the thickness of the covering insulating film is 9 nm or less. 4. The semiconductor memory device according to claim 1, wherein an impurity concentration in the floating gate is 1 XI 0 ¹⁸ cm ³ or more.  5. The semiconductor memory device according to claim 1, wherein the thickness of the inter-gate insulating film is 40 II m or less.  6. The semiconductor memory device according to claim 1, further comprising a sidewall insulating film formed on a side of the covering insulating film.  7. The semiconductor substrate,  A storage insulating film formed on the semiconductor substrate and including a nitride film having a charge trapping function;  A gate electrode formed on the semiconductor substrate via the storage insulating film, a coating insulating film covering the storage insulating film and the gate electrode,  An interlayer insulating film that embeds the storage insulating film and the gate electrode covered by the coating insulating film;  Semiconductor memory device having The coating insulating film may be a plasma oxide film, a plasma nitride film, or a plasma oxynitride film. A semiconductor memory device comprising one kind of insulating film selected from the group consisting of: 8. The semiconductor memory device according to claim 7, wherein phosphorus is introduced into the gate electrode. 9. The storage insulating film includes:  The nitride film;  A first oxide film formed between the nitride film and the semiconductor substrate;  8. The semiconductor memory device according to claim 7, comprising:  10. The semiconductor memory device according to claim 9, wherein said storage insulating film further includes a second oxide film formed between said nitride film and said gate electrode. 11. The semiconductor memory device according to claim 7, further comprising a side wall insulating film formed on a side of the covering insulating film.  1 2. forming a stack gate including a tunnel insulating film, a floating gate, an inter-gate insulating film, and a control gate sequentially stacked on a semiconductor substrate;  Forming a coating insulating film on the surface of the stack gate by a plasma oxidation method, a plasma nitridation method, or a series of steps including any of these steps;  Forming an interlayer insulating film for burying the stack gate covered with the covering insulating film;  A method for manufacturing a semiconductor memory device, comprising:  13. The method for manufacturing a semiconductor memory device according to claim 12, further comprising a step of introducing phosphorus into the floating gate before the step of forming the coating insulating film.  13. The method according to claim 12, wherein the thickness of the coating insulating film is 9 nm or less. 13. The method according to claim 12, wherein the impurity concentration in the floating gate is l × ^{10 18} / cm ³ or more.  16. The method for manufacturing a semiconductor memory device according to claim 12, wherein the thickness of the inter-gate insulating film is 40 nm or less. 1 7. A step of forming a side wall insulating film on the side of the insulating film. 13. The method for manufacturing a semiconductor memory device according to claim 12, wherein: 18. The step of forming the covering insulating film is performed in a plasma atmosphere of a source gas containing at least one kind of molecule selected from the group consisting of O ₂ , N _2, and NH _3. 13. The method for manufacturing a semiconductor memory device according to claim 12, wherein:  19. The method for manufacturing a semiconductor memory device according to claim 12, wherein the step of forming the coating insulating film is performed within a temperature range of not higher than 65 ° C.  20. forming a storage insulating film including a nitride film having a charge trapping function on a semiconductor substrate;  Forming a gate electrode on the semiconductor substrate via the storage insulating film;  Forming a coating insulating film on the surfaces of the storage insulating film and the gate electrode by a plasma oxidation method, a plasma nitriding method, or a series of steps including any of these methods;  Forming the storage insulating film covered with the covering insulating film and an interlayer insulating film burying the gate electrode;  A method for manufacturing a semiconductor memory device, comprising:  21. The method for manufacturing a semiconductor memory device according to claim 20, further comprising a step of introducing phosphorus into the gate electrode before the step of forming the coating insulating film. 22. The step of forming the storage insulating film includes:  Forming a first oxide film on the semiconductor substrate;  Forming the nitride film on the first oxide film;  21. The method for manufacturing a semiconductor memory device according to claim 20, comprising: 23. The semiconductor memory device according to claim 22, wherein the step of forming the storage insulating film further includes a step of forming a second oxide film on the nitride film. Method.  24. The method for manufacturing a semiconductor memory device according to claim 20, further comprising a step of forming a sidewall insulating film on a side of the insulating film. 2 5. The step of forming the insulating cover film is carried out at 0 _2, N ₂ and the raw material gas in the atmosphere of a plasma containing one molecule from the group consisting of NH ₃ and less have been selected 21. The method for manufacturing a semiconductor memory device according to claim 20, wherein: 26. The step of forming the covering insulating film includes a step of generating at least one kind of radical selected from the group consisting of at least radical 0 *, radical N *, and radical NH * in the atmosphere. 26. The method for manufacturing a semiconductor memory device according to claim 25, comprising:  27. The method for manufacturing a semiconductor memory device according to claim 25, wherein the source gas further contains a rare gas. 28. The method _{c according} to claim 27, wherein the rare gas contains at least one kind of molecule selected from the group consisting of Kr and Ar. 2 9. The raw material gas further method of manufacturing a semiconductor memory device according to claim 2 5, characterized that you containing H _2.  30. The method of manufacturing a semiconductor memory device according to claim 25, wherein in the step of forming the coating insulating film, the plasma ion irradiation energy is set to 7 eV or less.  31. The method for manufacturing a semiconductor memory device according to claim 25, wherein, in the step of forming the coating insulating film, the potential energy of the plasma is set to 10 eV or less.  32. In the step of forming the coating insulating film, the source gas is excited by using a microwave radiated from a planar antenna having a plurality of slits formed therein. 26. The method according to claim 25, wherein plasma is generated.  33. The method for manufacturing a semiconductor memory device according to claim 32, wherein a radial line slot antenna is used as the planar antenna.  34. The method for manufacturing a semiconductor memory device according to claim 20, wherein the step of forming the coating insulating film is performed within a temperature range of not higher than 65O <0> C.