WO2004008524A1 - Wafer cassette - Google Patents
Wafer cassette Download PDFInfo
- Publication number
- WO2004008524A1 WO2004008524A1 PCT/JP2003/007556 JP0307556W WO2004008524A1 WO 2004008524 A1 WO2004008524 A1 WO 2004008524A1 JP 0307556 W JP0307556 W JP 0307556W WO 2004008524 A1 WO2004008524 A1 WO 2004008524A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- plate
- semiconductor wafer
- wafer
- semiconductor
- rod
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/673—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere using specially adapted carriers or holders; Fixing the workpieces on such carriers or holders
- H01L21/6732—Vertical carrier comprising wall type elements whereby the substrates are horizontally supported, e.g. comprising sidewalls
Definitions
- the present invention relates to a wafer cassette for accommodating a semiconductor wafer in various processing apparatuses used for processing a semiconductor wafer.
- a semiconductor wafer on which a plurality of integrated circuits such as IC and LSI are formed is formed into a predetermined thickness by grinding the back surface, and then divided into individual semiconductor chips by dicing.
- a wafer cassette 50 as shown in FIG. 8 is usually used.
- the semiconductor wafer W is housed in the wafer cassette 50 by the carrying-in / out means 52 provided with the suction portion 51 at the tip, and the semiconductor wafer W is provided on both sides of the wafer cassette 50. Both ends are supported by the groove 53 provided on the side.
- the semiconductor ⁇ : c-ha W becomes thinner and the rigidity is reduced, so that bending occurs even if the protective tape T is adhered to the surface as shown in Fig. 9.
- the semiconductor wafer W cannot be accommodated because it cannot be supported by the groove 53 of the wafer cassette 50.
- a pre-dicing technology in which a groove having a depth corresponding to the thickness of a chip is formed in advance on the surface of a semiconductor wafer, and then the back surface is ground to expose the groove and divide the chip into individual chips.
- the semiconductor device can be housed in the wafer cassette 50 in the same manner as described above. There is a problem that can not be.
- the semiconductor wafer may fall off from the opening during transportation.
- the semiconductor member may come into contact with the stove member and break. Therefore, in actuality, it is necessary to carry the sheet with the opening facing upward without providing a stopper member at the opening.
- the semiconductors after grinding may need to be aligned in the accommodating position and orientation (crystal orientation) for the next process.
- the semiconductor in the ah cassette ⁇ — If the position of 8 is shifted or rotated, the problem that the next process will be hindered will occur.
- the present invention provides a semiconductor chip, which maintains the outer shape of a semiconductor X-ha semiconductor a wafer that has lost its rigidity, in an E-hakaset.
- Enclosed semiconductors The purpose is to prevent the semiconductor devices from falling off, displacing, or rotating. Disclosure of the invention
- the present invention relates to a cassette for accommodating a semiconductor X-ha, a plate supporting the housed semiconductor aa, a top plate disposed above the plate, and a plate below the plate. It is characterized by comprising at least a bottom plate provided, and a rod penetrating the plate and extending from the top plate to the bottom plate, wherein the plate is configured to support the entire surface of the semiconductor substrate E: E-H. ⁇ Provide an ehakaset.
- a spring member for supporting the plate on the rod and maintaining a gap between vertically adjacent plates is attached to the rod, and the spring member is a coil spring, and is loosely fitted to the rod.
- a spacer that regulates the contraction of the coil spring is attached, while maintaining a constant spacing between vertically adjacent plates, and through the plate.
- the housed semiconductor ⁇ From the top plate to the bottom plate, the housed semiconductor ⁇ : A position regulating pad that regulates the position of ⁇ -8 is provided, the position regulating rod is covered with a cushioning member, and the support surface of the plate is An additional requirement is that a non-slip member is laid.
- the thinned semiconductor wafer tip is a semiconductor wafer divided by dicing. Can be safely and reliably supported and contained.
- each plate is supported by a spring member, the semiconductor wafer is carried into the wafer cassette and is supported by the plate, or the semiconductor supported by the plate is sucked from above.
- the pressing force is reduced by the spring member even if the semiconductor wafer is pressed, and the semiconductor wafer is safely and securely loaded into the wafer cassette without damaging the semiconductor wafer, and the semiconductor wafer is removed from the wafer cassette.
- Semiconductor wafers can be carried out.
- the accommodated semiconductor device 18 can be held without slipping, so that even a thin semiconductor device can be accommodated without bending, and the semiconductor device can be dropped and removed. There will be no shift in position or orientation.
- FIG. 1 is an exploded perspective view showing an example of an embodiment for implementing a wafer cassette according to the present invention
- FIG. 2 is a perspective view showing the wafer cassette
- FIG. 3 is a perspective view showing a spacer provided on the same cassette
- FIG. 4 is a cross-sectional view showing a state where the spacer and a spring member are loosely fitted to a rod.
- FIG. 5 is a front view showing a plate on which a non-slip member is laid
- FIG. 6 is a perspective view showing a grinding apparatus which is an example of an apparatus using the I-hasakette according to the present invention
- FIG. 7 is a front view showing a state in which a semiconductor wafer is housed in a wafer cassette in the grinding apparatus.
- FIG. 8 is a perspective view showing a conventional wafer cassette
- FIG. 9 is a front view showing a semiconductor wafer having no rigidity.
- the wafer cassette 10 includes a top plate 11 on which a gripping handle 11 a is formed, a bottom plate 12, and a plurality of plates 13 for supporting the entire surface of the semiconductor X- 8 to be housed. And a rod 14 penetrating through all the plates 13 to the top plate 11 and the bottom plate 1 2, the top plate 1 1 being disposed above the plate 13, and the bottom plate 1 2 being a plate 1 It is located below 3.
- the plate 13 is not limited to the illustrated shape as long as it can support the entire surface of the semiconductor wafer.
- each rod 14 passes through a rod through hole 13 a formed in the plate 13, and is connected to the bottom plate 12 by a set screw 15. It is fixed, and the male screw part 14 a formed on the upper end of the rod 14 is screwed into the female screw part 11 b formed on the top plate 11 and fixed to the top plate 11.
- the rods 14 need to have at least three rods, and may have five or more rods.
- a spring member 16 is loosely fitted to each of the four rods 14 between the vertically adjacent plates 13, and this spring member 16 is vertically adjacent to the four rods 14.
- the gap between the plate 13 and the mating plate 13 is maintained, and when a pressing force is applied to the plate 13, the plate 13 serves as a cushioning member.
- the spring members 16 are coil springs in the illustrated example, and each of the coil springs supports the plate 13. Also, between the top plate 11 and the uppermost plate 13, Ring 1 1 d is inserted into rod 14.
- five position regulating rods 17 penetrate through the position regulating rod through holes 13 b formed in each plate 13 and are formed at the upper end of the position regulating rod 17.
- the male screw portion 17a is screwed and fixed to the female screw portion 11c formed on the top plate 11, and the lower end of the position regulating rod 17 is fixed by a rod screw 18.
- At least three position regulating rods 17 need only be provided, and serve to regulate the position of the semiconductor wafer W to be housed. It is preferable that the position regulating rod 17 is coated with vinyl or the like as a cushioning member for cushioning an impact when the outer periphery of the semiconductor wafer A collides.
- the ring-shaped spacer 19 shown in FIG. 3 is housed inside the spring member 16, and as shown in FIG. Preferably, 9 is loosely fitted.
- the spacer 19 keeps a constant interval between the vertically adjacent plates 13 in a normal state, and the shrinkage restricting portion 19 a formed on the spacer 19 forms the spring member 1. Regulate the shrinkage of 6. Further, by adjusting the length of the spacer 19 and the length of the spring member 16, it is possible to cope with semiconductors of various thicknesses: n-c.
- a non-slip member 13 d is laid on the support surface 13 c of the plate 13.
- various resins for example, an elastomer resin, a silicone resin, a natural resin, and the like can be used. Also, rubber, pounds, etc. can be used.
- These resins can be laid by applying them to the support surface 13c, or they can be laid by attaching a sealing member formed in a sheet shape in advance.
- the seal member previously formed in a sheet shape may be in a mesh shape.
- the non-slip member 13 d may be laid on the entire surface of the support surface 13 c or may be laid on a part thereof.
- the cassette 10 thus constructed is, for example, a grinding machine shown in FIG.
- the semiconductor wafer after being mounted on the wafer 20 is ground.
- this grinding apparatus 20 a plurality of semiconductor wafers before grinding are housed in a single cassette 21.
- the semiconductor wafers are carried out by carrying-in / out means 22 having a holding portion 22a, and are brought out of the positioning table 2. Placed on 3.
- the semiconductor wafer is placed and held on the chuck table 25 by the first carrying means 24.
- the chuck table 25 is supported by a turntable 26 so as to be able to rotate and revolve, and the turntable 26 is rotated by a required angle (90 degrees in the illustrated example), so that the first grinding means 27 is rotated.
- the first grinding means 27 is connected to a support plate 30 slidably engaged with a pair of guide rails 29 provided in a direction perpendicular to the inner surface of the wall portion 28, It is configured to be driven by a pulse motor 31 and move up and down together with the support plate 30.
- the first grinding means 27 includes a spindle 32 having a vertical axis, a motor 33 for rotating and driving the spindle 32, a mounter 34 formed at the lower end of the spindle 32, and a mounter.
- a grinding wheel 35 fixed to 3 4 is provided, and a grinding wheel 36 for rough grinding is fixed to the lower surface of the grinding wheel 35, and the spindle 32 is driven by the motor 33 to rotate. As a result, the grinding wheel 35 rotates.
- the first grinding means 27 descends while the grinding wheel 35 rotates while the chuck table 25 rotates, and the rotating grinding wheel 36 contacts the back surface of the semiconductor ⁇ : L-ha W Then, the back surface is roughly ground.
- the roughly ground semiconductor wafer W is positioned immediately below the second grinding means 37 by rotating the turntable 26 by a required angle (90 degrees in the illustrated example).
- the second grinding means 37 is connected to a support plate 39 slidably engaged with a pair of guide rails 38 arranged vertically on the inner surface of the wall portion 28, It is configured to be driven up and down with the support plate 39 by being driven by the motor 40.
- the second grinding means 37 includes a spindle 41 having a vertical axis and a spindle A motor 4 2 for rotating and driving the spindle 4 1, a mounter 4 3 formed at the lower end of the spindle 41, and a grinding wheel 44 fixed to the mounter 43.
- the grinding wheel 45 for finish grinding is fixed, and the grinding wheel 44 rotates as the spindle 41 rotates by being driven by the motor 42.
- the second grinding means 37 descends while the chuck table 25 rotates and the grinding wheel 44 rotates, and the rotating grinding wheel 45 contacts the back surface of the semiconductor wafer W and contacts the back surface. Is finish-ground.
- the chuck table 25 moves to be positioned near the second transport means 46, and the semiconductor ⁇ : ⁇ -c W is ground by the second transport means 46. Conveyed to 7. Then, the semiconductor washed here: L-W is housed in the wafer cassette 10 by the carrying-in / out means 22.
- the semiconductor wafer W housed in the wafer cassette 10 is entirely supported by the plate 13 shown in FIGS. 1 and 2, so the semiconductor wafer W is thinned by grinding and has reduced rigidity. It can safely and reliably support a semiconductor wafer whose rigidity has been lost due to the division.
- the semiconductor wafer X When accommodating the semiconductor wafer in the wafer cassette 10, as shown in FIG. 7, the semiconductor wafer X is sucked and held on the lower surface of the holding portion 22a constituting the carrying-in / out means 22, and is held.
- the part 22a moves horizontally and enters the inside of the wafer cassette 10, and the holding part 22a descends to release the suction force.
- the semiconductor ⁇ : c—c W is placed, a pressing force is applied from the holding portion 22 a to the plate 13. In this case, the pressing force is reduced by the contraction of the spring member 16. Therefore, the semiconductor wafer W can be housed safely and securely without being damaged.
- the spacer 19 when the spacer 19 is provided, the contraction of the spring member 16 is restricted by the contraction restricting portion 19a formed in the spacer 19, so that the spring member 16 is accommodated below the spacer.
- Semiconductor ⁇ : L-ha can be damaged Absent.
- the anti-slip member 13 d is laid on the support surface 13 c of the plate 13 as shown in FIG. 5, the semiconductor wafer W is placed on the anti-slip member 13 d. Therefore, the position and direction do not deviate even when tilted. Therefore, even if the stopper member is not provided in the opening serving as the loading / unloading port for the semiconductor wafer W, the semiconductor wafer W does not fall off and the crystal orientation can always be kept in a fixed direction. The process can be performed smoothly.
- the unloading is performed by the holding unit 22 a performing an operation reverse to that described above.
- the spring member 16 relaxes the pressing force as described above, so that the semiconductor wafer W can be safely and reliably carried out without being damaged.
- the spacer 19 is provided, the contraction of the spring member 16 is regulated, so that the semiconductor wafer housed under the spacer is not damaged.
- the semiconductor wafer since the plate capable of supporting the entire surface of the semiconductor wafer is provided, even if the semiconductor wafer is divided by the thinned semiconductor wafer tip dicing. It can be safely and securely supported and contained. Therefore, the semiconductor wafer is useful in that it does not damage the semiconductor chip during processing, transportation, and the like.
- each plate is supported by a spring member, the semiconductor wafer is transported into the wafer cassette and is supported by the plate or supported by the plate.
- the pressing force is reduced by the spring member even if the semiconductor wafer is pressed, and the semiconductor wafer is safely and securely inserted into the wafer cassette without damaging the wafer.
- Semiconductors It is useful for safely and reliably carrying semiconductor wafers into and out of wafer cassettes. Furthermore, if a non-slip member is laid on the support surface of the plate, the contained semiconductor wafer is held without slipping. Therefore, a thin semiconductor device can be accommodated without bending even if it is E-C, and it does not fall off or shift in position or direction. Therefore, the next process can be performed without correcting the position or direction shift. Useful for performing smoothly.
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
- Packaging Frangible Articles (AREA)
Abstract
Description
明 細 書 ゥエー/ヽカセッ卜 技術分野 Description ゥ A / ヽ Cassette Technical Field
この発明は、 半導体ゥエーハの加工に用いる各種の加工装置において半導体ゥ エーハを収容するゥエーハカセッ卜に関する。 背景技術 The present invention relates to a wafer cassette for accommodating a semiconductor wafer in various processing apparatuses used for processing a semiconductor wafer. Background art
I C、 L S I等の集積回路が複数形成された半導体ゥヱ一ハは、 裏面の研削に より所定の厚さに形成された後、 ダイシングにより個々の半導体チップに分割さ れる。 半導体ゥエー八が裏面研削工程からダイシング工程へ搬送される際には、 通常第 8図に示すようなゥェ一ハカセット 5 0が用いられる。 この場合、 半導体 ゥエーハ Wは、 先端部に吸着部 5 1を備えた搬出入手段 5 2によって半導体ゥェ ーハ Wがゥェ一ハカセット 5 0に収容され、 ゥエーハカセッ卜 5 0の両側面の内 側に設けられた溝部 5 3によって両端が支持された状態となる。 A semiconductor wafer on which a plurality of integrated circuits such as IC and LSI are formed is formed into a predetermined thickness by grinding the back surface, and then divided into individual semiconductor chips by dicing. When the semiconductor wafer 8 is transported from the back grinding step to the dicing step, a wafer cassette 50 as shown in FIG. 8 is usually used. In this case, the semiconductor wafer W is housed in the wafer cassette 50 by the carrying-in / out means 52 provided with the suction portion 51 at the tip, and the semiconductor wafer W is provided on both sides of the wafer cassette 50. Both ends are supported by the groove 53 provided on the side.
しかしながら、 研削後は半導体ゥ: cーハ Wが薄くなつて剛性が低下しているた め、 第 9図に示すように、 表面に保護テープ Tが貼着されていても、 撓みが生じ ることがある。 この場合はゥエーハカセッ卜 5 0の溝部 5 3によって支持するこ とができないために半導体ゥエーハ Wを収容することができないという問題があ る。 特に、 近年の携帯電話機等の各種機器の小型化、 薄型化、 軽量化のニーズに 応えるべく厚さが数十; u mに形成される半導体ゥ; Lーハにあってはこのような問 題が顕著である。 However, after the grinding, the semiconductor ゥ: c-ha W becomes thinner and the rigidity is reduced, so that bending occurs even if the protective tape T is adhered to the surface as shown in Fig. 9. Sometimes. In this case, there is a problem that the semiconductor wafer W cannot be accommodated because it cannot be supported by the groove 53 of the wafer cassette 50. In particular, semiconductors that are formed to have a thickness of several tens of μm in order to meet the needs for miniaturization, thinning, and weight reduction of various devices such as mobile phones in recent years. Is remarkable.
また、 半導体ゥエーハの表面に予めチップの厚さに相当する深さの溝を形成し ておき、 その後に裏面を研削して当該溝を表出させて個々のチップに分割すると いう先ダイシングの技術においては、 保護テープが貼着されているために研削後 も半導体ゥヱ一八の外形は維持しているものの、 すでに個々のチップに分割され て剛性がないために撓んでしまい、 この場合も上記と同様にゥェ一ハカセット 5 0に収容することができないという問題がある。 In addition, a pre-dicing technology in which a groove having a depth corresponding to the thickness of a chip is formed in advance on the surface of a semiconductor wafer, and then the back surface is ground to expose the groove and divide the chip into individual chips. In, after grinding because the protective tape is stuck Although the outer shape of the semiconductor device is maintained, it is already divided into individual chips and deflects due to lack of rigidity. In this case, the semiconductor device can be housed in the wafer cassette 50 in the same manner as described above. There is a problem that can not be.
更に、 溝部 5 3が滑りやすい材質によって形成されている場合は、 搬送時に半 導体ゥエーハが開口部から脱落するおそれがある。 その一方、 開口部にストツバ 部材を配設した場合には、 そのストツバ部材に半導体ゥ: cーハが接触して割れる おそれがある。 従って、 実際には、 開口部にストツバ部材を設けることなく、 開 口部を上に向けて搬送を行わなければならない。 Further, when the groove 53 is formed of a slippery material, the semiconductor wafer may fall off from the opening during transportation. On the other hand, if a stove member is provided in the opening, the semiconductor member may come into contact with the stove member and break. Therefore, in actuality, it is necessary to carry the sheet with the opening facing upward without providing a stopper member at the opening.
また、研削後の半導体ゥ: —ハは、次工程のために収容位置や向き(結晶方位) を揃えなければならない場合があるが、 ゥエーハカセッ卜の搬送中等においてゥ エーハカセッ卜内で半導体ゥ: π—八の位置がずれたり回転したりすると、 次工程 に支障が生じるという問題が生じる。 In addition, the semiconductors after grinding may need to be aligned in the accommodating position and orientation (crystal orientation) for the next process. However, during transport of the ahka cassette, etc., the semiconductor in the ah cassette: π — If the position of 8 is shifted or rotated, the problem that the next process will be hindered will occur.
そこで本発明は、 剛性を失った半導体ゥ X—ハゃ半導体ゥエーハの外形を維持 した半導体チップをゥ: E—ハカセッ卜に収容する場合において、 半導体ゥエーハ 等を確実に収容できるようにすると共に、 収容された半導体ゥ: nーハ等が脱落し たり位置ずれしたり回転したりするのを防止することを目的としている。 発明の開示 In view of the above, the present invention provides a semiconductor chip, which maintains the outer shape of a semiconductor X-ha semiconductor a wafer that has lost its rigidity, in an E-hakaset. Enclosed semiconductors: The purpose is to prevent the semiconductor devices from falling off, displacing, or rotating. Disclosure of the invention
本発明は、 半導体ゥ X—ハを収容するゥヱ一ハカセットであって、 収容された 半導体ゥエーハを支持するプレー卜と、 プレートの上方に配設される天板と、 該 プレー卜の下方に配設される底板と、 プレートを貫通し天板から底板に至るロッ ドとから少なくとも構成され、 プレー卜が、 半導体ゥ: E—ハの全面を支持するよ うに構成されることを特徴とするゥエーハカセッ卜を提供する。 The present invention relates to a cassette for accommodating a semiconductor X-ha, a plate supporting the housed semiconductor aa, a top plate disposed above the plate, and a plate below the plate. It is characterized by comprising at least a bottom plate provided, and a rod penetrating the plate and extending from the top plate to the bottom plate, wherein the plate is configured to support the entire surface of the semiconductor substrate E: E-H.ゥ Provide an ehakaset.
そしてこのゥエーハカセットは、 ロッドにはプレートを支持すると共に、 上下 方向に隣り合うプレートとの間隔を維持するばね部材が揷着されること、 ばね部 材はコイルばねであり、 ロッドに遊嵌してプレートを支持すること、 ロッドとコ ィルばねとの間に遊嵌し、 上下方向に隣り合うプレー卜の間隔を一定に保つと共 に、 コイルばねの収縮を規制するスぺーサが揷着されること、 プレートを貫通し て天板から底板に至り、 収容された半導体ゥ: ε—八の位置を規制する位置規制口 ッドが配設されること、 位置規制ロッドに緩衝部材を被覆したこと、 プレー卜の 支持面に滑り止め部材が敷設されていることを付加的要件とするものである。 このように構成されるゥエーハカセッ卜においては、 半導体ゥェ一ハの全面を 支持することができるプレートを配設したため、 薄くなつた半導体ゥエーハゃ先 ダイシングにより分割された半導体ゥェ一ハであっても安全かつ確実に支持して 収容することができる。 In this wafer cassette, a spring member for supporting the plate on the rod and maintaining a gap between vertically adjacent plates is attached to the rod, and the spring member is a coil spring, and is loosely fitted to the rod. To support the plate by And a spacer that regulates the contraction of the coil spring is attached, while maintaining a constant spacing between vertically adjacent plates, and through the plate. From the top plate to the bottom plate, the housed semiconductor ゥ: A position regulating pad that regulates the position of ε-8 is provided, the position regulating rod is covered with a cushioning member, and the support surface of the plate is An additional requirement is that a non-slip member is laid. In the wafer cassette configured as described above, since a plate capable of supporting the entire surface of the semiconductor wafer is provided, the thinned semiconductor wafer tip is a semiconductor wafer divided by dicing. Can be safely and reliably supported and contained.
また、 各プレートをばね部材によって支持しているため、 半導体ゥエーハをゥ エーハカセット内部に搬入してプレートに支持させる際、 またはプレー卜に支持 された半導体ゥ: n—ハを上方から吸着して搬出する際に、 半導体ゥエーハを押圧 してもばね部材によって押圧力が緩和され、 半導体ゥヱーハを損傷させることな く安全かつ確実にゥエーハカセッ卜内への半導体ゥヱ一八の搬入及びゥエーハカ セッ卜からの半導体ゥェ一ハの搬出を行うことができる。 Also, since each plate is supported by a spring member, the semiconductor wafer is carried into the wafer cassette and is supported by the plate, or the semiconductor supported by the plate is sucked from above. When the semiconductor wafer is unloaded, the pressing force is reduced by the spring member even if the semiconductor wafer is pressed, and the semiconductor wafer is safely and securely loaded into the wafer cassette without damaging the semiconductor wafer, and the semiconductor wafer is removed from the wafer cassette. Semiconductor wafers can be carried out.
更に、 プレートの支持面に滑り止め部材を敷設すれば、 収容された半導体ゥ工 一八が滑らずに保持されるため、 薄い半導体ゥエーハでも湾曲させることなく収 容することができると共に、脱落及び位置や向きのずれを生じさせることがない。 図面の簡単な説明 Furthermore, if a non-slip member is laid on the support surface of the plate, the accommodated semiconductor device 18 can be held without slipping, so that even a thin semiconductor device can be accommodated without bending, and the semiconductor device can be dropped and removed. There will be no shift in position or orientation. BRIEF DESCRIPTION OF THE FIGURES
第 1図は、 本発明に係るゥエーハカセットを実施するための形態の一例を示す 分解斜視図であり、 FIG. 1 is an exploded perspective view showing an example of an embodiment for implementing a wafer cassette according to the present invention,
第 2図は、 同ゥェ一ハカセットを示す斜視図であり、 FIG. 2 is a perspective view showing the wafer cassette,
第 3図は、 同ゥエーハカセッ卜に配設されるスぺーサを示す斜視図であり、 第 4図は、 同スぺーサ及びばね部材がロッドに遊嵌した状態を示す断面図であ り、 FIG. 3 is a perspective view showing a spacer provided on the same cassette, and FIG. 4 is a cross-sectional view showing a state where the spacer and a spring member are loosely fitted to a rod.
第 5図は、 滑り止め部材が敷設されたプレートを示す正面図であり、 第 6図は、 本発明に係るゥ I一ハカセッ卜が使用される装置の一例である研削 装置を示す斜視図であり、 FIG. 5 is a front view showing a plate on which a non-slip member is laid, FIG. 6 is a perspective view showing a grinding apparatus which is an example of an apparatus using the I-hasakette according to the present invention,
第 7図は、 同研削装置においてゥエーハカセッ卜に半導体ゥエーハを収容する 様子を示す正面図であり、 FIG. 7 is a front view showing a state in which a semiconductor wafer is housed in a wafer cassette in the grinding apparatus.
第 8図は、 従来のゥエーハカセットを示す斜視図であり、 FIG. 8 is a perspective view showing a conventional wafer cassette,
第 9図は、 剛性のない半導体ゥヱーハを示す正面図である。 発明を実施するための最良の形態 FIG. 9 is a front view showing a semiconductor wafer having no rigidity. BEST MODE FOR CARRYING OUT THE INVENTION
本発明を実施するための最良の形態として、 第 1図に示すゥエーハカセット 1 0について説明する。 このゥエーハカセット 1 0は、 把持用のハンドル 1 1 aが 形成された天板 1 1 と、 底板 1 2と、 収容される半導体ゥ X—八の全面を支持す る複数のプレート 1 3と、 すべてのプレート 1 3を貫通して天板 1 1及び底板 1 2に至るロッド 1 4とを備えており、天板 1 1はプレート 1 3の上方に配設され、 底板 1 2はプレート 1 3の下方に配設されている。 なお、 プレート 1 3は、 半導 体ゥェーハの全面を支持できる形状であれば、 図示の形状には限定されない。 図示の例では 4本のロッド 1 4を備えており、 各ロッド 1 4は、 プレート 1 3 に形成されたロッド貫通孔 1 3 aを貫通し、 口ッド止めねじ 1 5によって底板 1 2に固定され、 ロッド 1 4の上端に形成された雄ねじ部 1 4 aが天板 1 1に形成 された雌ねじ部 1 1 bに螺合して天板 1 1に固定される。 なお、 ロッド 1 4は、 少な〈とも 3本備えていることが必要であり、 5本以上備えていてもよい。 As the best mode for carrying out the present invention, a wafer cassette 10 shown in FIG. 1 will be described. The wafer cassette 10 includes a top plate 11 on which a gripping handle 11 a is formed, a bottom plate 12, and a plurality of plates 13 for supporting the entire surface of the semiconductor X- 8 to be housed. And a rod 14 penetrating through all the plates 13 to the top plate 11 and the bottom plate 1 2, the top plate 1 1 being disposed above the plate 13, and the bottom plate 1 2 being a plate 1 It is located below 3. The plate 13 is not limited to the illustrated shape as long as it can support the entire surface of the semiconductor wafer. In the illustrated example, four rods 14 are provided.Each rod 14 passes through a rod through hole 13 a formed in the plate 13, and is connected to the bottom plate 12 by a set screw 15. It is fixed, and the male screw part 14 a formed on the upper end of the rod 14 is screwed into the female screw part 11 b formed on the top plate 11 and fixed to the top plate 11. The rods 14 need to have at least three rods, and may have five or more rods.
第 2図に示すように、 4本のロッド 1 4にはそれぞればね部材 1 6が上下方向 に隣り合うプレート 1 3の間において遊嵌しており、 このばね部材 1 6は、 上下 方向に隣り合うプレート 1 3との間隔を維持すると共に、 プレート 1 3に押圧力 が加わった際には緩衝部材としての役割を果たすものである。 ばね部材 1 6は、 図示の例ではコイルばねであり、 この場合のコイルばねは、 それぞれがプレート 1 3を支持している。また、天板 1 1 と最上段のプレート 1 3との間においては、 リング 1 1 dがロッド 1 4に揷入されている。 As shown in FIG. 2, a spring member 16 is loosely fitted to each of the four rods 14 between the vertically adjacent plates 13, and this spring member 16 is vertically adjacent to the four rods 14. The gap between the plate 13 and the mating plate 13 is maintained, and when a pressing force is applied to the plate 13, the plate 13 serves as a cushioning member. The spring members 16 are coil springs in the illustrated example, and each of the coil springs supports the plate 13. Also, between the top plate 11 and the uppermost plate 13, Ring 1 1 d is inserted into rod 14.
また、 第 1図に示したように、 5本の位置規制ロッド 1 7が各プレート 1 3に 形成された位置規制ロッド貫通孔 1 3 bを貫通し、 位置規制ロッド 1 7の上端に 形成された雄ねじ部 1 7 aが天板 1 1に形成された雌ねじ部 1 1 cに螺合して固 定され、 位置規制ロッド 1 7の下端はロッド止めねじ 1 8によって固定される。 位置規制ロッド 1 7は、 少なくとも 3本配設されればよく、 収容される半導体ゥ エーハ Wの位置を規制する役割を果たす。 この位置規制ロッド 1 7には、 半導体 ゥエーハ Wの外周部が衝突する際の衝撃を和らげる緩衝部材として、 ビニール等 を被覆させておくことが望ましい。 Also, as shown in FIG. 1, five position regulating rods 17 penetrate through the position regulating rod through holes 13 b formed in each plate 13 and are formed at the upper end of the position regulating rod 17. The male screw portion 17a is screwed and fixed to the female screw portion 11c formed on the top plate 11, and the lower end of the position regulating rod 17 is fixed by a rod screw 18. At least three position regulating rods 17 need only be provided, and serve to regulate the position of the semiconductor wafer W to be housed. It is preferable that the position regulating rod 17 is coated with vinyl or the like as a cushioning member for cushioning an impact when the outer periphery of the semiconductor wafer A collides.
なお、 第 3図に示すリング状のスぺーサ 1 9をばね部材 1 6の内部に収容し、 第 4図に示すように、 ロッド 1 4とばね部材 1 6との間にスぺーサ 1 9を遊嵌さ せることが好ましい。 この場合は、 スぺーサ 1 9が通常の状態で上下方向に隣り 合うプレート 1 3の間隔を一定に保つと共に、 スぺーサ 1 9に形成された収縮規 制部 1 9 aがばね部材 1 6の収縮を規制する。 またこのスぺ一サ 1 9の長さ及び ばね部材 1 6の長さを調整することで、 種々の厚さの半導体ゥ: n—ハに対応する ことができる。 In addition, the ring-shaped spacer 19 shown in FIG. 3 is housed inside the spring member 16, and as shown in FIG. Preferably, 9 is loosely fitted. In this case, the spacer 19 keeps a constant interval between the vertically adjacent plates 13 in a normal state, and the shrinkage restricting portion 19 a formed on the spacer 19 forms the spring member 1. Regulate the shrinkage of 6. Further, by adjusting the length of the spacer 19 and the length of the spring member 16, it is possible to cope with semiconductors of various thicknesses: n-c.
第 5図に示すように、 プレート 1 3の支持面 1 3 cには、 滑り止め部材 1 3 d が敷設されている。 この滑り止め部材 1 3 dとしては、 各種の樹脂、 例えば、 ェ ラストマー樹脂、 シリコーン樹脂、 天然樹脂等を用いることができる。 また、 ゴ ム、 ポンド剤等を用いることもできる。 As shown in FIG. 5, a non-slip member 13 d is laid on the support surface 13 c of the plate 13. As the non-slip member 13d, various resins, for example, an elastomer resin, a silicone resin, a natural resin, and the like can be used. Also, rubber, pounds, etc. can be used.
これらの樹脂は、支持面 1 3 cに塗布することにより敷設することもできるし、 予めシート状に形成されたシール部材を貼着することによつても敷設することも できる。 予めシート状に形成されたシール部材は、 メッシュ状であってもよい。 また、 滑り止め部材 1 3 dは、 支持面 1 3 cの全面に敷設してもよいし、 一部に 敷設するようにしてもよい。 These resins can be laid by applying them to the support surface 13c, or they can be laid by attaching a sealing member formed in a sheet shape in advance. The seal member previously formed in a sheet shape may be in a mesh shape. Further, the non-slip member 13 d may be laid on the entire surface of the support surface 13 c or may be laid on a part thereof.
このように構成されるゥ: c一ハカセット 1 0は、 例えば第 6図に示す研削装置 2 0に載置されて研削後の半導体ゥエーハを収容する。 この研削装置 2 0におい ては、研削前の複数の半導体ゥヱーハがゥヱ一ハカセッ卜 2 1に収容されており、 保持部 2 2 aを有する搬出入手段 2 2によって搬出されて位置合わせテーブル 2 3に載置される。 そして、 半導体ゥエーハの位置合わせがなされた後に第一の搬 送手段 2 4によってチャックテーブル 2 5に載置され保持される。 チャックテー ブル 2 5は、 ターンテーブル 2 6によって自転及び公転可能に支持されており、 ターンテーブル 2 6が所要角度 (図示の例では 9 0度) 回転することによって第 一の研削手段 2 7の直下に位置付けられる。 ここで、 第一の研削手段 2 7は、 壁 部 2 8の内側の面に垂直方向に配設された一対のガイドレール 2 9に摺動可能に 係合した支持板 3 0に連結され、 パルスモータ 3 1によって駆動されて支持板 3 0と共に上下動する構成となっている。 The cassette 10 thus constructed is, for example, a grinding machine shown in FIG. The semiconductor wafer after being mounted on the wafer 20 is ground. In this grinding apparatus 20, a plurality of semiconductor wafers before grinding are housed in a single cassette 21. The semiconductor wafers are carried out by carrying-in / out means 22 having a holding portion 22a, and are brought out of the positioning table 2. Placed on 3. Then, after the semiconductor wafer is aligned, the semiconductor wafer is placed and held on the chuck table 25 by the first carrying means 24. The chuck table 25 is supported by a turntable 26 so as to be able to rotate and revolve, and the turntable 26 is rotated by a required angle (90 degrees in the illustrated example), so that the first grinding means 27 is rotated. It is positioned directly below. Here, the first grinding means 27 is connected to a support plate 30 slidably engaged with a pair of guide rails 29 provided in a direction perpendicular to the inner surface of the wall portion 28, It is configured to be driven by a pulse motor 31 and move up and down together with the support plate 30.
第一の研削手段 2 7は、 垂直方向の軸心を有するスピンドル 3 2と、 スピンド ル 3 2を回転駆動するモータ 3 3と、 スピンドル 3 2の下端に形成されたマウン タ 3 4と、 マウンタ 3 4に固定された研削ホイール 3 5とを備え、 研削ホイール 3 5の下面には粗研削用の研削砥石 3 6が固着されており、 モータ 3 3に駆動さ れてスピンドル 3 2が回転するのに伴い研削ホイール 3 5が回転する構成となつ ている。 The first grinding means 27 includes a spindle 32 having a vertical axis, a motor 33 for rotating and driving the spindle 32, a mounter 34 formed at the lower end of the spindle 32, and a mounter. A grinding wheel 35 fixed to 3 4 is provided, and a grinding wheel 36 for rough grinding is fixed to the lower surface of the grinding wheel 35, and the spindle 32 is driven by the motor 33 to rotate. As a result, the grinding wheel 35 rotates.
研削時は、 チャックテーブル 2 5が回転すると共に、 研削ホイール 3 5が回転 しながら第一の研削手段 2 7が下降し、 回転する研削砥石 3 6が半導体ゥ: Lーハ Wの裏面に接触して当該裏面が粗研削される。粗研削された半導体ゥエーハ Wは、 ターンテーブル 2 6が所要角度 (図示の例では 9 0度) 回転することにより第二 の研削手段 3 7の直下に位置付けられる。 第二の研削手段 3 7は、 壁部 2 8の内 側の面に垂直方向に配設された一対のガイドレール 3 8に摺動可能に係合した支 持板 3 9に連結され、 パルスモータ 4 0によって駆動されて支持板 3 9と共に上 下動する構成となっている。 During grinding, the first grinding means 27 descends while the grinding wheel 35 rotates while the chuck table 25 rotates, and the rotating grinding wheel 36 contacts the back surface of the semiconductor ゥ: L-ha W Then, the back surface is roughly ground. The roughly ground semiconductor wafer W is positioned immediately below the second grinding means 37 by rotating the turntable 26 by a required angle (90 degrees in the illustrated example). The second grinding means 37 is connected to a support plate 39 slidably engaged with a pair of guide rails 38 arranged vertically on the inner surface of the wall portion 28, It is configured to be driven up and down with the support plate 39 by being driven by the motor 40.
第二の研削手段 3 7は、 垂直方向の軸心を有するスピンドル 4 1と、 スピンド ル 4 1を回転駆動するモータ 4 2と、 スピンドル 4 1の下端に形成されたマウン タ 4 3と、 マウンタ 4 3に固定された研削ホイール 4 4とを備え、 研削ホイール 4 4の下面には仕上げ研削用の研削砥石 4 5が固着されており、 モータ 4 2に駆 動されてスピンドル 4 1が回転するのに伴い研削ホイール 4 4が回転する構成と なっている。 The second grinding means 37 includes a spindle 41 having a vertical axis and a spindle A motor 4 2 for rotating and driving the spindle 4 1, a mounter 4 3 formed at the lower end of the spindle 41, and a grinding wheel 44 fixed to the mounter 43. The grinding wheel 45 for finish grinding is fixed, and the grinding wheel 44 rotates as the spindle 41 rotates by being driven by the motor 42.
研削時は、 チャックテーブル 2 5が回転すると共に、 研削ホイール 4 4が回転 しながら第二の研削手段 3 7が下降し、 回転する研削砥石 4 5が半導体ゥエーハ Wの裏面に接触して当該裏面が仕上げ研削される。 仕上げ研削の終了後は、 チヤ ックテーブル 2 5が移動して第二の搬送手段 4 6の近傍に位置付けられ、 第二の 搬送手段 4 6によって研削後の半導体ゥ: π—ハ Wが洗浄手段 4 7に搬送される。 そしてここで洗浄された半導体ゥ: L—ハ Wは、 搬出入手段 2 2によってゥエーハ カセット 1 0に収容される。 At the time of grinding, the second grinding means 37 descends while the chuck table 25 rotates and the grinding wheel 44 rotates, and the rotating grinding wheel 45 contacts the back surface of the semiconductor wafer W and contacts the back surface. Is finish-ground. After the finish grinding, the chuck table 25 moves to be positioned near the second transport means 46, and the semiconductor ゥ: π-c W is ground by the second transport means 46. Conveyed to 7. Then, the semiconductor washed here: L-W is housed in the wafer cassette 10 by the carrying-in / out means 22.
ゥエーハカセット 1 0に収容された半導体ゥエーハ Wは、 第 1図及び第 2図に 示したプレート 1 3によって全面を支持されるため、 研削により薄くなつて剛性 が低下した半導体ゥエーハゃ、 先ダイシングにより分割されて剛性がなくなった 半導体ゥエーハでも、 安全かつ確実に支持することができる。 The semiconductor wafer W housed in the wafer cassette 10 is entirely supported by the plate 13 shown in FIGS. 1 and 2, so the semiconductor wafer W is thinned by grinding and has reduced rigidity. It can safely and reliably support a semiconductor wafer whose rigidity has been lost due to the division.
ゥエーハカセット 1 0に半導体ゥエーハを収容する際は、第 7図に示すように、 搬出入手段 2 2を構成する保持部 2 2 aの下面において半導体ゥ X—ハ Wを吸引 保持し、 保持部 2 2 aが水平移動してゥエーハカセット 1 0の内部に進入し、 更 に保持部 2 2 aが下降して吸着力を解除することにより半導体ゥ:]:ーハ Wがプレ ート 1 3の上に載置される。 従って、 半導体ゥ: c—ハ Wの載置の際に保持部 2 2 aからプレート 1 3に対して押圧力が加わるが、 この際はばね部材 1 6の収縮に よって押圧力が緩和されるため、 半導体ゥエーハ Wが損傷することがなく、 安全 かつ確実に収容することができる。 また、 スぺーサ 1 9が配設されている場合に は、 スぺーサ 1 9に形成された収縮規制部 1 9 aによってばね部材 1 6の収縮が 規制されるため、 その下方に収容されている半導体ゥ: Lーハを損傷させることが ない。 When accommodating the semiconductor wafer in the wafer cassette 10, as shown in FIG. 7, the semiconductor wafer X is sucked and held on the lower surface of the holding portion 22a constituting the carrying-in / out means 22, and is held. The part 22a moves horizontally and enters the inside of the wafer cassette 10, and the holding part 22a descends to release the suction force. Placed on 13 Therefore, when the semiconductor ゥ: c—c W is placed, a pressing force is applied from the holding portion 22 a to the plate 13. In this case, the pressing force is reduced by the contraction of the spring member 16. Therefore, the semiconductor wafer W can be housed safely and securely without being damaged. Further, when the spacer 19 is provided, the contraction of the spring member 16 is restricted by the contraction restricting portion 19a formed in the spacer 19, so that the spring member 16 is accommodated below the spacer. Semiconductor ゥ: L-ha can be damaged Absent.
更に、 第 5図に示したようにプレート 1 3の支持面 1 3 cに滑り止め部材 1 3 dが敷設されている場合は、 半導体ゥヱーハ Wが滑り止め部材 1 3 dの上に載置 されるため、 傾いたりしても位置や向きがずれることがない。 従って、 半導体ゥ エーハ Wの搬出入口である開口部にストツパ部材が配設されていなくても半導体 ゥエーハ Wが脱落することがなく、 結晶方位も常に一定の向きに保つことができ るため、 次工程を円滑に遂行することができる。 Further, when the anti-slip member 13 d is laid on the support surface 13 c of the plate 13 as shown in FIG. 5, the semiconductor wafer W is placed on the anti-slip member 13 d. Therefore, the position and direction do not deviate even when tilted. Therefore, even if the stopper member is not provided in the opening serving as the loading / unloading port for the semiconductor wafer W, the semiconductor wafer W does not fall off and the crystal orientation can always be kept in a fixed direction. The process can be performed smoothly.
一方、 半導体ゥエーハ Wをゥエーハカセット 1 0から搬出する場合は、 保持部 2 2 aが上記と逆の動作をすることにより搬出が行われるため、 半導体ゥ; L—ハ Wを保持する際には押圧力が加わるが、 前記同様ばね部材 1 6が押圧力を緩和さ せるため、 半導体ゥエーハ Wを損傷させることなく、 安全かつ確実に搬出するこ とができる。 また、 スぺーサ 1 9が配設されている場合には、 ばね部材 1 6の収 縮が規制されるため、 その下方に収容されている半導体ゥエーハを損傷させるこ とがない。 On the other hand, when the semiconductor wafer W is unloaded from the wafer cassette 10, the unloading is performed by the holding unit 22 a performing an operation reverse to that described above. Although a pressing force is applied, the spring member 16 relaxes the pressing force as described above, so that the semiconductor wafer W can be safely and reliably carried out without being damaged. Further, when the spacer 19 is provided, the contraction of the spring member 16 is regulated, so that the semiconductor wafer housed under the spacer is not damaged.
なお、 研削装置 2 0においては、 研削後の半導体ゥヱーハのみ本発明のゥエー ハカセット 1 0に収容することとしたが、 研削前の半導体ゥエーハについてもゥ エーハカセット 1 0に収容しておくことができる。 産業上の利用可能性 In the grinding apparatus 20, only the semiconductor wafer after grinding is housed in the wafer cassette 10 of the present invention, but the semiconductor wafer before grinding can be housed in the wafer cassette 10. . Industrial applicability
以上のように、 本発明に係るゥエーハカセットにおいては、 半導体ゥエーハの 全面を支持することができるプレートを配設したため、 薄くなつた半導体ゥエー ハゃ先ダイシングにより分割された半導体ゥエーハであっても安全かつ確実に支 持して収容することができる。 従って、 加工中及び搬送中等において半導体ゥェ ーハゃ半導体チップを破損させない点で有用である。 As described above, in the wafer cassette according to the present invention, since the plate capable of supporting the entire surface of the semiconductor wafer is provided, even if the semiconductor wafer is divided by the thinned semiconductor wafer tip dicing. It can be safely and securely supported and contained. Therefore, the semiconductor wafer is useful in that it does not damage the semiconductor chip during processing, transportation, and the like.
また、 各プレート間をばね部材によって支持しているため、 半導体ゥ; Lーハを ゥエーハカセット内部に搬送してプレー卜に支持させる際、 またはプレー卜に支 持された半導体ゥ Iーハを上方から吸着して搬出する際に、 半導体ゥエーハを押 圧してもばね部材によって押圧力が緩和され、 半導体ゥエーハを損傷させること なく安全かつ確実にゥヱーハカセット内への半導体ゥ: c一八の搬入及びゥェ一ハ カセッ卜からの半導体ゥエーハの搬出を安全かつ確実に行うのに有用である。 更に、 プレートの支持面に滑り止め部材を敷設すれば、 収容された半導体ゥェ ーハが滑らずに保持される。 従って、 薄い半導体ゥ: E—ハでも湾曲させることな く収容することができると共に、 脱落及び位置や向きのずれを生じさせることが ないため、 位置や向きのずれを修正することなく次工程を円滑に遂行するのに有 用である。 In addition, since each plate is supported by a spring member, the semiconductor wafer is transported into the wafer cassette and is supported by the plate or supported by the plate. When the semiconductor wafer held is sucked from above and carried out, the pressing force is reduced by the spring member even if the semiconductor wafer is pressed, and the semiconductor wafer is safely and securely inserted into the wafer cassette without damaging the wafer. Semiconductors: It is useful for safely and reliably carrying semiconductor wafers into and out of wafer cassettes. Furthermore, if a non-slip member is laid on the support surface of the plate, the contained semiconductor wafer is held without slipping. Therefore, a thin semiconductor device can be accommodated without bending even if it is E-C, and it does not fall off or shift in position or direction. Therefore, the next process can be performed without correcting the position or direction shift. Useful for performing smoothly.
Claims
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| AU2003242402A AU2003242402A1 (en) | 2002-06-20 | 2003-06-13 | Wafer cassette |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002179958A JP4267262B2 (en) | 2002-06-20 | 2002-06-20 | Wafer cassette |
| JP2002-179958 | 2002-06-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO2004008524A1 true WO2004008524A1 (en) | 2004-01-22 |
Family
ID=30112238
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/JP2003/007556 Ceased WO2004008524A1 (en) | 2002-06-20 | 2003-06-13 | Wafer cassette |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JP4267262B2 (en) |
| AU (1) | AU2003242402A1 (en) |
| WO (1) | WO2004008524A1 (en) |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6199493U (en) * | 1984-12-03 | 1986-06-25 | ||
| JPS61132398U (en) * | 1985-02-05 | 1986-08-18 | ||
| JPS62208884A (en) * | 1986-03-07 | 1987-09-14 | 株式会社東芝 | Gripper for robot |
| JPH0645332U (en) * | 1992-01-31 | 1994-06-14 | 信越石英株式会社 | Vertical wafer storage jig |
| JPH0936219A (en) * | 1995-07-24 | 1997-02-07 | Yodogawa Kasei Kk | Cassette for substrate |
| JPH0982791A (en) * | 1995-09-20 | 1997-03-28 | Advanced Display:Kk | Cassette |
| JP2000277603A (en) * | 1999-03-25 | 2000-10-06 | Shin Etsu Polymer Co Ltd | Wafer frame cassette |
-
2002
- 2002-06-20 JP JP2002179958A patent/JP4267262B2/en not_active Expired - Fee Related
-
2003
- 2003-06-13 AU AU2003242402A patent/AU2003242402A1/en not_active Abandoned
- 2003-06-13 WO PCT/JP2003/007556 patent/WO2004008524A1/en not_active Ceased
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6199493U (en) * | 1984-12-03 | 1986-06-25 | ||
| JPS61132398U (en) * | 1985-02-05 | 1986-08-18 | ||
| JPS62208884A (en) * | 1986-03-07 | 1987-09-14 | 株式会社東芝 | Gripper for robot |
| JPH0645332U (en) * | 1992-01-31 | 1994-06-14 | 信越石英株式会社 | Vertical wafer storage jig |
| JPH0936219A (en) * | 1995-07-24 | 1997-02-07 | Yodogawa Kasei Kk | Cassette for substrate |
| JPH0982791A (en) * | 1995-09-20 | 1997-03-28 | Advanced Display:Kk | Cassette |
| JP2000277603A (en) * | 1999-03-25 | 2000-10-06 | Shin Etsu Polymer Co Ltd | Wafer frame cassette |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2004023052A (en) | 2004-01-22 |
| JP4267262B2 (en) | 2009-05-27 |
| AU2003242402A1 (en) | 2004-02-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20230115122A1 (en) | Method of bonding thin substrates | |
| US6837776B2 (en) | Flat-object holder and method of using the same | |
| US6777310B2 (en) | Method of fabricating semiconductor devices on a semiconductor wafer using a carrier plate during grinding and dicing steps | |
| US6153536A (en) | Method for mounting wafer frame at back side grinding (BSG) tool | |
| US9595504B2 (en) | Methods and systems for releasably attaching support members to microfeature workpieces | |
| TWI559361B (en) | Apparatus and method for treating substrate | |
| JP2004207606A (en) | Wafer support plate | |
| TWI892652B (en) | Bonding device and bonding method | |
| JP2016154168A (en) | Delivery method for workpiece | |
| JP2003209080A (en) | Semiconductor wafer protection member and semiconductor wafer grinding method | |
| CN111146128B (en) | Die transfer module and die bonding apparatus having the same | |
| JP4673195B2 (en) | Wafer processing method | |
| JP2001284303A (en) | Grinding equipment | |
| US7846776B2 (en) | Methods for releasably attaching sacrificial support members to microfeature workpieces and microfeature devices formed using such methods | |
| JP4812660B2 (en) | Substrate handling equipment and substrate handling method | |
| JP2000332097A (en) | Wafer storage carrier, wafer transfer device and wafer transfer method | |
| US6869830B2 (en) | Method of processing a semiconductor wafer | |
| KR100670762B1 (en) | Wafer back polishing and tape applying apparatus and method | |
| TWI839869B (en) | Substrate processing device and substrate processing method | |
| WO2004008524A1 (en) | Wafer cassette | |
| JP2003077869A (en) | Semiconductor wafer processing method and supporting substrate used therefor | |
| JP7734031B2 (en) | cassette | |
| US20030073264A1 (en) | Method of manufacturing semiconductor device from semiconductor wafer having thick peripheral portion | |
| JP2002208625A (en) | Semiconductor wafer thinning method | |
| JP2003197710A (en) | Apparatus and method for processing thin layer of plate-like object |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| AK | Designated states |
Kind code of ref document: A1 Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NI NO NZ OM PH PL PT RO RU SC SD SE SG SK SL TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW |
|
| AL | Designated countries for regional patents |
Kind code of ref document: A1 Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LU MC NL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG |
|
| 121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
| 122 | Ep: pct application non-entry in european phase |