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WO2004095564A1 - Procede de manufacture d'un dispositif semi-conducteur avec un transistor bipolaire - Google Patents

Procede de manufacture d'un dispositif semi-conducteur avec un transistor bipolaire Download PDF

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Publication number
WO2004095564A1
WO2004095564A1 PCT/IB2004/050497 IB2004050497W WO2004095564A1 WO 2004095564 A1 WO2004095564 A1 WO 2004095564A1 IB 2004050497 W IB2004050497 W IB 2004050497W WO 2004095564 A1 WO2004095564 A1 WO 2004095564A1
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WIPO (PCT)
Prior art keywords
layer
semiconductor material
grooves
silicon
mask
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PCT/IB2004/050497
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English (en)
Inventor
Petrus H. C. Magnee
Raymond J. E. Hueting
Joost Melai
Michael A. A. In 't Zandt
Johannes J. T. M. Donkers
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Koninklijke Philips NV
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Koninklijke Philips Electronics NV
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Publication of WO2004095564A1 publication Critical patent/WO2004095564A1/fr
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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/01—Manufacture or treatment
    • H10D10/021—Manufacture or treatment of heterojunction BJTs [HBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/80—Heterojunction BJTs
    • H10D10/821—Vertical heterojunction BJTs
    • H10D10/891—Vertical heterojunction BJTs comprising lattice-mismatched active layers, e.g. SiGe strained-layer transistors

Definitions

  • the invention relates to a method of manufacturing a semiconductor device comprising a bipolar transistor, wherein a first layer of a semiconductor material in which the base of the transistor is formed is provided on a surface of a silicon body on which borders a surface layer of a first conductivity type which is formed on a more heavily doped contact layer of the first conductivity type, and wherein a second layer of a semiconductor material of the first conductivity type is locally provided on the first layer of semiconductor material to form the emitter of the transistor.
  • the more heavily doped contact layer may be a customary n-type, doped buried layer having a doping of, for example, 10 20 atoms per cm 3 ; the surface layer may be a less heavily doped n-type epitaxial layer having a doping of, for example, 10 17 atoms per cm 3 .
  • This epitaxially formed layer is doped such that the collector of the transistor can be formed in said layer.
  • the first layer of a semiconductor material wherein the base of the transistor is formed, may be a p-type doped silicon layer that is epitaxially grown on the surface layer, but also a layer composed of a number of sub-layers, such as a layer of silicon to which 5 to 25 at.% germanium is added, on which a silicon layer without additives may additionally be deposited, the layer comprising silicon and germanium being provided with a p-type doping. In the latter case, a so-termed heterojunction bipolar transistor (HBT) is formed.
  • the second layer of semiconductor material may be an n-type doped layer of amorphous or polycrystalline silicon, in which case the emitter of the transistor may be formed in the first layer of semiconductor material by diffusion of doping atoms from said second layer.
  • WO 00/17423 discloses a method of the type mentioned in the opening paragraph, wherein the first layer of semiconductor material is composed of sub-layers, including a layer of silicon to which 5 to 25 at.% germanium is added and a layer of silicon without additives which is deposited thereon. Into the layer comprising silicon and germanium, boron is introduced as the dopant.
  • the second layer of semiconductor material is locally provided on the first layer of semiconductor material by forming, on the first layer, a layer of isolating material having a window at the location of the transistor to be formed, after which the second layer is deposited on the isolating layer and, within the window formed therein, on the first layer of semiconductor material.
  • the emitter is formed in the upper sub-layer of the first semiconductor material, i.e. the silicon sub-layer without additives.
  • the part of the first layer of semiconductor material situated below the emitter forms the base of the transistor, and the part of the surface layer situated below said base forms the collector.
  • a conductor pattern is etched in the comparatively heavily doped second layer of semiconductor material; the emitter of the transistor may thus be connected to, for example, another transistor in the semiconductor device.
  • the layer of isolating material situated on the first layer is also etched in accordance with a pattern, after which an additional dopant is introduced into the exposed parts of the first layer of semiconductor material, as a result of which these parts obtain a relatively low electric resistance.
  • a conductor pattern may be formed too.
  • the first layer of semiconductor material When the second layer of semiconductor material and the underlying layer of isolating material are etched in accordance with a pattern, the first layer of semiconductor material must not be exposed at the location of the intrinsic emitter. Since alignment tolerances must be taken into account during etching of the pattern, a non-additionally doped part of the first layer of semiconductor material will remain between the base situated below the emitter and the well conducting parts of this first layer of semiconductor material. As a result, the transistor formed will exhibit a comparatively high base resistance, which adversely affects the operation thereof.
  • the method is characterized in accordance with the invention in that at the location of the transistor base to be formed, a mask is provided on the first layer of semiconductor material, after which the part of the first layer of semiconductor material that is not covered by the mask is removed and a layer of doped non-monocrystalline silicon is applied instead, after which an isolating layer is provided on the layer of non- monocrystalline silicon, the mask is removed, thereby forming a window within which the first layer of semiconductor material is exposed, and subsequently the second layer of semiconductor material is provided within said window.
  • the layer of non-monocrystalline silicon (amorphous or polycrystalline silicon) can be provided, in this case, by depositing a comparatively thick layer of non- monocrystalline silicon and subsequently subjecting this layer to a customary etching planarization treatment such as in the case of a chemical mechanical planarization. This treatment can be stopped when the upper side of the mask is exposed, after which the layer may be etched further until, for example, its thickness is substantially equal to that of the masked part of the first layer of semiconductor material.
  • the layer of non-monocrystalline silicon may be doped in situ during the deposition or, alternatively, by ion implantation after the deposition or after the planarizing etching treatment.
  • an isolating layer of silicon oxide may be formed on this layer of non-monocrystalline silicon by means of thermal oxidation.
  • a window leaving the previously masked part of the first layer of semiconductor material exposed is formed in the isolating layer.
  • the emitter is formed in this window.
  • the subjacent base is substantially equally large and directly contiguous to the well conducting layer of non-monocrystalline silicon.
  • the layer of non-monocrystalline silicon may be very highly doped with, for example, 5.10 20 atoms per cm 3 .
  • the connection of the base can thus be embodied so as to be very highly conducting, so that the transistor will exhibit a comparatively low base resistance.
  • the mask is formed on the first layer of semiconductor material in a double layer deposited on this first layer, which double layer is formed by a layer of silicon nitride on which a layer of silicon oxide is deposited, after which non-covered parts of the first layer of semiconductor material are etched away, a layer of non-monocrystalline silicon is deposited and planarized by etching until the layer of silicon nitride is exposed, after which the layer of isolating material is formed on the layer of non-crystalline silicon by an oxidation treatment.
  • the layer of silicon oxide forming the top layer of the mask enables a layer of semiconductor material comprising silicon and germanium to be selectively etched away with respect to the surface.
  • the thermal oxidation treatment where an isolating layer of silicon oxide is formed on the layer of non-monocrystalline silicon
  • the first layer of semiconductor material situated below the mask is protected by the layer of silicon nitride.
  • the mask can be readily etched away if, prior to the deposition of the silicon nitride layer wherein the mask is formed, the first layer of semiconductor material is provided with a layer of silicon oxide.
  • Said layer of silicon oxide which may be comparatively thin, protects the subjacent first layer of semiconductor material during removing the silicon nitride layer from the mask by etching. Further, the layer of silicon oxide can in practice be etched away very selectively from the first layer of semiconductor material; as indicated hereinabove, this layer in practice is a layer of silicon or a composite layer having a top layer of silicon. If, after said thermal oxidation, the thickness of the layer of non- monocrystalline silicon still exceeds that of the first layer of semiconductor material, then, when the mask is being removed, a window is formed in the layer of isolating material formed on the layer of non-monocrystalline silicon, which window extends into the layer of non-monocrystalline silicon.
  • the window an edge of this layer is then exposed. If the second layer of highly doped semiconductor material is subsequently deposited, then a short- circuit between the emitter and the base of the transistor takes place. This can be precluded in a simple manner if, prior to depositing the second layer of semiconductor material, the window formed during the removal of the mask is provided, at the location of its side walls, with a layer of isolating material. This can be carried out in a customary manner by depositing a layer of isolating material and subsequently carrying out an anisotropic etching treatment to remove the layer thus provided from the bottom of the window. This isolating layer may be comparatively thin.
  • the mask is used, after removal of the part of the first layer of semiconductor material that is not covered by the mask, to etch grooves in the surface layer next to the mask, which grooves are subsequently filled, after which, instead of the removed part of the first layer of semiconductor material, the layer of doped, non-monocrystalline silicon is provided on the surface and on the filled grooves.
  • the layer of non-monocrystalline silicon is directly contiguous to the part of the first layer of semiconductor material that is covered by the mask and also covers the grooves.
  • the collector would extend to below the heavily doped layer of non-monocrystalline silicon connected to the base, as a result of which this capacitance could be comparatively large.
  • a large capacitance between collector and base adversely affects the high-frequency properties of the transistor.
  • the grooves etched in the surface layer are filled substantially up to the surface of the silicon body. It is thus achieved that both the collector-base capacitance and the base resistance are minimal. If the grooves formed in the surface layer were filled to a level below the surface of the silicon body, then an edge of the collector zone would border on the layer of non-monocrystalline silicon provided on the filled grooves, resulting in a minimal base resistance but not in an entirely minimal collector-base capacitance. If the grooves were filled to a level above the surface, then an edge of the first layer of semiconductor material would not be in contact with the layer of highly doped non- monocrystalline silicon provided on the filled grooves, as a result of which the collector-base capacitance would be minimal, yet the base resistance would not be entirely minimal.
  • the grooves formed in the surface layer are provided with a layer of isolating material applied onto their walls extending transversely to the surface and onto their bottom parts, then the grooves can be filled with an isolating material as well as a conducting material.
  • the walls and bottom parts of the grooves are preferably provided with a layer of silicon oxide and a superjacent top layer of silicon nitride.
  • the grooves may then be filled by depositing a comparatively thick layer of silicon oxide and subsequently subjecting this layer to a planarizing etching treatment.
  • the latter layer of silicon nitride can be used as a stop layer in this process.
  • the subjacent layer of silicon oxide provides for good isolation.
  • the grooves formed in the surface layer and filled with isolating material are formed such that they can be used as field isolation regions. If the grooves are filled with a conductive material after their walls and bottom parts have been provided with a layer of isolating material, i.e. the grooves are provided, for example at their walls and bottom parts, with a layer of silicon oxide and are further filled with a highly doped non-monocrystalline silicon, then this conductive material is connected to the base of the transistor by the non-monocrystalline silicon provided on the grooves.
  • the grooves thus filled with substantially isolating material do not lead to an increase of the collector-base capacitance.
  • the electric field which is formed in the collector zone will, however, be smaller than that in the above-described embodiment of the method, in which case the grooves were filled with conductive material.
  • the gain factor at high frequencies will thus be higher than in this exemplary embodiment, yet breakdown of the transistor will occur at lower operating voltages.
  • Figs. 1 through 8 are diagrammatic, cross-sectional views of a few stages in the manufacture of a semiconductor device with a vertical bipolar transistor, use being made of a first embodiment of the method in accordance with the invention
  • Figs. 9 through 14 are diagrammatic, cross-sectional views of a few stages in the manufacture of a semiconductor device with a vertical bipolar transistor, use being made of a second embodiment of the method in accordance with the invention,
  • Figs. 15 through 20 are diagrammatic, cross-sectional views of a few stages in the manufacture of a semiconductor device with a vertical bipolar transistor, use being made of a third embodiment of the method in accordance with the invention
  • Figs. 21 through 28 are diagrammatic, cross-sectional views of a few stages in the manufacture of a semiconductor device with a vertical bipolar transistor, use being made of a fourth embodiment of the method in accordance with the invention.
  • Figs. 1 through 8 are diagrammatic, cross-sectional views of a few stages in the manufacture of a semiconductor device with a bipolar transistor.
  • the Figures only show the manufacture of a single transistor; it will be clear however that a semiconductor device with an integrated circuit may comprise very many such transistors as well as transistors of other types, diodes and, if necessary, passive components such as resistors and capacitors.
  • the collector is connected to a highly doped substrate in such a manner that the electron current flows completely in the vertical direction.
  • the component is a discrete semiconductor component.
  • For the starting material use is made of a slice of silicon 1 which, as shown in
  • Fig. 1 is provided with an epitaxially grown layer 2 that is n-type doped with approximately 5.10 16 atoms per cm 3 .
  • This layer 2 is doped such that the collector of the transistor can be formed in said layer.
  • An active region 4 and isolation regions 5 of silicon oxide isolating said region 4 are formed in this layer 2, so as to border on a surface 3 of said layer.
  • a buried contact layer 6 which is n-type doped with approximately 10 20 atoms per cm 3 as well as a contact zone 7 which is n-type doped with approximately 10 19 atoms per cm 3 and which borders on the surface 3 are formed in a customary manner.
  • a first layer of semiconductor material 8 is deposited on the surface 3 by means of a RPCVD process (Reduced Pressure Chemical Vapor Deposition Process).
  • said layer is built up of a number of sub-layers which, for clarity, are not separately indicated in the drawings.
  • the first sub-layer is an approximately 5 nm thick layer of silicon, after which an approximately 35 nm thick layer of Si ⁇ . x Ge x , where 0.05 ⁇ x ⁇ 0.25, to which less than 0.2 at.% carbon is added, and an approximately 30 nm thick layer of silicon are deposited.
  • the silicon body is placed in a reaction chamber through which a gas mixture is passed which comprises, in addition to a non-reactive carrier gas, in succession silane, a gas mixture with silane, germanium and carbon dioxide and silane.
  • a gas mixture which comprises, in addition to a non-reactive carrier gas, in succession silane, a gas mixture with silane, germanium and carbon dioxide and silane.
  • diborane is added to the gas mixture for a short period of time.
  • the layer is thus provided with a p-type doping with boron ions.
  • the deposited first layer of semiconductor material 8 is monocrystalline, and said deposited first layer is polycrystalline on the isolation regions 5.
  • the base of the transistor is formed in the layer with silicon and germanium, the emitter in the superjacent layer of silicon is formed by diffusion of doping atoms from a second layer of semiconductor material that is to be provided at a later stage.
  • a layer packet 11, 12, 13 comprising an approximately 20 nm thick layer of silicon oxide 11, an approximately 100 nm thick layer of silicon nitride 12 and an approximately 100 nm thick layer of silicon oxide 13 there is formed a mask 9 on the first semiconductor layer 8 at the location of the base to be formed.
  • a mask 10 is formed that covers, inter alia, the contact region 7.
  • the parts of the first semiconductor layer 8 that are not covered by the mask 9, 10 are subsequently etched away.
  • a layer of non-monocrystalline, here polycrystalline, silicon 16 is provided.
  • a thick layer of polycrystalline silicon 14 is deposited in a customary manner, which layer is p-type doped during the deposition with approximately 10 20 atoms per cm 3 .
  • a customary chemical-mechanical polishing treatment is carried out which stops automatically on the layer of silicon nitride 12 present in the mask 9, 10. Relatively well conducting base contacts 15 are thus formed.
  • the layer of non-monocrystalline silicon may, like in this example, be doped in situ during the deposition process, however, doping by ion implantation after the deposition or after the planarizing etch treatment is also possible.
  • the polycrystalline silicon of the base contacts 15 is subsequently provided, as shown in Fig. 5, with an isolating layer of silicon oxide 16 by an oxidation treatment, in this case a customary thermal oxidation, the layer of the first semiconductor material 8 situated below the mask 9, 10 being protected by the layer of silicon nitride 12 of the mask 9, 10.
  • the mask 9, 10 is removed, as a result of which a window 17 is formed within which the first layer of semiconductor material 8 is exposed.
  • the mask 9, 10 can be etched away in a simple manner, in this case, as the layer of silicon nitride 12 of the mask 9, 10 is provided on a layer of silicon oxide 11.
  • the base contacts 15 formed in the layer of non- monocrystalline silicon 14 have a larger thickness than the first layer of semiconductor material 8, so that upon the removal of the mask 9, a window 17 is formed that extends into the layer of non-monocrystalline silicon. An edge of this layer, visible in Fig. 6, is then exposed within the window.
  • the second layer of highly doped semiconductor material 19 causes a short-circuit between the emitter and the base of the transistor.
  • a subsequent thermal treatment is applied to form the emitter 20 of the transistor in the first layer of semiconductor material 8 by diffusion of doping atoms from the second layer of semiconductor material 19.
  • the part of the first layer of semiconductor material 8 situated below the emitter 20 forms the base 21 of the transistor, the part of the active region 4 situated below said base forms the collector 22.
  • a conductor 23 is formed in the second layer of semiconductor material 19, as a result of which the emitter 20 can be contacted, and the layer of silicon oxide 16 is locally removed from the base contacts 15, so that the base 21 can be contacted.
  • the collector can be contacted via the buried contact layer 6 and the exposed contact region 7. It will be obvious that also other conductor tracks can be formed in the layer of non-monocrystalline silicon 15 as well as in the second layer of semiconductor material 19, which other conductor tracks connect the transistor shown to, for example, other transistors in the semiconductor device.
  • an isolating layer may be provided over the transistor shown in Fig. 8, which isolating layer is provided with contact windows for contacting the contacts 17, 15 and 23. Further wiring may then be provided on this isolating layer.
  • the base 21 is directly contiguous to the base contacts 15 formed in the well-conducting layer of non-monocrystalline silicon 14.
  • the layer 14 of non-monocrystalline silicon can be highly doped with approximately 5.10 20 atoms per cm 3 during its deposition, the base 21 can be connected via the contacts 15 so as to be highly conductive, so that the transistor will exhibit a comparatively low base resistance.
  • Figs. 9 through 14 are diagrammatic, cross-sectional views of a few stages in the manufacture of a semiconductor device, a preferred embodiment of the method being used enabling a transistor having even better properties to be obtained.
  • the same reference numerals are used as in the preceding Figures, whenever possible.
  • the mask 9, 10 is used, after the removal of the part of the first layer of semiconductor material 8 that is not covered by the mask 9, 10, to etch grooves 24 in the surface layer 2 next to the mask 9, which grooves are subsequently filled up to the surface 3 of the silicon body 1.
  • the grooves are filled with isolating material.
  • a comparatively thin layer 25 is deposited, shown as a single layer for clarity, which is composed of a layer of silicon oxide provided with a top layer of silicon nitride.
  • a thick layer of silicon oxide 26 is deposited.
  • a customary chemical-mechanical polishing treatment is carried out which stops, as shown in Fig. 11 , on the layer of silicon nitride 12 of the mask 9, 10.
  • an etching treatment is carried out wherein the layers 25 and 26 are etched until their free surface 27 is substantially flush with the surface 3 of the semiconductor body 1.
  • the removed part of the first layer of semiconductor material 8 is replaced with the base contacts 15 formed in the layer of in situ-doped non-monocrystalline silicon 14 on the surface 3. Also in this case, these base contacts 15 are directly contiguous to the part of the first layer of semiconductor material 8 covered by the mask 9, and also cover the filled grooves 24.
  • the above-described method is used to form the transistor shown in
  • the collector 22 of the transistor has lateral dimensions which are equal to those of the emitter 20 and the base 21, as a result of which a minimal capacitance is formed between base 21 and collector 22. Without the grooves, the collector 22 would extend to below the base contacts 15, as shown in Fig. 8, which are formed in the highly doped layer of non-monocrystalline silicon 14 and are connected with the base 21, as a result of which this capacitance could be comparatively large. A large capacitance between collector and base adversely affects the high-frequency properties of the transistor.
  • the grooves 24 are filled substantially up to the surface 3 of the silicon body 1. It is thus achieved that both the collector-base capacitance and the base resistance are minimal. If the grooves 24 were filled to a level below the surface 3 of the silicon body 1, then an edge of the collector region would border on the layer of non- monocrystalline silicon provided on the filled grooves, in which case the base resistance would be minimal, however, the collector-base capacitance would not be entirely minimal. If the grooves 24 were filled to a level above the surface 3, then an edge of the first layer of semiconductor material would not be in contact with the highly doped non-monocrystalline silicon layer provided on the filled grooves, in which case the collector-base capacitance would be minimal, however, the base resistance would not be entirely minimal.
  • the grooves 24 prior to being filled, the grooves 24 were provided with a layer of an isolating material 25 applied to their walls extending transversely to the surface 3 and to their bottom parts. Further, they were filled with isolating material 26.
  • the grooves 24 may alternatively be filled, however, with conductive material if their walls and bottom parts have been provided with a layer of an isolating material 25.
  • the grooves are provided, for example at the location of their walls and bottom parts, with a layer of silicon oxide and are further filled with a highly doped non-monocrystalline silicon, the conductive material is connected to the base 21 of the transistor via the non-monocrystalline material of the base contacts 15.
  • the mask 9, 10 is used, as shown in Fig. 15, after the removal of the part of the first layer of semiconductor material 8 that is not covered by the mask 9, 10, to etch grooves 28 in the surface layer 2 next to the mask 9, which grooves are subsequently filled up to the surface 3 of the silicon body 1.
  • the grooves 28 are formed in the surface layer 2 in such a manner that they extend into the highly doped contact layer 6 formed below the surface layer 2.
  • the grooves are provided in a customary manner with a layer of an isolating material 30, in this case an approximately 30 nm thick layer of silicon oxide, by depositing such a layer over the structure shown in Fig. 15 and subsequently removing this layer from surfaces extending parallel to the surface 3 by means of anisotropic etching.
  • the grooves 28 are filled, in this case, with a weakly conductive semiconductive material, such as intrinsically polycrystalline silicon.
  • a weakly conductive semiconductive material such as intrinsically polycrystalline silicon.
  • a planarizing etching treatment is carried out, in this case a customary mechanical-chemical polishing treatment followed by an anisotropic etching treatment, until the filled groove has a surface 32 which is substantially flush with the surface 3 of the semiconductor body 1.
  • the layer of non-monocrystalline silicon 14 is deposited and the base contacts 15 are formed. Also in this case, these base contacts 15 are directly contiguous to the part of the first layer of semiconductor material 8 covered by the mask 9 and also cover the filled grooves 28, the base contacts 15 electrically contacting the weakly conductive semiconductor material 31 in the grooves 28.
  • the transistor shown in Fig. 20 is formed in the same manner as described hereinabove.
  • the weakly conductive semiconductive material 31 provided in the grooves 28 is connected at the upper side, via the well-conducting base contacts 15 formed in the layer of non-monocrystalline silicon 15, to the base 21 of the transistor, and at the lower side to the buried contact layer 6, thus enabling the collector 22 to be contacted.
  • the voltage across the semiconductive material in the groove is equal to that between base 21 and collector 22.
  • 21 through 28 are diagrammatic, cross-sectional views of a few stages in the manufacture of a semiconductor device, wherein use is made of a further preferred embodiment of the method by means of which a transistor can be obtained which takes up a comparatively small part of the surface.
  • the grooves provided in the surface layer and filled with isolating material are formed such that they can be used as field isolation regions. Also in these Figures, the reference numerals used are the same as in the preceding Figures, whenever possible.
  • the first semiconductor layer 8 on which the masks 9 and 10 are provided is formed on the surface 3 of the silicon body 1.
  • the mask 9 is provided at the location of the transistor base 21 to be formed, the mask 10 is provided, in this example, at the location of the transistor contact region 7 to be formed.
  • grooves 33 are subsequently etched as shown in Fig. 22.
  • Fig. 22 As shown in Fig.
  • these grooves are filled, in the same manner as described hereinabove, with an isolating layer 25, in this case of silicon oxide with a top layer of silicon nitride, and isolating material 26, in this case silicon oxide.
  • the grooves 33 are formed such that they form field isolation regions 5, which isolate the active region 4 and the contact region 7 from each other. In this example, the grooves 33 are filled to a level just below the surface 3. As indicated hereinabove, a transistor with a minimal base resistance and minimal collector-base capacitance is obtained if the grooves 33 are filled exactly to the surface 3.
  • the layer of non-monocrystalline silicon 15 and the layer of silicon oxide 16 are formed, as described hereinabove, at the location of the etched away part of the first layer of semiconductor material 8.
  • the masks 9 and 10 are removed, resulting in the formation of the windows 17 and 34, respectively.
  • the window 17 is situated at the location of the base 21 to be formed of the transistor
  • the window 34 is situated at the location of the contact region 7 to be formed.
  • the second layer of semiconductor material 19 is deposited, after which the layers 15, 16 and 23, as shown in Fig. 28, are etched in accordance with a pattern.
  • the surface layer 2 is exposed, after which the contact region 7 is formed by ion implantation.
  • the transistor thus formed comprises emitter 20 which is contacted by the contact 23, base 21 contacted by the base contact 15, and collector 22 contacted by the contact region 7 and the buried layer 6.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Bipolar Transistors (AREA)

Abstract

Selon le procédé décrit de manufacture d'un dispositif semi-conducteur avec un transistor bipolaire, une première couche de matériau semi-conducteur (8) est formée sur la surface (3) d'un corps en silicium qui comprend une couche superficielle (2) d'un premier type de conductivité sur une couche de contact fortement dopée (6) du même premier type de conductivité, et la base (21) est formée sur la première couche de matériau semi-conducteur (8). Selon ce procédé, on forme un masque (9) sur la première couche de matériau semi-conducteur à l'endroit où la base à former est située, puis on décape successivement les parties non recouvertes de la première couche de matériau semi-conducteur et on les remplace par une couche de silicium polycristallin ou amorphe dopé. Ensuite, on enlève le masque de façon à former une fenêtre (17) à l'endroit de la base où une seconde couche de matériau semi-conducteur (19) du premier type de conductivité est déposée afin de former l'émetteur (20) du transistor. On forme ainsi un transistor dont la base est en contact avec un contact de base fortement conducteur (15) formé dans la couche de silicium polycristallin ou amorphe dopé.
PCT/IB2004/050497 2003-04-24 2004-04-23 Procede de manufacture d'un dispositif semi-conducteur avec un transistor bipolaire Ceased WO2004095564A1 (fr)

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EP03101144 2003-04-24
EP03101144.8 2003-04-24

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4338138A (en) * 1980-03-03 1982-07-06 International Business Machines Corporation Process for fabricating a bipolar transistor
EP0378794A1 (fr) * 1989-01-18 1990-07-25 International Business Machines Corporation Structure de transistor bipolaire vertical et procédé de fabrication
US5250448A (en) * 1990-01-31 1993-10-05 Kabushiki Kaisha Toshiba Method of fabricating a miniaturized heterojunction bipolar transistor

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Title
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