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WO2004088715A2 - Structure tronconique destinee a assurer le couplage entre un dispositif optique externe et un guide d'onde optique planaire et procede de formage associe - Google Patents

Structure tronconique destinee a assurer le couplage entre un dispositif optique externe et un guide d'onde optique planaire et procede de formage associe Download PDF

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Publication number
WO2004088715A2
WO2004088715A2 PCT/US2004/009086 US2004009086W WO2004088715A2 WO 2004088715 A2 WO2004088715 A2 WO 2004088715A2 US 2004009086 W US2004009086 W US 2004009086W WO 2004088715 A2 WO2004088715 A2 WO 2004088715A2
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WO
WIPO (PCT)
Prior art keywords
silicon substrate
silicon
optical
tapered
coupling
Prior art date
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Ceased
Application number
PCT/US2004/009086
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English (en)
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WO2004088715A3 (fr
Inventor
Vipulkumar Kantilal Patel
Prakash Gothoskar
Robert Keith Montgomery
Margaret Ghiron
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Lightwire LLC
Original Assignee
SiOptical Inc
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Publication date
Priority claimed from US10/775,872 external-priority patent/US6993225B2/en
Application filed by SiOptical Inc filed Critical SiOptical Inc
Publication of WO2004088715A2 publication Critical patent/WO2004088715A2/fr
Publication of WO2004088715A3 publication Critical patent/WO2004088715A3/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B6/122—Basic optical elements, e.g. light-guiding paths
    • G02B6/1228—Tapered waveguides, e.g. integrated spot-size transformers
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B6/13—Integrated optical circuits characterised by the manufacturing method
    • G02B6/136—Integrated optical circuits characterised by the manufacturing method by etching
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/26—Optical coupling means
    • G02B6/30—Optical coupling means for use between fibre and thin-film device
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B2006/12166—Manufacturing methods
    • G02B2006/12195—Tapering
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/26—Optical coupling means
    • G02B6/34—Optical coupling means utilising prism or grating
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements
    • G02B6/4201—Packages, e.g. shape, construction, internal or external details
    • G02B6/4204—Packages, e.g. shape, construction, internal or external details the coupling comprising intermediate optical elements, e.g. lenses, holograms
    • G02B6/4214—Packages, e.g. shape, construction, internal or external details the coupling comprising intermediate optical elements, e.g. lenses, holograms the intermediate optical element having redirecting reflective means, e.g. mirrors, prisms for deflecting the radiation from horizontal to down- or upward direction toward a device

Definitions

  • the present invention relates to the formation and utilization of a tapered coupling region between an external optical coupling device (such as a prism) and a planar optical waveguide, such as a waveguide formed in an upper silicon layer of a Silicon-On-Insulator (SOI) wafer structure.
  • an external optical coupling device such as a prism
  • a planar optical waveguide such as a waveguide formed in an upper silicon layer of a Silicon-On-Insulator (SOI) wafer structure.
  • SOI Silicon-On-Insulator
  • the light signal must be introduced to the silicon waveguide from an external source.
  • One conventional prior art arrangement for introducing light into a silicon waveguide is to use a separate laser or LED module emitting a free space beam, followed by optical elements to shape, focus and steer the light beam and/or adjust its polarization state.
  • a fiber-connected light source module can be used, where the coupling termination of the fiber is then followed by similar light coupling components to focus the light signal into the silicon waveguide.
  • While receiving elements may be incorporated in the silicon wafer as on-chip or integrated detectors, there are many applications where the user will need direct access to the optical signal after the on-chip functions have been performed. Thus, it is appropriate to provide an optical output port that would generally be a fiber-based termination, although the preferred embodiments do not exclude other output configurations.
  • a common prior art technique for coupling light from an external source to a silicon waveguide is to cleave end facets on both the waveguide and the mating fiber termination.
  • fiber terminations include, but are not limited to, multimode or single-mode fibers with small or zero cleave angles, and specially- shaped or lensed single-mode fibers that produce spot sizes as small as 1.5 ⁇ m.
  • the fiber termination is aligned to allow maximum light transmission through the waveguide, and then fixed in position.
  • Anti-reflection (AR) coatings can be used on both the fiber termination and the waveguide facet to reduce the Fresnel losses. Since input and output ports for devices must be located at edge facets of the waveguide- containing wafer die for this configuration, significant restrictions on device geometry (e.g., topology and/or size) are imposed by using this prior art edge coupling constraint.
  • edge coupling technique is effective if the mode-field diameter of the desired mode in the waveguide is similar to the spot size associated with the fiber termination, and if the numerical apertures (NAs) of the fiber termination and waveguide are well-matched.
  • silicon waveguides must be relatively thin, having a thickness of less than 0.35 ⁇ m (with a numerical aperture (NA) essentially equal to 1) to remain single- mode in the vertical direction and enable high-speed electronic applications.
  • NA numerical aperture
  • an input beam is incident upon an optical element of high-index material that is disposed in very close proximity to the waveguide of interest.
  • An exemplary arrangement of this technique is disclosed in an article entitled "Theory of Prism-Film Coupler and Thin-Film Light Guides", by P.K. Tien et al., appearing in the Journal of the Optical Society of America, Vol. 60, 1970, at pages 1325-1337.
  • very close proximity is intended to mean that the separation distance between the optical element and the waveguide permits evanescent coupling of light from the optical element to the waveguide.
  • the medium separating the optical element from the waveguide must have a refractive index that is lower than those associated with the optical element and waveguide materials.
  • the refractive index of the launch optical element must equal or exceed that of the waveguide material.
  • the optical element is frequently fabricated in the form of a prism. By varying the angle of incidence of the external beam on the angled facet of the prism, the beam inside the prism can be refracted at the desired angle. For this reason, the evanescent technique is generally referred to in the art as "prism coupling".
  • FIG. 1 illustrates one such exemplary prior art prism coupling arrangement, wherein in particular FIG. 1 illustrates an exemplary optical waveguide device 1 such as disclosed and claimed in US Patent 6,526,187, issued on February 25, 2003 and assigned to the same assignee as the present application.
  • an optical signal O passes through an input prism 2 and is thereafter coupled into a silicon optical waveguide layer 3, layer 3 being the upper silicon layer of a Silicon- On-Insulator (SOI) structure including a silicon substrate 4 and a buried oxide layer 5, layer 5 disposed between upper silicon waveguide layer 3 and silicon substrate 4, with layer 5 exhibiting a lower refractive index than silicon layers 3 and 4.
  • SOI Silicon- On-Insulator
  • a "gate” electrode 6 is disposed to cover the guided region above waveguide 3 between input prism 2 and an output prism 7.
  • An upper insulating layer 8 (also referred to as the "gate oxide” and exhibiting a relatively low refractive index) is disposed between gate electrode 6 and waveguide layer 3, and is used to maintain light guiding within waveguide layer 3. It has been found that as a voltage potential is applied to gate electrode 6, the distribution of free carriers (either holes or electrons) near the boundary between waveguide layer 3 and gate oxide 8 changes, actuating an optical action in waveguide layer 3 sufficient to support propagation of an optical signal (the distribution change illustrated by the shaded region in FIG. 1). The position and physical properties of prisms 2 and 7 are utilized to couple the light signal into and out of waveguide 3.
  • the prisms are sub-optimal in terms of the amount of light actually coupled into the waveguide when the evanescent coupling region has a substantially constant thickness. Additionally, the quality of the prism edge has been found to be directly related to the uniformity (or lack of uniformity) in the coupled signal.
  • a known method of addressing this prism-to-waveguide coupling problem is to utilize a layer (that is, an evanescent coupling layer) of graded thickness between the prism exit surface and the entry point of the waveguide.
  • a layer that is, an evanescent coupling layer
  • the shape of the output beam can be modified to improve the coupling into the silicon waveguide layer.
  • the present invention relates to the formation and utilization of a tapered coupling region between an external optical coupling device (such as a prism) and a planar optical waveguide, such as a waveguide formed in an upper silicon layer of a Silicon-On-Insulator (SOI) wafer structure.
  • an external optical coupling device such as a prism
  • a planar optical waveguide such as a waveguide formed in an upper silicon layer of a Silicon-On-Insulator (SOI) wafer structure.
  • SOI Silicon-On-Insulator
  • the formation of a tapered evanescent coupling region is based on using gray-scale lithography to obtain the controlled slope and dimensional accuracy required for forming the desired tapered region for providing efficient coupling between external optics and a relatively thin silicon optical waveguide layer in an SOI wafer.
  • a tapered region of low refractive index material e.g., an oxide
  • a tapered region of low refractive index material is formed along a first major surface of a silicon substrate, with the opposing major surface processed using masks and etching techniques to form angled surfaces appropriate for coupling a free space optical signal into the evanescent coupling region.
  • cavity regions may also be formed in the coupling substrate to prevent the premature re-entry of light from the optical waveguide into the coupling substrate.
  • the coupling surfaces and tapered evanescent coupling region are formed on the same major surface of an optical substrate, leaving the opposing substrate free for formation of other useful optical components (e.g., transmissive and/or reflective optical components).
  • While the present invention, as described hereinbelow, is directed to the construction and utilization of a silicon-based wafer containing a tapered evanescent coupling region as particularly used with an SOI wafer, it is to be understood that similar silicon-based devices in die or wafer form can be attached in the same manner to wafers that include waveguides formed from any material that has a lower refractive index than silicon.
  • Some exemplary waveguide materials include, but are not limited to, indium phosphide (refractive index of approximately 3.2 at a wavelength of 1550 nm) and lithium niobate (refractive index of approximately 2.1 - 2.2 at a wavelength of 1550 nm). While such device wafers cannot be manufactured with standard silicon processing techniques or features, applications for these wafers may still benefit from the inventive tapered coupling region processing and attachment technique.
  • FIG. 1 illustrates an exemplary prior art prism coupling arrangement
  • FIG. 2 shows, in a cut-away partial view, an exemplary arrangement utilizing a tapered evanescent coupling region formed in accordance with the present invention
  • FIG. 3 contains both diagrams illustrating exemplary evanescent coupling layer thickness profiles and the accompanying beam profiles for an optical signal passing therethrough;
  • FIGs. 4 - 10 illustrate a first sequence of processing steps used to form the exemplary arrangement of FIG. 2, particularly illustrating the formation of a tapered evanescent coupling region and pyramidal optical coupling facets;
  • FIGs. 11 - 15 illustrate an alternative set of processing steps, used to form a tapered evanescent coupling region and associate V-groove optical coupling structure
  • FIGs. 19-23 illustrate yet another set of processing steps of the present invention, in this case for forming both a tapered evanescent coupling region and optical coupling facet through the same major surface of a silicon substrate;
  • FIGs. 24 and 25 illustrate an alternative to the process illustrated in FIGs. 19- 23 where an additional reflective optical element is disposed on the opposing major surface;
  • FIGs. 26-29 illustrate another processing sequence of the present invention, using a transmissive optical element to directly steer an incoming optical beam into the tapered evanescent coupling region without the need for a separate optical coupling facet.
  • FIG. 2 illustrates, in a cut-away partial view, an exemplary arrangement 10 of the present invention utilizing a tapered evanescent coupling region 12 disposed between an external optical coupling element 14 (in this case, a prism) and a relatively thin silicon optical waveguide layer 16.
  • silicon waveguide layer 16 is formed as part of an SOI structure, the SOI structure further comprising a silicon substrate 18 and buried oxide layer 20.
  • buried oxide layer 20 is disposed between the relatively thin upper silicon optical waveguide layer 16 and silicon substrate 18.
  • a light beam I is introduced from an external source (not shown) and impinges an input coupling facet 22 of input prism 14. The light beam is thereafter refracted at the proper angle through prism 14, passes through tapered evanescent coupling region 12 and enters silicon optical waveguide layer 16.
  • tapered evanescent coupling region 12 separating prism 14 from silicon optical waveguide layer 16 must have a refractive index that is lower than those associated with either prism 14 or waveguide layer 16. Additionally, the refractive index of input coupling prism 14 must equal or exceed the refractive index of silicon optical waveguide layer 16. In order to efficiently couple light from prism 14 to waveguide layer 16 for a specific input light beam wavelength and thickness of waveguide layer 16, the light beam must be incident on waveguide layer 16 at a specific angle of incidence. Thus, a prism is often used as the input coupling device so as to achieve this particular angle.
  • tapered evanescent coupling region 12 has been found to improve the coupling efficiency as compared with an evanescent coupling region of substantially constant thickness.
  • the use of a tapered coupling region eliminates the requirement of exact gap spacing, as well as eliminating the need for making a high quality edge on an inner surface of prism 14 to truncate the beam.
  • the middle section of tapered coupling region 12 maintains a thickness large enough to avoid the coupling of light from the underlying silicon waveguide layer 16 back into prism 14.
  • the third section of tapered coupling region 12, denoted as 12C is formed in accordance with the present invention to exhibit a decreasing taper, thus allowing the optical signal propagating along waveguide layer 16 to be evanescently coupled through section 12C and into an output coupling prism 24, exiting along an output facet 26 of output coupling prism 24.
  • FIG. 3 contains exemplary evanescent coupling layer thickness profiles for sections 12A and 12C, and illustrates exemplary beam profiles associated with these 5 tapered input (12A) and output (12C) regions of evanescent coupling layer 12.
  • the first light exiting from output prism 24 should be fairly weakly coupled, so that most of light remains in waveguide layer 16.
  • the thickness of evanescent coupling layer 12C should be well above the value required
  • the formation of a tapered coupling region is based on using gray-scale lithography to obtain the controlled slope and
  • FIGs. 4-10 illustrate a first process of the present invention used to form a tapered evanescent coupling region to facilitate light coupling between external coupling elements (e.g., prism couplers) and a relatively thin silicon optical waveguide layer formed within an SOI structure.
  • external coupling elements e.g., prism couplers
  • the tapered coupling region is formed as part of the prism coupler.
  • An alternative embodiment, wherein joining of the tapered evanescent coupling region to the waveguide in the SOI wafer will be discussed hereinafter.
  • FIG. 4 illustrates an initial step in the fabrication process, which comprises the selection of a silicon substrate 50 as the material for the final prism structure.
  • silicon substrate 50 is chosen to have a dopant species and concentration such that the refractive index of the final prism wafer is at least equal to that of the silicon optical 5 waveguide in the final structure (see FIG. 10 for a depiction of the silicon optical waveguide).
  • the thickness of substrate 50 is selected to provide for fabrication of a prism coupler with a desired height.
  • a specific prism design based on industry standard wafer thickness (i.e., 625 ⁇ m ⁇ 25 ⁇ m for a typical six-inch diameter wafer), will result in significant cost reduction.
  • substrate 50 In processing, substrate 50
  • substrate 50 is subjected to a double polishing process such that its top major surface 52 and bottom major surface 54 are both
  • photosensitive layer 56 is deposited over top major surface 52 of substrate 50.
  • Commercially available photoresist materials used in the semiconductor industry are exemplary materials that may be used for this process.
  • layer 56 is exposed using a gray-scale lithography mask and
  • Gray-scale lithography utilizes locally modulated exposure doses to multiple depths of the exposed photoresist (or any other photosensitive material) across the substrate surface. This is due to ultraviolet light being absorbed by the photoactive compound as it travels through the depth of the photoresist, where the thickness of the
  • tapered photoresist region 56 ⁇ may be used in the process of the present invention, such as laser beam direct-write lithography or e-beam direct-write lithography, both well-known practices in the semiconductor processing art, albeit more expensive and time-consuming than the batch capabilities of gray-scale photolithography.
  • FIG. 5 illustrates substrate 50 5 at the completion of this process, where top major surface 52 of substrate 50 has been processed to include a tapered region 52 ⁇ .
  • One exemplary method that may be used to transfer the desired evanescent coupling region profile into substrate 50 is to etch resist layer 56 with an etchant(s) appropriate to transfer the exact profile of the taper, that is an etchant that exhibits the same removal rate for the resist material and for
  • the etching process will create an identical reverse tapered shape within top major surface 52 of silicon substrate 50.
  • the removal process will create features that are approximately five times shallower in the silicon surface as compared with the
  • FIG. 6 illustrates the next step in the fabrication process, which is related to "filling" tapered silicon region 52 ⁇ with the material chosen for use as the evanescent coupling region. As discussed above, the material used for the evanescent coupling
  • a relatively simple oxidation process can be applied to etched substrate 50 so as form an oxide layer 58 that will "fill” tapered region 52 ⁇ so as to form a dielectric tapered region 58 ⁇ , as well as cover the remaining top major surface 52 of silicon substrate 50
  • CVD chemical vapor deposition
  • VAD plasma-assisted vapor deposition
  • PVD physical vapor deposition
  • a polishing process such as chemical-mechanical polishing (CMP) can then be used to remove all of the dielectric material outside of filled tapered region 58 ⁇ , resulting in the structure as shown in FIG. 7.
  • CMP chemical-mechanical polishing
  • a first 5 step in an exemplary process of forming the desired prism coupler requires the formation of a patterned etch layer 60 on bottom major surface 54 of substrate 50, as shown in FIG. 7.
  • a wet chemical etching process can then be used to complete etch through silicon substrate 50, forming angled surfaces as shown in FIG. 8. For example, with a ⁇ 100>-oriented wafer, as discussed above, wet etching processes
  • RIE reactive ion etch
  • FIG. 9 illustrates the next step in the process, where substrate 50 is rotated such that top major surface 52 is disposed underneath bottom major surface 54. It is
  • an input prism coupler 62 that advantageously includes a tapered evanescent coupling region 58 ⁇ , in accordance with the present invention.
  • a layer of anti-reflective material 64 such as silicon nitride, may be formed to cover the exposed surfaces of
  • substrate 50 may be joined to a second substrate, such as an SOI wafer 70 illustrated in FIG. 9, where SOI wafer 70 has been processed to comprise a silicon substrate 72, buried oxide layer 74 and a relatively thin silicon optical waveguide layer 76.
  • SOI wafer 70 has been processed to comprise a silicon substrate 72, buried oxide layer 74 and a relatively thin silicon optical waveguide layer 76.
  • substrate 50 is joined to SOI wafer 70 such that tapered evanescent coupling region 58 ⁇ contacts relatively thin silicon optical waveguide layer 76.
  • FIG. 10 illustrates the final structure, where an input optical signal O will pass through input facet 68 of input prism coupler 64 (the angled surface of facet 68 being properly formed through the wet chemical etch process discussed
  • FIGs. 11-15 illustrate a set of processing steps associated with an alternative embodiment of the present invention, utilizing a V-groove structure formed in 5 opposition to a tapered evanescent coupling region to provide coupling from an external signal source into the tapered evanescent coupling region.
  • the same processing steps as illustrated in FIGs. 4-7 are used to form tapered evanescent coupling region 58 ⁇ in coupling substrate 50.
  • a V-groove coupling element is then formed, as illustrated in the
  • a patterned mask layer 80 is formed ⁇ across bottom major surface 54 of substrate 50, delineating an opening 82 through which a V-groove (used for coupling) will be formed.
  • the location of opening 82 is carefully chosen to align with tapered evanescent coupling region 58 ⁇ so that an optical signal passing through the formed
  • V-groove-type input/output coupling surfaces are formed by performing an anisotropic wet chemical etch on bottom major surface 54 of substrate 50, resulting in the structure as illustrated in FIG. 12, which contains an exemplary V- groove 84.
  • An AR coating 86 may then be formed to completely cover bottom major
  • FIG. 13 The next step in this process embodiment is illustrated in FIG. 13, where tapered evanescent coupling region 58 ⁇ is used as an etch mask and top major surface 52 of substrate 50 is etched to form cavity regions 88.
  • a lithography- based mask can be used to define cavity region(s) 88.
  • Cavity region 88 is utilized, as
  • substrate 50 is rotated and joined to an SOI wafer 90, wafer 90 comprising a silicon substrate 92, a buried oxide layer 94 and a relatively
  • FIG. 14 illustrates, in an exploded view, the joining of coupling substrate 50 to SOI wafer 90, where FIG. 15 illustrates the final structure.
  • an input optical signal from an external source (not shown) will impinge an angled surface 98 of V-groove 84, angled surface 98 thus functioning as an input facet.
  • the optical signal thereafter passes through substrate 50 and enters tapered evanescent coupling region 58 ⁇ , where as before tapered evanescent coupling region 58 ⁇ functions to efficiently couple the optical signal into silicon optical waveguide layer 96 of SOI wafer 90.
  • cavity region 88 in accordance with the present invention, is disposed above the portion of silicon 5 optical waveguide layer 96 supporting the propagation of an optical signal so as to prevent the coupling of the optical signal back into coupling substrate 50 (since the refractive index of air is greater than that of silicon).
  • the cavity regions in coupling substrate 50 may be formed using other processes, such as reactive ion etching (RIE), plasma etching, ion milling, or any
  • FIG. 16 illustrates an alternative process step (in comparison with FIG. 13) where reactive ion etching is used to form cavity regions 100 in coupling substrate 50.
  • sidewalls 102 of cavity regions 100 in the embodiment of FIG. 16 are essentially vertical, as compared to the
  • substrate 50 is joined to an exemplary SOI wafer 110 including a silicon substrate 112, buried oxide layer 114 and silicon optical waveguide layer 116, as shown in FIG. 17.
  • SOI wafer 110 including a silicon substrate 112, buried oxide layer 114 and silicon optical waveguide layer 116, as shown in FIG. 17.
  • coupling substrate 50 is inverted prior to joining such that tapered evanescent
  • FIG. 18 illustrates the joined structure formed in accordance with this embodiment of the present invention, illustrating the propagation of an external optical signal O through input facet 98 of V-groove 84 of coupling substrate 50 and into tapered evanescent coupling region 58 ⁇ . Thereafter, the optical
  • 25 signal O is evanescently coupled into silicon optical waveguide layer 116, where the presence of RIE-formed cavity region 100 prevents any of the optical signal from coupling back into coupling substrate 50 (since the refractive index of the air within cavity region 100 is greater than the refractive index of silicon substrate 50).
  • Such an embodiment is considered to be a major advantage for performing conventional, gray-scale or nano-imprint photolithographic pattern transfer techniques 5 in combination with the etch processes that are commonly used in the fabrication of silicon-based micro-optical components, where various ones of these micro-optical components can thus be formed on this un-used wafer surface.
  • micro- optical components such as lenses, gratings, mirrors and sub-wavelength diffractive optical elements can be realized in precise locations in the optical path on this major
  • FIGs. 19-23 illustrate an exemplary process of the present invention that may be used to form both an optical coupling surface and tapered evanescent coupling region through the same major surface of an optical coupling substrate.
  • optical coupling substrate 50 as described above, is illustrated with tapered evanescent coupling region 58 ⁇ formed as described above in FIGs. 4-7.
  • a patterned etch mask 120 is disposed over top major surface 52 of coupling substrate 50 so as to protect tapered evanescent coupling 0 region 58 ⁇ and expose a first portion 122 of top major surface 52 where an optical coupling surface is to be formed.
  • mask 120 may be patterned to delineate a second portion 124 of top major surface 52 where a cavity region (for blocking an optical signal) can be formed.
  • a wet chemical anisotropic etch is used to remove the substrate material, thus forming the structure as 5 illustrated in FIG. 20.
  • a silicon wafer with a ⁇ 100> crystal plane orientation is used to form optical coupling substrate 50, such that with a KOH- type conventional wet chemical etch, surfaces at an angle of 54.7° are formed with respect to surface 52.
  • other angles may be achieved by selecting silicon wafers with a different crystallographic orientation.
  • Gray-scale lithography and 0 etching can also be used to form input/output coupling facets at a desired angle in silicon wafers with these different orientations.
  • FIG. 20 illustrates optical coupling substrate 50 including tapered evanescent coupling region 58 ⁇ and a pyramidal opening formed from the wet chemical etch process to provide an angled optical reflecting surface 126, where in this example surface 126 fo ⁇ ns an angle of 54.7° with respect to top major surface 52.
  • angled reflecting surface 126 is used for re-directing an optical input signal into tapered evanescent coupling region 58 ⁇ .
  • a cavity region 128 may 5 also formed in the structure during the same wet chemical etch process, as shown in FIG. 20, that will be used to aid in maintaining the propagation of an optical signal in a silicon optical waveguide layer, as discussed below.
  • a transmissive optical element 130 (such as, for example, a lens or diffractive optical element) may be
  • optical coupling substrate 50 is re-oriented such that "top" major surface 52, including both tapered evanescent coupling region 58 ⁇ and optical reflecting surface 126 is disposed underneath "bottom” major surface 54.
  • FIG. 22 illustrates the next step in this embodiment of the present invention
  • optical coupling substrate 50 including transmissive optical element 130 is coupled to an SOI wafer 140 comprising a silicon substrate 142, a buried oxide layer 144 and a surface silicon optical waveguide layer 146.
  • SOI wafer 140 comprising a silicon substrate 142, a buried oxide layer 144 and a surface silicon optical waveguide layer 146.
  • optical coupling substrate 50 is disposed over and joined to silicon optical waveguide layer 146 of SOI wafer 140.
  • FIG. 23 illustrates the final arrangement formed using this
  • an optical input signal passes through transmissive optical element 130 and is thereafter focused onto surface 126.
  • the optical signal will reflect off of surface 126, and thereafter be directed into tapered evanescent coupling region 58 ⁇ . If .
  • an additional optical reflective coating 127 may be formed on the exposed region of surface 126 to improve the reflection efficiency of this embodiment.
  • the optical signal present in tapered evanescent coupling region 58 ⁇ will then be coupled into optical waveguide layer 146 and propagate therealong.
  • the presence of cavity region 128 above optical waveguide layer 146 will block the re-entry of the optical signal into substrate 50 and aid in maintaining the propagation of the signal along waveguide 146.
  • FIGs. 24 and 25 illustrate an alternative to the process illustrated in FIGs. 19- 23, where an additional reflective optical element 132 is disposed on major surface 54 of optical coupling substrate.
  • optical substrate 50 is shown as including both transmissive optical element 130 (such as a lens) and a reflective optical element 132 (such as a mirrored surface), thus providing an internal reflection of the optical signal prior to the signal reaching tapered evanescent coupling region 58 ⁇ .
  • FIG. 25 illustrates the complete arrangement, illustrating the joining of optical coupling substrate 50 and SOI wafer 140. Referring to FIG. 25, it is shown how an input optical signal O passes through transmissive optical element 130, reflects off of angled surface 126 and then impinges reflective optical element 132. The reflected optical signal is then directed into tapered evanescent coupling region 58 ⁇ at a desired angle determined to be optimum for coupling light into an underlying silicon optical waveguide layer 146.
  • FIGs. 26-29 illustrate yet another processing embodiment of the present invention, again utilizing the processing steps of FIGs. 4-7 to form optical coupling substrate 50 including tapered evanescent coupling region 58 ⁇ .
  • a transmissive optical element is utilized, as illustrated below, to steer the incoming optical signal directly into tapered evanescent coupling region 58 ⁇ .
  • an optical grating may be written into bottom major surface 54.
  • the process begins with optical coupling substrate 50 and tapered evanescent coupling region 58 ⁇ formed as discussed above with FIGs. 4-7.
  • a mask 150 is deposited on top major surface 52 of substrate 50 to cover and protect tapered evanescent coupling region 58 ⁇ .
  • cavity regions 152 are used to block the re-coupling of the propagating optical signal back into substrate 50 from the silicon optical waveguide layer of the SOI wafer.
  • FIG. 28 illustrates the next step in this particular process, where substrate 50 is inverted and a beam steering transmissive optical element 154 is disposed at a predetermined location along bottom major surface 54 of substrate 50.
  • the final device structure is illustrated in FIG. 29, which illustrates the re-direction of an input optical signal O by beam steering transmissive optical element 154 into tapered evanescent coupling region 58 ⁇ .
  • bonding process may be used.
  • the use of a low temperature process permits the incorporation of device structures within the SOI wafer that cannot withstand elevated temperatures.
  • One exemplary process uses chemically activated surfaces on both the optical coupling substrate and SOI wafer, allowing for low temperature bonding at a relatively moderate applied pressure. The bonding chemistry must be compatible
  • the materials used in the SOI wafer and coupling substrate include, but are not limited to, compatibility with various integrated circuit metallization systems and/or AR coating materials. Regardless of the materials or processes used to attach the optical coupling substrate to the SOI wafer, the actual attachment must be sufficient to withstand dicing/sawing operations used to separate the various
  • the attachment process should not cause any electrostatic damage to any active components on the SOI wafer.
  • Another advantage of the semiconductor-based bonding process is the alignment accuracy that can be achieved between the two bonded substrates using integrated circuit manufacturing infrastructures. For example, alignment accuracies better than ⁇ l ⁇ m
  • both the coupling substrate and SOI wafer will include alignment features, as well-known and used in the art, to perform the alignment required for the intended application.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Optical Integrated Circuits (AREA)
  • Optical Couplings Of Light Guides (AREA)

Abstract

L'invention concerne des procédés de formage d'une zone de couplage évanescent tronconique pouvant être utilisée avec un guide d'onde optique en silicium relativement mince, par exemple une structure à silicium sur isolant (SOI). Une zone de couplage évanescent tronconique est formée sur un substrat en silicium servant de substrat de couplage, ce dernier adhérant ensuite à la structure à SOI. Un procédé de photolithographie à échelle de gris permet de définir une zone tronconique en résine photosensible, le motif tronconique étant par la suite transféré dans le substrat en silicium. On utilise alors un matériau présentant un indice de réfraction inférieur à celui de la couche d'un guide d'onde optique en silicium (par exemple, la silice) pour remplir l'ouverture tronconique dans le substrat. On peut utilise avec intérêt les étapes de traitement du silicium classique pour former des facettes de couplage dans le substrat en silicium (c'est-à-dire des surfaces angulaires, des rainures en V) dans une relation appropriée avec la zone de couplage évanescent tronconique. Les facettes de couplage peuvent être formées contiguës avec une zone de couplage évanescent tronconique ou à travers le côté opposé du substrat en silicium.
PCT/US2004/009086 2003-03-28 2004-03-25 Structure tronconique destinee a assurer le couplage entre un dispositif optique externe et un guide d'onde optique planaire et procede de formage associe Ceased WO2004088715A2 (fr)

Applications Claiming Priority (4)

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US45850303P 2003-03-28 2003-03-28
US60/458,503 2003-03-28
US10/775,872 US6993225B2 (en) 2004-02-10 2004-02-10 Tapered structure for providing coupling between external optical device and planar optical waveguide and method of forming the same
US10/775,872 2004-02-10

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1850160A1 (fr) * 2006-04-26 2007-10-31 Honeywell International Inc. Structure de couplage optique
JP2017102312A (ja) * 2015-12-03 2017-06-08 新光電気工業株式会社 光導波路及びその製造方法と光導波路装置
US10215924B2 (en) 2016-12-22 2019-02-26 Imec Vzw Optical interconnect with high alignment tolerance
CN118472138A (zh) * 2024-06-26 2024-08-09 扬州中科半导体照明有限公司 能够调控出光面光束形貌的发光二极管的制作方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4220135A1 (de) * 1992-06-15 1993-12-16 Bosch Gmbh Robert Verfahren zum Ankoppeln von Photoelementen an integriert-optische Schaltungen in Polymertechnologie
US5515464A (en) * 1992-07-06 1996-05-07 Sheem Sang K Optical fiber interconnections using self-aligned core-extensions
JPH09153638A (ja) * 1995-11-30 1997-06-10 Nec Corp 導波路型半導体受光装置およびその製造方法
US6760529B2 (en) * 2001-12-11 2004-07-06 Intel Corporation Three-dimensional tapered optical waveguides and methods of manufacture thereof

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1850160A1 (fr) * 2006-04-26 2007-10-31 Honeywell International Inc. Structure de couplage optique
US7454102B2 (en) 2006-04-26 2008-11-18 Honeywell International Inc. Optical coupling structure
JP2017102312A (ja) * 2015-12-03 2017-06-08 新光電気工業株式会社 光導波路及びその製造方法と光導波路装置
US10215924B2 (en) 2016-12-22 2019-02-26 Imec Vzw Optical interconnect with high alignment tolerance
CN118472138A (zh) * 2024-06-26 2024-08-09 扬州中科半导体照明有限公司 能够调控出光面光束形貌的发光二极管的制作方法

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