WO2004068689A1 - Rectifier circuit, circuit arrangement and method for producing a rectifier circuit - Google Patents

Abstract

The invention relates to a rectifier circuit (500), a circuit arrangement and a method for producing a rectifier circuit. The rectifier circuit for providing a rectified voltage contains a first (505) and a second (506) field effect transistor. The first source/drain terminal (505a) of the field effect transistor is coupled to a gate terminal (506c) of the second field effect transistor. The first source/drain terminal (506a) of the second field effect transistor is coupled to a gate terminal (505c) of the first field effect transistor. A second source/drain terminal (505b) of the first field effect transistor is coupled to a second source/drain terminal (506b) of the second field effect transistor.

Description

description

Rectifier circuit, circuit arrangement and method for producing a rectifier circuit

The invention relates to a rectifier circuit, a circuit arrangement and a method for producing a rectifier circuit.

In an application with contactless electronic

Functionality such as a contactless chip card or a contactless identification data carrier (so-called "ID tag"), the electrical energy required for the operation of an associated circuit is often transmitted using an alternating electromagnetic field, which is usually coupled into a circuit by means of an antenna , Such an antenna can be a coil, for example, if the energy is transmitted inductively.

Since a DC voltage is usually required for the operation of a circuit, the signal tapped at the output of the antenna (for example a current or a voltage) must first be rectified and then optionally smoothed and stabilized. A rectifier circuit is particularly required for this.

A circuit in polymer electronics, in particular using polymer transistors, is of interest for mass application in the area of an ID tag. Such should be able to be formed for further cost reduction, if possible, using a printing process.

In polymer electronics technology is a pn diode or a diode with a similar performance and

Characteristics as provided in silicon microelectronics are not available. Another The basic condition in polymer electronics can be that there is only a so-called single-channel technology, which means that either only n-MOS or only p-MOS transistors are available. Furthermore, such a component can be a so-called normally-on component, which in the

Circuit technology is usually less favorable than a corresponding normally-off component.

A polymer transistor 100 according to the prior art is shown in FIG.

The polymer transistor 100 has a substrate 101 on which a gate electrode 102 is formed. A gate dielectric 103 is formed on the gate electrode 102. Furthermore, first and second source / drain connections 104, 105 are provided on left and right edge regions of the gate insulating layer 103. A channel region 106 is formed between the two source / drain connections 104, 105. Some of the components of the polymer transistor 100 are made of polymer material.

FIG. 2 shows a diagram 200 in which the nomenclature of a normally-on component or a normally-off component used in the context of this description and the figures is defined as an n-MOS or p-MOS transistor becomes.

A normally-on transistor is a transistor of the self-conducting type or of the depletion type _/ which already has an electrically conductive channel at a gate-source voltage of OVolt. In contrast to this, in the case of a normally-off transistor, that is to say in the case of a normally-off transistor or a transistor of the enhancement type, the channel region is only applied when an electrical voltage other than zero is applied to the gate region brought an electrically conductive state. A standard bridge rectifier circuit known from the prior art for rectifying an input AC voltage Vm is described below with reference to FIG. 3A.

The rectifier circuit 300 has one

AC voltage source 301 and interconnected first to fourth diodes 302 to 305. A first connection of the AC voltage source 301 is coupled to a first connection of the first diode 302, the second connection of which is coupled to a first connection of the fourth diode 304 and to a first DC voltage output connection 306. Furthermore, the first connection of the AC voltage source 301 is coupled to a first connection of the second diode 303, the second connection of which is coupled to a first connection of the fourth diode 305 and to a second DC voltage output connection 307. A second connection of the AC voltage source 301 is with the second connection of the third diode 304 and with the second connection of the fourth

Diode 305 coupled. Between the DC output terminals 306, 307 is provided uτ due to the functionality of the rectifier circuit 300, a generated from the AC voltage V _ιN DC voltage V _0th Furthermore, a filter capacitor 308 is provided between the connections 306, 307 for smoothing the rectified output voltage.

FIG. 3B shows a diagram 310, along the abscissa 311 of which the voltage V _TD between the two connections of one of the diodes 302 to 305 is shown, and on the ordinate 312 of which the associated electrical current I _TD . which flows through the respective diode 302 to 305, is plotted. The course of a typical current-voltage characteristic curve of a semiconductor diode from a pn junction is thus sketched in FIG. 3B. In a first approximation, the diode blocks if a voltage is applied that is less than one Threshold voltage V _t a of the diode. If a voltage is applied above this threshold voltage, the electrical current increases with steepness and with increasing voltage.

3C shows a rectifier circuit 320 according to the prior art, which differs from the rectifier circuit 300 essentially in that the first to fourth diodes 302 to 305 by first to fourth normally-off n-MOS field-effect transistors 321 to 324 are replaced, which are connected in a diode circuit. This means that in each of the field effect transistors 321 to 324, the gate region is coupled to a respective one of the source / drain regions.

In the example shown in figure 3D graph 330, the voltage V _TR (drain region compared to the non-coupled with the gate region of source /) is plotted along the abscissa 331 at ^'the gate region applied to the normally-off transistors 321 to 324, and along an ordinate 332, the current I _R through the channel region of one of the normally-off n-MOS transistors 321 to 324. A current flow only begins when the voltage is greater than a threshold voltage V _{tn of} the respective n-MOS field-effect transistor. As shown in FIG. 3D, the slope of the characteristic curve of an n-MOS field-effect transistor is usually significantly lower (that is to say with the same area consumption of the circuit elements used) than when using a pn diode (see FIG. 3B).

The rectifier circuit 340 shown in FIG. 3Ξ differs from the rectifier circuit 320 in that, instead of the first to fourth n-MOS field effect transistors 321 to 324, first to fourth p-MOS field effect transistors 341 to 344 of the normally-off type are used are. A current-voltage characteristic of this p-MOS field effect transistors shown in the diagram 350 of Fig.3F along the abscissa 351, the voltage at the gate terminal of the respective one of the p-MOS field effect transistors 341-344 and to ^'the ordinate 352 the corresponding current is applied through the channel. The transistors 341 to 344 are in turn connected in diode circuits (that is to say a short circuit between the gate connection and one of the source / drain connections). The current-voltage characteristic of a normally-off p-MOS transistor in a diode circuit, as shown in FIG. 3F, also shows a threshold voltage V _{tp of} the corresponding p-MOS transistors.

3G shows a rectifier circuit 360 according to the prior art, in which the

AC voltage source 301 from FIG. 3A is replaced by a coil 361 as an antenna, into which an AC voltage can be coupled electromagnetically. In other words, the circuit diagram from FIG. 3G results in a contactless application when using pn diodes in the rectifier circuit.

A diagram 400 is described below with reference to FIG. 4A, which shows a current-voltage characteristic curve of a normally-on n-MOS transistor in a diode circuit. The voltage between the two source / drain connections of the field effect transistor is plotted along the abscissa 401 of the diagram 400, whereas the current is plotted along one of the two source / drain connections along the ordinate 402. As diagram 400 shows, the use of a normally-on n-MOS field effect transistor does not result in a sufficiently good blocking behavior.

A similar statement applies to the use of a self-conducting p-MOS transistor, the current-voltage characteristic of which is shown in diagram 410 from FIG. 4B. The voltage is again along the abscissa 411 of diagram 410 between the two source / drain connections, along the ordinate 412, the current is applied to a source / drain connection of the self-conducting p-MOS field-effect transistor.

It is in principle possible to form a rectifier circuit from a normally-on n-MOS transistor (see FIG. 4A) or a normally-on p-MOS transistor (see FIG. 4B) (for example in a circuit as shown in FIG. 3C or FIG. 3E), but such a rectifier circuit would be subject to considerable losses, in particular because of the inadequate blocking behavior of self-conducting transistors. This is intolerable, especially in low-power and contactless applications.

The invention is therefore based on the problem of a

To create the possibility to provide a rectifier circuit that is also suitable when using self-conducting transistors or for contactless applications.

The problem is solved by a rectifier circuit, by a circuit arrangement and by a method for producing a rectifier circuit with the features according to the independent patent claims.

The rectifier circuit according to the invention for

Providing a rectified voltage has a first and a second field effect transistor. The first and the second field effect transistor each have a first source / drain connection, for applying an alternating voltage between the first source / drain

Connections that are set up in such a way that the electrical potentials at the first source / drain connections of the field effect transistors have a different sign with respect to a reference potential. The first source / drain of the first

Field effect transistor is coupled to the gate terminal of the second field effect transistor, and the first source / drain Connection of the second field effect transistor is coupled to the gate connection of the first field effect transistor. Furthermore, a second source / drain connection of the first field effect transistor is coupled to a second source / drain connection of the second field effect transistor.

In addition, the invention provides a circuit arrangement with a substrate and a rectifier circuit formed on and / or in the substrate with the features mentioned above.

Furthermore, a method for producing a rectifier circuit for providing a rectified voltage is provided according to the invention, a first and a second field effect transistor being formed according to the method. In addition, a first source / drain connection of the first and the second field effect transistor is set up to apply an AC voltage between the first source / drain connections, which is set up in such a way that the electrical potentials at the first source / drain Connections of the field effect transistors have different signs with respect to one another with respect to a reference potential. The first source / drain connection of the first field effect transistor is coupled to the gate connection of the second field effect transistor. Furthermore, the first source / drain connection of the second field effect transistor is coupled to the gate connection of the first field effect transistor. A second source / drain connection of the first field effect transistor is coupled to a second source / drain connection of the first field effect transistor.

According to the invention, a circuit architecture for a rectifier circuit is clearly created, which, even when using self-conducting transistors, overcomes the disadvantages of a high level of loss known from the prior art. Through the interconnection of a AC voltage source (for example an inductor) and two transistors interconnected in a crosswise manner, a sufficiently rectified voltage which can be predetermined or selected as desired can be generated with a simple and inexpensive circuit architecture.

The transistors are clearly operated as three-terminal components, not as second-terminal components such as the transistors connected in a diode circuit in FIGS. 3C and 3E.

When the AC voltage source is implemented as an antenna or coil, the rectifier circuit according to the invention is an inexpensive, efficient and inexpensive option, particularly for contactless applications or for low-cost applications in polymer electronics, of providing a DC voltage required for the operation of a functional circuit ,

Since the rectifier circuit according to the invention is not limited to the use of field effect transistors of a certain type, a DC voltage of the desired sign (i.e. a positive or negative DC voltage) can be generated. Furthermore, the rectifier circuit according to the invention can be flexibly implemented according to the needs of the individual case with p-MOS transistors and / or n-MOS transistors, normally-on transistors and / or normally-off transistors.

The rectifier circuit according to the invention is of interest for the most diverse areas of circuit technology, in particular for polymer electronics or silicon microelectronics.

Preferred developments of the inventions result from the dependent patent claims. At least one of the field effect transistors is preferably self-conducting and / or at least one of the field effect transistors is self-blocking.

At least one of the field effect transistors may be a p-type transistor. If only field-effect transistors of the p-line type are available in a circuit architecture (for example in polymer electronics), this is sufficient to implement the rectifier circuit. Alternatively, at least one of the field effect transistors can also be of the n-type conduction.

At least one of the field effect transistors can be a polymer field effect transistor, a silicon-on-insulator (SOI).

Field effect transistor, a bulk silicon field effect transistor, a junction FET (JFET), a fin FET or a double gate field effect transistor.

The alternating voltage can be

Elements can be provided, which is preferably an antenna, a coil or an AC voltage source.

If a coil is used as an AC voltage element, it can be provided with a center tap on which the electrical reference potential can be provided. For example, the center tap of the coil can be placed on the electrical ground potential.

The rectifier circuit according to the invention can

Provision of a second rectified voltage, in particular of such a sign, which is inverse (opposite) to the sign of the first rectified voltage. In this case, the rectifier circuit can have a third and a fourth field effect transistor, the first source / Drain connection of the first field effect transistor with a first source / drain connection of the third

Field effect transistor and coupled to the gate terminal of the fourth field effect transistor. The first source / drain connection of the second field effect transistor is with a first source / drain connection of the fourth

Field effect transistor and coupled to the gate terminal of the third field effect transistor. A second source / drain connection of the third field effect transistor is with a second source / drain connection of the fourth

Field effect transistor coupled. This embodiment of the invention can clearly be understood as a two-way rectifier circuit consisting of a first subcircuit and a second subcircuit complementary to the first subcircuit, so that two rectified output voltages with opposite polarity are created.

The rectified voltage and the other rectified voltage can have different signs to one another (for example based on the reference potential). The first and second field-effect transistors in this case are preferably of the p-line type, and the third and fourth field-effect transistors are preferably of the n-line type in this case.

According to a preferred exemplary embodiment of the invention, the rectifier circuit is provided with a voltage offset device which is set up in such a way that it provides a predeterminable voltage offset (ie an electrical potential difference) between the first source ZDrain connection and the gate for at least one of the field effect transistors -Connection of the respective field effect transistor generated. Clearly, a voltage can be applied to a gate node of one of the transistors which is identical in its course to that applied to one of the source / drain nodes of the respective transistor Voltage is, but is offset by a predetermined (preferably positive) amount. This configuration is particularly advantageous when the transistor is a normally-on transistor, since a normally-on transistor of this circuit clearly behaves like a normally-off transistor.

The voltage offset device can by means of a capacitance between the first source / drain connection and the gate connection of the respective field effect transistor, as well as by means of a resistor, which is for example an ohmic resistor, and a bias voltage source between the gate connection of the respective field effect transistor and the first source / drain connections of two other of the field effect transistors.

Preferably at least part of the

Circuit components of the rectifier circuit according to the invention implemented in polymer electronics or silicon microelectronics.

The circuit arrangement according to the invention, which has a rectifier circuit according to the invention, is described in more detail below. Refinements of the rectifier circuit also apply to the circuit arrangement.

The circuit arrangement can be used as a contactless chip card or identification data carrier ("ID tag", in particular an RFID ("Radio Frequency Identification") data carrier, e.g. a

Transponder). In these fields of application, the advantages of the rectifier circuit come into play particularly strongly, namely a simple structure, an inexpensive manufacture and a reasonably good and low-loss functionality when providing a voltage. Exemplary embodiments of the invention are shown in the figures and are explained in more detail below.

Show it:

FIG. 1 shows a polymer transistor according to the prior art,

Figure 2 is a diagram in which a nomenclature for n-MOS or p-MOS field effect transistors of the normally-on or. Normally-off type is agreed

Figures 3A to 3G known from the prior art

Rectifier circuits and current-voltage characteristics of diodes or transistors connected therein,

FIGS. 4A, 4B current-voltage characteristics of a normally-on-n-MOS field-effect transistor or a normally-on-p-MOS field-effect transistor,

FIG. 5 shows a rectifier circuit according to a first exemplary embodiment of the invention,

6A, 6B voltage profiles at different nodes of the rectifier circuit from FIG. 5,

FIG. 7 shows a rectifier circuit according to a second exemplary embodiment of the invention,

FIG. 8 shows a rectifier circuit in accordance with a third exemplary embodiment of the invention,

FIG. 9 shows a rectifier circuit according to a fourth exemplary embodiment of the invention,

FIGS. 10A to 10E implementations of a resistance of the rectifier circuit from FIG. 9, FIGS. 11A to 11E implementations of a circuit component of the rectifier circuit from FIG. 9,

FIG. 12A transistors with a voltage offset device according to the invention,

FIG. 12B shows an equivalent circuit diagram from FIG. 12A,

FIG. 13 voltage profiles at different nodes of the subcircuits shown in FIGS. 12A, 12B,

Figure 14 is a diagram showing characteristics for different

Components are shown

15A shows a rectifier circuit according to a fifth

Embodiment of the invention,

FIG. 15B shows an equivalent circuit diagram of the rectifier circuit from FIG. 15A,

FIG. 16A shows a rectifier circuit according to a sixth exemplary embodiment of the invention,

FIG. 16B shows an equivalent circuit diagram of the rectifier circuit from FIG. 16A,

FIG. 17 shows a rectifier circuit according to a seventh exemplary embodiment of the invention,

Figures 18A to 20F simulation results for rectifier circuits according to the invention according to different embodiments of the invention.

The same or similar components in different figures are provided with the same reference numbers. A rectifier circuit 500 according to a first exemplary embodiment of the invention is described below with reference to FIG.

The rectifier circuit 500 has a coil 501, which is divided into a first coil component 502 and a second coil component 503. A center tap 504, which is brought to the electrical ground potential 508, is provided between the coil components 502, 503. The first coil component 502 is coupled to a first source / drain connection 505a of a first self-conducting p-MOS field-effect transistor 505, the second source / drain connection 505b of which is connected to a second source / drain connection 506b of a second self-conducting p-MOS field effect transistor 506 is coupled. The first source / drain connection 506a of the second self-conducting p-MOS field-effect transistor 506 is coupled to the second coil component 503. Furthermore, the first source / drain connection 505a of the first p-MOS field-effect transistor 505 is coupled to the gate connection 506c of the second p-MOS field-effect transistor 506. The first source ZDrain connection 506a of the second p-MOS field effect transistor 506 is coupled to the gate connection 505c of the first p-MOS field effect transistor 505. The second source /

Drain connections 505b, 506b are coupled to one another and to a first connection of a smoothing capacitance 507, the second connection of the smoothing capacitance 507 being at electrical ground potential 508. Furthermore, the first connection of the smoothing capacitance 507 to one

Output port 509 connected. An output voltage V ₀ u is generated between the output terminal 509 and the ground potential 508.

The rectifier circuit 500 shown in FIG. 5 represents a rectifier circuit using self-conducting transistors 505, 506, in which those from the prior art Known disadvantages are avoided. In contrast to the prior art (cf. FIG. 3C, FIG. 3E), where the transistors are operated as two terminal components in diode connection, the transistors 505, 506 are operated as three-terminal components. In addition, coil 501 is used as an AC voltage source with center tap 504. The transistors 505, 506 are operated at their gate connections 505c, 506c with a negative or positive electrical voltage with respect to the source / drain terminals, so that the transistors 505 and 505, respectively, are generated with sufficient amplitude of the driving AC voltage (generated in the coil 501) 506 can be switched on and off sufficiently safely. Since the end sections of the coil components 502, 503, which are not at ground potential 508, are in phase opposition to one another, each is

Half-wave clearly one of the transistors 505 or 506 in the open, the other in the blocked state.

It should be noted that the rectifier circuit 500 also functions when using normally-off transistors instead of the normally-on transistors shown in FIG. Due to the threshold voltage of a normally-off transistor, only the duration of the time interval in which the transistors 505 and 506 are switched off changes slightly compared to the circuit from FIG. 5 with normally-on transistors.

The coil 501 enables electromagnetic coupling of an AC voltage into the circuit. It should also be noted that the smoothing capacitance 507 is optional and can be omitted in a simplified embodiment. The rectified output voltage V ₀ uτ has a positive sign according to FIG.

The voltage profiles at different circuit nodes shown in FIG. 5 are described below with reference to FIGS. 6A and 6B. FIG. 6A shows a diagram 600, along which the time is plotted along the abscissa 601, whereas the voltage is plotted along the ordinate 602. A first curve 603 shows the voltage profile on the first coil component 502, the second curve 604 shows a voltage profile on the second coil component 604 and the third curve 605 shows the potential difference between the voltage profiles on the coil components 502, 503, clearly the difference between the second curve 604 and the first curve 603. The curves 603, 604 clearly represent the time profile of the input voltages coupled in via the coil 501.

A diagram 610 is also shown in FIG. 6B, along the abscissa 611 of the time and along the ordinate 612 of the voltage. A fourth curve 613 shows the time course of the output voltage V ₀ uτ- The curve 613 is the time course of the output voltage when sieving using a sieve or

Smoothing capacitor 508 and a current drain obtained. Curve 613 has a continuous positive sign, which means that the rectifier circuit 500 fulfills a rectification functionality.

The functionality of the rectifier circuit 500 from FIG. 5 can be clearly seen in that one of the transistors 505, 506 is positive at all times due to the alternating-phase alternating voltage signals at the gate connections 505c, 506c

Provides output voltage component at the output terminal 509, ie allows a corresponding current flow between its two source / drain terminals due to its respective gate voltage. This is a consequence of the crosswise connection of transistors 505, 506 shown in FIG. 5, which are thereby driven in phase opposition at the gate connections. This results in the total Consistently positive output voltage, which is shown as the fourth curve 613 in FIG. 6B.

A rectifier circuit 700 according to a second exemplary embodiment of the invention is described below with reference to FIG.

As can be seen from FIG. 7, the rectifier circuit 700 contains the components of the rectifier circuit 500. In addition, first and second normally-on n-MOS field-effect transistors 701, 702 are provided. The first source / drain connection 505a of the first normally-on p-MOS field-effect transistor 505 is coupled to a first source / drain connection 701a of the first n-MOS field-effect transistor 701. Furthermore, the first source / drain connection 506a of the second p-MOS field effect transistor 506 is coupled to a first source ZDrain connection 702a of the second n-MOS field effect transistor 702. The first source ZDrain connection 701a is coupled to the gate connection 702c, and the first source ZDrain connection 702a is coupled to the gate connection 701c. Furthermore, second source ZDrain connections 701b, 702b are coupled to one another and to a first connection of a further smoothing capacitance 703, the second connection of which lies on the electrical ground potential. The second source-Z drain connections 701b, 702b are further coupled to the further output connection 704, at which a negative electrical potential is provided. A rectified negative voltage -VQUT is thus created between the further output connection 704 and the electrical ground potential 508.

In the exemplary embodiment in FIG. 7, one branch of the rectifier circuit is designed with p-MOS transistors and another branch with n-MOS transistors. As a result, output voltages with both signs are obtained. According to Figure 7, both half-waves are vividly for that Provision of a positive and a negative direct voltage against a center tap 504 of the coil 501 associated with the electrical ground potential 508 is utilized.

A rectifier circuit 800 according to a third exemplary embodiment of the invention is described below with reference to FIG.

As shown in FIG. 8, the center tap 504 can also be omitted if a center potential is not required. Therefore, a coil 801 without a center tap is provided in FIG. A capacitor 802 is optionally connected between the output connections 509 and 704.

It is also possible to use the subcircuit for providing the positive rectified output voltage and the subcircuit for providing the negative rectified output voltage both with normally-on transistors, both with normally-off transistors, or also a subcircuit with normally-on transistors and to build the other one with normally-off transistors, provided that the latter, for example, is technology-related.

In many cases it is desirable to implement two-way rectification using both half-waves to provide positive and negative DC voltages. Unless pn diodes and complementary transistors are available in a technology and the available transistors due to their

Another solution must be found for the threshold voltage or because of its normally-on behavior not allowing the implementation of rectifier circuits according to the prior art (FIG. 3C, FIG. 3E). Exemplary embodiments of such solutions according to the invention are discussed below. Although the solution approaches set out below relate to the case of self-conducting p-MOS transistors, all exemplary embodiments can of course also be implemented with normally-off transistors or with n-MOS transistors.

A rectifier circuit 900 according to a fourth exemplary embodiment of the invention is described below with reference to FIG.

The rectifier circuit 900 represents a modification of the rectifier circuit 700. Instead of the first and second n-MOS field effect transistors 701, 702, third and fourth self-conducting p-MOS field effect transistors 901, 902 are provided according to FIG first and second p-MOS field-effect transistors 505, 506 are connected similarly to the n-MOS transistors 701, 702 in FIG. 7.

A first source ZDrain connection 901a of the third p-MOS field effect transistor 901 is coupled to the first source ZDrain connection 505a of the first p-MOS field effect transistor 505. Furthermore, the first source ZDrain connection 901a is coupled to a first connection of a first capacitor 903, the second connection of which is coupled to the gate connection 901c of the third p-MOS field-effect transistor 901. Furthermore, the gate connection 901c is coupled to a first connection of a first resistor 905 (for example an ohmic resistor), the second connection of which is connected to a first connection of a second resistor 906

(preferably an ohmic resistor) and is coupled to a first terminal of a circuit block 907. The second connection of the second resistor 906 is coupled to the gate connection 902c of the fourth p-MOS field-effect transistor 902 and is coupled to a first connection of a second capacitor 904, the second connection of which is connected both to a first source ZDrain connection 902a des fourth p-MOS field effect transistor 902 and also to a first source ZDrain connection 506a of the second p-MOS field effect transistor 506. A second source Z drain connection 901b of the third p-MOS field effect transistor 901 is coupled to a second source Z drain connection 902b of the fourth p-MOS field effect transistor 902. Furthermore, these two connections are coupled to a first connection of a third capacitor 908, the second connection of which lies at the electrical ground potential 508. The first connection of the third capacitor 908 is further coupled to an output connection 909, at which a potential of an output voltage -V ₀ uτ which is negative with respect to the ground potential is generated. A second connection of the circuit block 907 is at the electrical ground potential 508, and a third connection of the circuit block 907 is coupled to the respective second source ZDrain connections 505b, 506b of the first and second p-MOS field effect transistors 505, 506.

The rectifier circuit 900 is a two-way rectifier circuit using only transistors of one conduction type (here normally-on-p-MOS transistors) for generating two rectified output voltages with opposite polarity.

The subcircuit around the transistors 505, 506 for providing the positive output voltage + V ₀ u is implemented in a manner similar to that in FIG. 7 and is therefore not described in more detail here.

An electrical voltage is applied to the gate nodes 901c, 902c of the third and fourth p-MOS field-effect transistors 901, 902, which form part of the subcircuit for providing the negative output voltage -V ₀ uτ is identical to that applied to the first source ZDrain connections 901a, 901b of the respective transistors 901, 902 Tensions of the first and second coil components 502 and 503, which, however, are offset by a predetermined positive amount. This voltage can be provided, for example, with the aid of circuit block 907 (referred to as V _b ia _s in FIG. 9). The positive DC voltage V ₀ uτ of the subcircuit consisting of transistors 505, 506 is present at its third connection. The optional second connection of the circuit block 907 represents a reference node which is brought to the electrical ground potential 508. According to FIG. 9, the output voltage at the first connection of the circuit block 907 lies between the potential at the third connection and the electrical ground potential 508.

The connection of the components 903 to 906 shown results in a suitable dimensioning, in particular if the

Resistors R meet the condition that R >> lZ [2τrfC], where f is the frequency of the AC voltage applied and received and C is the capacitance of the capacitors 903, 904, that the average of the gate potential of the transistors 901, 902 on the electrical Potential of the first connection of the

Circuit block 907 lies. Furthermore, the electrical potential at the gate connections 901c, 902c follows the electrical potential at the first source ZDrain connections 901a and 902a.

The resistors 905, 906 can be implemented using the resistive materials available in the respective technology. Since the linearity of these resistors 905, 906 is low, each of the resistors 905, 906 can also be implemented using available active components (for example transistors).

FIGS. 10A to 10E show different exemplary embodiments for the realization of the resistors 905 or 906, wherein in all exemplary embodiments only transistors of one conduction type (here Normally-On-p-MOS transistors) are used. If complementary transistors (of the n-line type and the p-line type) are available, both types of transistors can also be used to implement the resistors 905, 906. In Fig.lOA to Fig.lOE series connections of a respective repeating basic element are shown.

In Fig.lOA ^'a plurality of interconnected resistance 1000 in diode circuit by means of a series circuit of p-MOS field-effect transistors realized 1,001th In this case, a second source / drain connection 1001b is coupled to the gate connection 1001c for a respective field effect transistor.

FIG. 10B shows a further realization of a resistor 1010, which is formed from a repetitive arrangement of two p-MOS field-effect transistors 1011, 1012 which are interconnected. The gate connection 1011c of a first p-MOS field-effect transistor 1011 is coupled to a second source ZDrain connection 1011b of the first p-MOS field-effect transistor 1011, and is connected to a first source ZDrain connection 1012a of a second p-MOS field-effect transistor 1012 and coupled to the gate terminal 1012c of the second p-MOS field effect transistor 1012.

IOC shows a repeating arrangement of first and second p-MOS field-effect transistors 1021, 1022, which form a resistor 1020. Here, a gate connection 1021c of the first p-MOS field-effect transistor 1021 is coupled to its second source / drain connection 1021b and to a second source / drain connection 1022b of the second p-MOS field-effect transistor 1022. The gate connection 1022c of the second p-MOS field-effect transistor 1022 is coupled to its first source / drain connection 1022a and to a first source / drain connection 1021a of the first p-MOS field-effect transistor. FIG. 10D shows a resistor 1030, again formed from a first and a second p-MOS field effect transistor 1031, 1032. Here, a first source / drain connections 1031a of the first p-MOS field effect transistor 1031 and a first source - / Drain terminal 1032a of the second p-MOS field-effect transistor 1032 coupled together. Likewise, the second source / drain connections 1031b and 1032b of the two field effect transistors 1031, 1032 are coupled to one another. The gate connection 1031c of the first p-MOS field-effect transistor 1031 is coupled to a first line 1033, which is brought to the electrical potential of the coil tap on the first coil component 502. Furthermore, the gate connection 1032c is coupled to a second line 1034, which is brought to the electrical potential of the coil tap on the second coil component 503.

FIG. 10E shows a resistor 1040, which is formed from a series connection of individual p-MOS field-effect transistors 1041, the gate connection 1041c of which is in each case at the electrical ground potential 508.

Furthermore, referring to FIGS. 11A to 11E, different exemplary embodiments of the circuit block. 907 from FIG. 9 for driving the resistors 905, 906 using only transistors of one conduction type (p-MOS field-effect transistors of the normally-on type) or resistors.

Here, the connection designated as the first connection in the description of FIG. 9 is provided with the designation "o", the second connection with the designation "b" and the third connection with the designation "i".

FIG. 11A shows circuit block 907 from FIG. 9 again. FIG. 11B shows a circuit block 1100 as an implementation of the circuit block 907. The nodes "i" and "o" are coupled to one another, ie short-circuited. In this case, the resistors 905, 906 are directly coupled at their common node to the positive output voltage + V _{out of} the subcircuit of the rectifier circuit 900 generating this. In other words, according to this implementation, the resistors 905, 906 are coupled to the second source / drain connections 505b, 506b of the first and second p-MOS field-effect transistors 505, 506. For a higher efficiency of the circuit for generating the negative voltage, however, it may be even more favorable to apply a lower voltage to the common nodes of the resistors 905, 906 than the positive output voltage + V ₀ u. In Fig.llC to Fig.llE variants are shown that make this possible.

In Fig.llC this is realized by means of the circuit block 1110, one of third and fourth resistors

1111 and 1112 formed voltage divider is used. Here, the connection "i" is coupled to a first connection of the third resistor 1111, the second connection of which is coupled to a first connection of the fourth resistor 1112. The other terminal of the fourth resistor

1112 is at electrical ground potential 508, whereas the second connection of the third resistor 1111 and the first

Connection of the fourth resistor 1112 are coupled to the node "o".

As shown in circuit block 1120 from FIG. HD, instead of resistors 1111, 1112, two first and second auxiliary transistors 1121, 1122 operated or connected in a diode circuit can also be used.

In FIG. HD, the connection "i" is coupled to a first source / drain connection 1121a of the first auxiliary transistor 1121, the second source / drain connection 1121b of which a second source / drain terminal 1122b of the second auxiliary transistor 1122 is coupled. The first source / drain terminal 1122a of the second auxiliary transistor 1122 is coupled to the gate terminal 1122c of the second auxiliary transistor 1122, whereas the second source / drain terminal 1121b of the first auxiliary transistor 1120 is coupled to its gate Port 1121c is coupled.

In the variants discussed so far, the voltage at the common node "o" of the first and second resistors 905, 906 is a strictly monotonically increasing function of the value of the positive output voltage of the subcircuit with the transistors 505, 506. For some applications it can be advantageous to build a circuit with a strongly non-linear transmission characteristic on the basis of a first auxiliary transistor 1131 operated in a diode circuit and a second auxiliary transistor 1132 connected as a current source.

Such a configuration is out of circuit block 1130

Fig.llE shown.

In circuit block 1130, connection "i" is coupled to a first source / drain connection 1131a and to the gate connection 1131c of the first auxiliary transistor 1131. The second source / drain terminal 1131b of the first auxiliary transistor 1131 is coupled to a first source / drain terminal 1132a of the second auxiliary transistor 1132 and to the node "o". Furthermore, the node "b" is at electrical ground potential 508 and is coupled to the gate connection 1132c and to a second source / drain connection 1132b of the second auxiliary transistor 1132. Circuit block 1130 has a non-linear transfer characteristic as shown in Fig. IIE.

In Fig.llB to Fig.llE are apart from the circuit blocks described mathematical relationships between the Voltages V (o) and V (i) are shown at the corresponding connections "o" and "i". Furthermore, diagrams are shown in which the dependence of the voltage V (o) at the node "o" on the voltage V (i) at the node "i" is plotted for the respective circuit block. Here Rl is the value of the third resistor 1111, R2 is the value of the fourth resistor 1112. Wl is the channel width of the first auxiliary transistor 1121 or 1131, L1 is the channel length. W2 is the channel width of the second auxiliary transistor 1122 or 1132, and L2 is the channel length, a. is a constant.

In the following, the circuitry effect of the transistor control according to FIG. 9 for that branch of the rectifier circuit 900 in which the negative output voltage is generated is explained with reference to FIGS. 12A, 12B.

FIG. 12A shows a partial circuit diagram 1200 of the rectifier circuit 900 with the third and fourth self-conducting p-MOS field-effect transistors 901, 902. The effects of those components in FIG. 9 which cause the voltage offset between the respective first source / drain connections and the gate connection of the transistors 901, 902 are in FIG. 12A by means of a first voltage offset component 1201 and a second

Voltage offset component 1202 is shown schematically. The voltage offset between the respective electrical potentials of the first source / drain connections and the respective gate connection of the transistors 901, 902 is denoted schematically by Δ in FIG. 12A. By means of this predeterminable voltage offset Δ, the normally-on behavior of the transistors 901, 902 is clearly compensated, so that due to their interconnection with the voltage-offset components 1201, 1202 they behave similarly to normally-off transistors. FIG. 12B shows a partial equivalent circuit diagram 1210 in which the first voltage offset component 1201 and the third self-conducting p-MOS field-effect transistor 901 are replaced by a first normally-off p-MOS field-effect transistor 1211 connected in a diode circuit. Furthermore, the

The arrangement consisting of the second voltage offset component 1202 and the fourth self-conducting p-MOS field-effect transistor 902 is replaced by a second self-blocking p-MOS field-effect transistor 1212 connected in a diode circuit. As shown in Fig. 12B, the first source / drain is

1211a of the first normally-off p-MOS field-effect transistor 1211 is coupled to its gate terminal 1211c. Similarly, the first source / drain terminal 1212a and the gate terminal 1212c of the second normally-off p-MOS field effect transistor 1212 are coupled together.

Fig. 12B thus shows an abstracted representation of the partial circuit diagram 1200 from Fig. 12A. Instead of the normally-on transistors 901, 902, the equivalent circuit diagram from FIG. 12B shows two normally-off transistors in diode connection, which are operated as a branch of the bridge rectifier.

When adjusting the voltage amount to compensate for the normally-on, it must be ensured that this is not too low, since otherwise this rectifier branch is still subject to loss, that is to say that the transistors do not block early enough. In this case, the threshold voltage-compensated transistor in the equivalent circuit diagram of Fig. 12B remains a normally-on device. Will the

If the voltage offset is too high, the time window in which the transistors are open is very small, so that only relatively small amounts of charge can pass through. For this reason, a circuit such as that shown in FIG. 11E can be advantageous for optimizing the rectifier characteristic or the rectifier efficiency. A diagram 1300 is described below with reference to FIG. 13, along which the time is plotted along the abscissa 1301 and a voltage is plotted along the ordinate 1302. First to sixth curves 1303 to 1305, 1308 to 1310 show voltage profiles at different nodes of the rectifier circuit 900 from FIG. 9. First to fourth voltage differences 1306, 1307, 1311, 1312 show potential differences between different curves from FIG. 13.

Curves 1303 to 1305 show voltage profiles at different nodes from FIG. 9 for a first amplitude of the input voltage between the first and second coil components 502, 503. Curves 1308 to 1310 show voltage profiles at different nodes from FIG. 9 for a second amplitude the input voltage between the first and second coil components 502, 503, which second amplitude is greater than the first amplitude. Curves 1303 and 1308 each show the voltage curve between the two end sections of the coil components 502, 503. Curves 1304 and 1309 show the voltage curves at the gate connections 901c, 902c when the circuit blocks from FIG. 11C or FIG. HD are implemented as a circuit block 907. Furthermore, curves 1305 and 1310 show voltage profiles at the gate connections 901c, 902c of the transistors 901, 902 for the case of the implementation of the circuit block from FIG. 11E as circuit block 907 in FIG. 9. The reference numerals 1306 and 1311 denote the voltage offsets between the respective source / drain connections 901a and 902a and the associated gate connections 901c, 902c, in the case of

Realization of the circuit block 907 by means of the circuit block shown in Fig.llE. Reference numbers 1307 and 1312 denote the voltage offset between the first source / drain connections 901a, 902a and the respective gate connections 901c, 902c of the respective transistors in the case of the implementation of the circuit block 907 below Using one of the circuit blocks shown in Fig.llC, Fig. HD.

Again with reference to the circuitry implemented threshold voltage compensation for the transistors 901, 902 in the subcircuit to form the negative

The output voltage in FIG. 9 in FIG. 13 is the gate voltage of the transistors 901, 902 in FIG. 9 (curves 1304, 1305, 1309, 1310) as a function of the input voltage (curves 1303, 1308) of the rectifier circuit from FIG. 9 for different amplitudes of the input voltage and different implementations of the circuit component designated in FIG. 9 as circuit block 907 for driving the resistors 905, 906. Curves 1304, 1309 result when using the circuit from Fig.llC, Fig. HD, curves 1305, 1310 result when using the circuit from Fig.llE.

The voltage difference 1307 or 1312 (difference from curve 1304 and curve 1303 or 1309 and 1308) when using one of the circuit blocks from FIG. 11C, FIG. HD depends on the amplitude of the input voltage 1303 or 1308 and is approximately proportional to this. The voltage difference 1306 or 1311 (difference from curve 1305 and 1303 or 1310 and 1308) when using the circuit from FIG. 11E is essentially independent of the amplitude of the input voltage 1303, 1308 if this amplitude exceeds a certain minimum value.

Furthermore, the advantages of realizing the rectifier circuit according to the invention in silicon CMOS technology are discussed in detail.

In silicon bulk and SOI ("Silicon On Insulator") CMOS processes, both n- and p-doped material are often available and thus pn junctions, so that in some cases a bridge rectifier, as shown in Fig.3A or Fig.3G, can be realized.

However, there are cases or areas of application in which the implementation of rectifiers according to the invention provides significant advantages, as will be described below.

There are applications in which the voltage transmitted to a receiver antenna or coil varies within wide limits. The maximum DC voltage that can be tapped at an output of a bridge rectifier constructed with silicon pn diodes is essentially equal to the peak-to-peak value of the coupled AC voltage, reduced by twice the amount of the threshold voltage of the diodes. If a current is drawn from an output of the rectifier, this value drops further. In the case of a silicon diode, the threshold voltage lies between approximately 600mV and 700mV due to the basic material properties within a window which cannot be changed by means of technological measures. If, for example, the antenna or coil supplies an AC voltage of 1.5V (peak-to-peak), the resulting DC voltage is below 300mV, in the case of a current draw even less than 100mV, which is necessary for the operation with the output voltage of the rectifier circuit operated useful circuit is clearly too low for many applications. A rectifier that works with low voltage drops on the rectifying components is desirable in this area of application. Selenium or germanium diodes can be used with a lower one

Threshold voltages in the range of approximately 200mV to 300mV can be produced, but can only be integrated into the CMOS process with extremely great effort.

This problem is solved by means of the rectifier circuit according to the invention, since transistors with low threshold voltages and often occur in modern CMOS processes different transistor types with different threshold voltages are also available.

The circuit architecture according to the invention also delivers significant advantages if the circuit which is connected to. the rectified voltage is operated using a technology in which the maximum permissible operating voltage is typically around 1.2V for future generations. Since the current drawn from the circuit also flows through the rectifier, this means that often 50% or more of the total power loss (current multiplied by the voltage drop) is already generated in the rectifier circuit, since typically 1.2V to 1.4 V drop. This unfavorable power balance can be considerably improved by using a rectification circuit according to the invention, since this allows the construction of rectifiers with low voltage drops on the rectifying components.

Some of the relationships described are illustrated again in diagram 1400 shown in FIG. 14.

A voltage in volts is plotted along the abscissa 1401- of the diagram 1400, and a current in amperes is plotted along an ordinate 1402. A first curve 1403 shows a current-voltage characteristic for a MOSFET with a low threshold voltage Vt _h . A second curve 1404 shows the current-voltage characteristic for a silicon pn diode, and a third curve 1405 shows a current-voltage characteristic for a field effect transistor with regular threshold voltage V _t -

In FIG. 14 there are thus current-voltage characteristics of a silicon pn diode 1404 and two MOS transistors 1403, 1405 with different threshold voltages as a function of that at the pn junction of the diode. or between the gate connection and the first source / drain connection when the electrical potential of the second source / drain connection (for example second source / drain voltage greater than or equal to the gate voltage) is not too low. For the pn diode, the typical value of the threshold voltage is assumed to be 650mV, for the transistors, typical values for modern processes are assumed to be 400mV ("regular V _τ device") or 100mV ("Low V _τ device").

If you consider an application in which the by means of a

Receiver antenna or coil transmitted voltage varies within wide limits, it is possible to connect a rectifier circuit according to the invention in parallel with a bridge rectifier made of silicon pn diodes. In this case, one benefits at low voltages from the fact that the circuit according to the invention then already works; at high voltages, one benefits from a greater steepness of the pn diode characteristic in the pass band (cf. FIG. 14).

In the following, exemplary embodiments of the rectifier circuit according to the invention in CMOS technology are described with reference to FIGS. 11A to 17. A distinction is made between bulk CMOS process and SOI CMOS process. In a CMOS process, the p-MOS transistors are often implemented in wells, whereas in such processes the n-MOS transistors are often formed directly in a common substrate. The examples described below refer to this case. However, it should be noted that the rectifier circuit according to the invention can also be implemented with n-MOS transistors in wells and p-MOS transistors directly in a substrate. There are processes based on an n-type substrate in which the p-MOS transistor is formed directly in the substrate, whereas the n-MOS transistor is manufactured in a tub. Some modern CMOS processes allow or require the production of n- and p-MOS transistors in their own tub. If such processes are carried out, for example, on the basis of a p-type substrate, the p-MOSFET is in a simple n-type well, while the n-MOSFET is in a p-type well, which in turn is formed in a deeper n-type well. In this case, it is possible to switch the operating point between inversion and accumulation (or depletion) using the trough connection for n- and p-MOS transistors.

In the following, a rectifier circuit 1500 in silicon technology and a replacement circuit diagram 1510 are described with reference to FIGS. 1A, 5B.

Referring to the equivalent circuit diagram shown in Fig.lSB

1510 of the rectifier circuit 1500 according to a fifth exemplary embodiment of the invention, the essential difference to the rectifier circuit 500 from FIG. 5 is that instead of the three terminals (gate connection, two source / drain connections) transistors 505, 506 fourth terminals (Gate connection, two source / drain connections, well connection) first and second p-MOS field-effect transistors 1503, 1504 are provided. As a fourth connection, these have a trough connection 1503d or 1504d.

The well connection 1503d of the first p-MOS field-effect transistor 1503 is coupled to the first and the second source / drain connection 1503a and 1503b via second and third parasitic diodes 1506, 1507. Analogously, the second well connection 1504d is coupled to the first and second source / drain connections 1504a and 1504b of the second p-MOS field-effect transistor 1504 via first and second parasitic pn junctions 1505, 1506, respectively.

In Fig. 15A is the integration of that shown in Fig. 15B

Components shown in a p-type silicon substrate 1501, the source / drain regions 1504a, 1504b, 1503a, 1503b as p ⁺ -doped regions and the well regions 1503d, 1504d as n ⁺ -doped regions are formed in an n-conductive trough 1502 formed in the p-conductive silicon substrate 1501.

The rectifier circuit 1500 represents a realization of a rectifier circuit according to the invention from two p-MOS transistors in silicon bulk CMOS technology for generating a positive rectified voltage at an output 1508. The parasitic diodes 1505 to 1507 are connected to the pn- Transitions of transistors 1503, 1504 shown. It should also be noted that the tub connections 1504d, 1503d are coupled to the output 1508. The source-side diodes of transistors 1503, 1504 can, depending on the voltage drop, become electrically conductive under certain circumstances, but since they support the rectifier function and do not counteract this, this is not a problem.

Furthermore, referring to Fig.lδA, Fig.l6B

Rectifier circuit 1600 and its equivalent circuit diagram 1610 according to a sixth embodiment of the invention.

The rectifier circuit 1600 from FIG. 16A differs from the rectifier circuit 1500 essentially in that n-MOS transistors 1602, 1603 are provided instead of p-MOS transistors 1503, 1504. Furthermore, the source / drain connections of the transistors and the well connections are not formed in an n-conductive well 1502, as in FIG. 11A, but rather directly in a p-conductive substrate 1501. The line types of the source / drain regions 1603a, 1603b, 1602a, 1602b (n ⁺ -doped) and of the well regions 1603d, 1602d (p ⁺ -doped) are thus inverse to those from FIG. 15A. The rectifier circuit 1600 is thus set up from two n-MOS transistors 1602, 1603 in standard silicon bulk CMOS technology for generating a negative rectified output voltage at the output 1508. The substrate 1501 is coupled to the output 1508. The parasitic diodes 1604 to 1606 at the pn junctions of the transistors are shown in Fig. 16A and in the equivalent circuit diagram 1610 from Fig. 16B. Depending on the voltage drop, the source-side diodes of the transistors can become electrically conductive, but since they support rectification and do not counteract this, this is not a problem.

It is possible to combine the rectifier circuits shown in FIGS. 16A and 16A (for example, to form them in a common substrate), as a result of which a two-way bridge rectifier circuit composed of rectifier circuits according to the invention consisting of two n-MOS and two p- MOS transistors result.

A rectifier circuit 1700 according to a seventh exemplary embodiment of the invention is described below with reference to FIG.

17 shows a two-way bridge rectifier circuit 1700 comprising two p-MOS transistors 1705, 1706 and two n-MOS transistors 1707 and 1708 in silicon SOI-CMOS technology (SOI, "Silicon-On -Insulator ") for generating a negative and a positive rectified voltage at first and second outputs 1709, 1710.

An SOI layer sequence 1704 is formed from a bulk silicon substrate 1701, a buried silicon oxide layer 1702 and a silicon layer 1703. In the silicon layer 1703, p ⁺ , n ⁺ or p- and n-doped regions are formed, which are the source / drain connections 1706a, 1706b, 1705b, 1705a, 1707a, 1707b, 1708b, 1708a and channel - Form areas of the transistors. A gate insulating layer is provided between gate connections 1706c, 1705c, 1707c, 1708c of the transistors and silicon layer 1703. The parasitic diodes at the pn junctions of the transistors are shown in Fig.17. Because the body material of the

17 is not coupled to another node of the circuit or to the output voltage connections 1709, 1710, the discussion of the effect of the parasitic diodes, as in the case of bulk technology, is unnecessary here.

If SOI technology is used, or bulk technology, in which the transistors used as rectifiers can be implemented in their own tub, and if the peak values of the rectifying ones

If the voltage is below approximately 600 mV to 700 mV (threshold voltage of a pn diode), the gate node can also be coupled to the well node of a relevant transistor. In this case, a so-called dynamic V _τ transistor is obtained, that is to say a transistor whose

Threshold voltage takes a low value if it is to be electrically conductive and takes a high value if it is to be blocked.

It should also be noted that instead of planar MOS transistors, other designs (Fin-FET, double gate transistor, vertical transistor, etc.) can also be used.

In the following, reference is made to those in FIGS

20F shows diagrams in which simulation results for circuit arrangements according to the invention are shown.

For these simulations, n-MOS transistors with a gate length of 200 nm, a width of 10 μm and a thickness of the gate insulating layer (silicon oxide) of 3 nm are assumed. The peak value and frequency of the exciting voltage are as 500mV and 500MHz assumed. Only one polarity is considered, the output is connected with a smoothing capacity of 100pF and loaded with an ohmic load of 100Ω, lkΩ or lOkΩ.

In the voltage diagrams of Fig. 11A, Fig. 19A, Fig. 20A, a voltage at the upper end section of the first coil component 502 according to Fig. 5 is shown as V (A1).

In Fig.lδB, Fig.l9B, Fig.20B is the temporal

5 shows the voltage curve at a lower section of the second coil component 503 according to FIG. 5, designated V (A2).

In Fig. 16C, Fig. 19C, Fig. 20C the time course of the respective output voltage from the respective output connection is shown, designated V _out . The arrow shown in Fig.lδC, Fig.l9C, Fig.20C shows the change in the output voltage curve for different loads, the arrow showing the lowest load (100Ω) to the highest load (lOkΩ).

Fig. LD, Fig. 19D, Fig. 20D show the curves of the electrical current at the respective second transistor of a respective rectifier circuit (for example transistor 506 in Fig. 5) for different loads, with an arrow in Fig. LD again shows the change in current when the load changes from 100Ω to 10kΩ.

In Fig. LδE, Fig. 19E, Fig. 20E, the curves of the electrical current at the first transistor of a respective rectifier circuit (for example transistor 505 in Fig. 5) are shown for different loads, with an arrow in Fig. 1E again shows the change in current when the load changes from 100Ω to 10kΩ.

In Fig. 18F, Fig. 19F, Fig. 20F is the at the respective output node of the rectifier according to the invention Circuit present electrical current I _{D t shown} for different loads.

Fig.lδA to Fig.lδF refer to a normally-on transistor with a threshold voltage of -300mV.

Fig. 19A to Fig. 19F refer to a "zero V _t device" with a vanishing threshold voltage.

20A to 20F show results for a normally-off device with a threshold voltage of + 300mV.

The simulation results from Fig.lδA to Fig.20F show the operability of the rectifier circuit according to the invention. In particular, the lower voltage drop across the rectifying elements, which is possible compared to pn diodes, and therefore the particularly advantageous suitability for low voltage becomes clear.

LIST OF REFERENCE NUMBERS

100 polymer transistor

101 substrate

102 gate electrode

103 gate insulating layer

104 first source / drain connection

105 second source / drain connection

106 channel area 200 diagram

300 rectifier circuit

301 AC voltage source

302 first diode

303 second diode

304 third diode

305 fourth diode

306 first DC output terminal

307 second DC output terminal

308 filter capacitor

310 diagram

311 abscissa

312 ordinate

320 rectifier circuit

321 first n-MOS field effect transistor

322 second n-MOS field effect transistor

323 third n-MOS field effect transistor

324 fourth n-MOS field effect transistor 330 diagram

331 abscissa

332 ordinate

340 rectifier circuit

341 first p-MOS field effect transistor

342 second p-MOS field effect transistor

343 third p-MOS field effect transistor

344 fourth p-MOS field effect transistor 350 diagram

351 abscissa

352 ordinate

360 rectifier circuit

361 spool

400 diagram

401 abscissa

402 ordinate

410 diagram

411 abscissa

412 ordinate

500 rectifier circuit

501 spool

502 first coil component

503 second coil component

504 center tap

505 first self-conducting p-MOS field effect transistor 505a first source / drain connection

505b second source / drain connection 505c gate connection

506 second self-conducting p-MOS field effect transistor 506a first source / drain connection

506b second source / drain connection 506c gate connection

507 smoothing capacity

508 ground potential

509 output connector

600 diagram

601 abscissa

602 ordinate

603 first curve

604 second curve

605 third curve

610 diagram

611 abscissa 612 ordinate

613 fourth curve

700 rectifier circuit

701 first normally-on n-MOS field effect transistor 701a first source / drain connection

701b second source / drain connection 701c gate connection

702 second self-conducting n-MOS field-effect transistor 702a first source / drain connection

702b second source / drain connection 702c gate connection

703 more smoothing capacity

704 further output connection

800 rectifier circuit

801 coil

802 capacitor

900 rectifier circuit

901 third self-conducting p-MOS field-effect transistor 901a first source / drain connection

901b second source / drain connection 901c gate connection

902 fourth self-conducting p-MOS field effect transistor 902a first source / drain connection

902b second source / drain connection 902c gate connection

903 first capacitor

904 second capacitor

905 first resistor • 906 second resistor

907 circuit block

90δ third capacitor

909 output connector

1000 resistance

1001 p-MOS field effect transistor

1001a first source / drain connection 1001b second source / drain connection 1001c gate connection

1010 resistance

1011 first p-MOS field effect transistor 1011a first source / drain connection 1011b second source / drain connection 1011c gate connection

1012 second p-MOS field effect transistor 1012a first source / drain connection 1012b second source / drain connection 1012c gate connection

1020 resistance

1021 first p-MOS field effect transistor 1021a first source / drain connection 1021b second source / drain connection 1021c gate connection

1022 second p-MOS field effect transistor 1022a first source / drain connection 1022b second source / drain connection 1022c gate connection

1030 resistance

1031 first p-MOS field effect transistor 1031a first source / drain connection 1031b second source / drain connection 1031c gate connection

1032 second p-MOS field effect transistor 1032a first source / drain connection 1032b second source / drain connection 1032c gate connection

1033 first line

1034 first line

1040 resistance

1041 p-MOS field effect transistor 1041a first source / drain connection 1041b second source / drain connection 1041c gate terminal 1100 circuit block

1110 circuit block

1111 third resistance

1112 fourth resistance

1120 circuit block

1121 first auxiliary transistor

1121a first source / drain connection 1121b second source / drain connection 1121c gate connection

1122 second auxiliary transistor 1122a first source / drain connection 1122b second source / drain connection 1122c gate connection

1130 circuit block

1131 first auxiliary transistor

1131a first source / drain connection 1131b second source / drain connection 1131c gate connection

1132 second auxiliary transistor 1132a first source / drain connection 1132b second source / drain connection 1132c gate connection

1200 part circuit diagram

1201 first voltage offset component

1202 second tension offset component

1210 equivalent circuit diagram

1211 first self-blocking p-MOS field-effect transistor 1211a first source / drain connection

1211b second source / drain connection 1211c gate connection

1212 second normally-off p-MOS field effect transistor 1212a first source / drain connection

1212b second source / drain connection 1212c gate connection 1300 diagram

1301 abscissa

1302 ordinate

1303 first curve

1304 second curve

1305 third curve

1306 first voltage difference 1307 second voltage difference 13Oδ fourth curve

1309 fifth curve

1310 sixth curve

1311 third voltage difference

1312 fourth voltage difference

1400 diagram

1401 abscissa

1402 ordinate

1403 first curve

1404 second curve

1405 third curve

1500 rectifier circuit

1501 p-type silicon substrate

1502 n-conductive tub

1503 first p-MOS field effect transistor 1503a first source / drain connection 1503b second source / drain connection 1503c gate connection

1503d tub connection

1504 second p-MOS field effect transistor 1504a first source / drain connection 1504b second source / drain connection 1504c gate connection

1504d tub connection

1505 first pn transition 1506 second pn transition 1507 third pn transition 1508 exit

1510 equivalent circuit diagram

1600 rectifier circuit

1601 p-type silicon substrate

1602 first n-MOS field effect transistor 1602a first source / drain connection 1602b second source / drain connection 1602c gate connection

1602d tub connection

1603 second n-MOS field effect transistor 1603a first source / drain connection 1603b second source / drain connection 1603c gate connection

1603d tub connection

1604 first pn transition

1605 second pn junction

1606 third pn junction 1610 equivalent circuit diagram

1700 rectifier circuit

1701 bulk silicon substrate

1702 buried silicon dioxide layer

1703 silicon layer

1704 SOI layer sequence

1705 first p-MOS field effect transistor 1705a first source / drain connection 1705b second source / drain connection 1705c gate connection

1706 second p-MOS field effect transistor 1706a first source / drain connection 1706b second source / drain connection 1706c gate connection

1707 first n-MOS field effect transistor 1707a first source / drain connection 1707b second source / drain connection 1707c gate connection 1708 second n-MOS field effect transistor 1708a first source / drain connection 1708b second source / drain connection 1708c gate connection

1709 first exit

1710 second exit

Claims

Claims: 1. rectifier circuit for providing a rectified voltage, • with a first and a second field effect transistor; Wherein the first and second field effect transistors each have a first source / drain connection, for applying an AC voltage between the first source / drain connections, which is set up in such a way that the electrical potentials at the first source / drain Connections of the field effect transistors have different signs with respect to one another with respect to a reference potential; o wherein the first source / drain connection of the first field effect transistor is coupled to a gate connection of the second field effect transistor; • wherein the first source / drain connection of the second field effect transistor is coupled to a gate connection of the first field effect transistor; • a second source / drain connection of the first Field effect transistor is coupled to a second source ZDrain connection of the second field effect transistor. Rectifier circuit according to claim 1, in which at least one of the field effect transistors is normally on and Z or in which at least one of the field effect transistors is normally off. Rectifier circuit according to claim 1 or 2, in which at least one of the field-effect transistors is of the p-line type and Z or is at least one of the field-effect transistors of the n-line type. 4. Rectifier circuit according to one of claims 1 to 3, in which at least one of the field effect transistors Polymer field-effect transistor; Silicon-on-insulator field effect transistor, • bulk silicon field effect transistor; Junction FET; Fin-FET; or Double gate field effect transistor is. 5. Rectifier circuit according to one of claims 1 to 4, in which the AC voltage can be provided by means of an AC voltage element. 6. Rectifier circuit according to claim 5, wherein the AC element • an antenna; • a coil; or • is an AC voltage source. 7. Rectifier circuit according to claim 5 or 6, wherein the AC element is a coil with center tap, which is brought to the electrical reference potential. 8. Rectifier circuit according to one of claims 1 to 7 for providing another rectified voltage, o with a third and a fourth Field effect transistor; o the first source / drain connection of the first field effect transistor having a first source / Drain connection of the third field effect transistor and is coupled to a gate connection of the fourth field effect transistor; ® wherein the first source / drain connection of the second field effect transistor with a first source ZDrain connection of the fourth field effect transistor and with a gate connection of the third field effect transistor is coupled; wherein a second source ZDrain connection of the third field effect transistor is coupled to a second source ZDrain connection of the fourth field effect transistor. 9. Rectifier circuit according to claim 8, in which the field effect transistors are set up in such a way that the rectified voltage and the other rectified voltage have different signs with respect to one another with respect to the reference potential. 10. A rectifier circuit according to claim 9, wherein the first and second field effect transistors are of the p-line type and the third and fourth field effect transistors are of the n-line type. 11. Rectifier circuit according to one of claims 1 to 10, with a voltage offset device, which is set up in such a way that it has a predeterminable voltage offset between the first source ZDrain connection and the gate connection of the respective field effect transistor for at least one of the field effect transistors generated. 12. Rectifier circuit according to claim 11, wherein the voltage offset device by means of a capacitance between the first source ZDrain connection and the gate connection of the respective field effect transistor and by means of a resistor and a bias source between the gate connection of the respective field effect transistor and the first source ZDrain connections of two of the other field effect transistors. 13. Rectifier circuit according to one of claims 1 to 12, in which at least part of the circuit components in • polymer electronics; or • Silicon microelectronics is implemented. 14. Circuit arrangement • with a substrate; With a rectifier circuit formed on andZ or in the substrate according to one of claims 1 to 13. 15. Circuit arrangement according to claim 14, configured as a • contactless chip card; or • Identification media. 16. A method of making a rectifier circuit for providing a rectified voltage, according to the method • a first and a second field effect transistor are formed; • a first source ZDrain connection of the first and the second field effect transistor for applying one AC voltage is set up between the first source ZDrain connections, which is set up in such a way that the electrical potentials at the first source ZDrain connections of the field effect transistors have different signs with respect to a reference potential; o the first Source-ZDrain connection of the first Field effect transistor is coupled to a gate terminal of the second field effect transistor; • the first Source-ZDrain connection of the second Field effect transistor is coupled to a gate terminal of the first field effect transistor; a second source ZDrain connector of the first Field effect transistor is coupled to a second source ZDrain connection of the second field effect transistor.