WO2004055672A1 - 性能シミュレーション装置、性能シミュレーションプログラムおよび性能シミュレーション方法 - Google Patents
性能シミュレーション装置、性能シミュレーションプログラムおよび性能シミュレーション方法 Download PDFInfo
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- WO2004055672A1 WO2004055672A1 PCT/JP2002/013251 JP0213251W WO2004055672A1 WO 2004055672 A1 WO2004055672 A1 WO 2004055672A1 JP 0213251 W JP0213251 W JP 0213251W WO 2004055672 A1 WO2004055672 A1 WO 2004055672A1
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
- G06F11/3457—Performance evaluation by simulation
Definitions
- the present invention relates to a performance simulation apparatus, a performance simulation program, and a performance simulation method for simulating the operation of a computer and collecting and displaying data relating to the dynamic situation of hardware elements constituting the computer.
- the present invention relates to a performance simulation apparatus, a performance simulation program, and a performance simulation method that make it easy for a hardware designer to grasp a place where a phenomenon to be caused occurs and a cause of the phenomenon.
- CMPs on-chip multiprocessors
- multi-strand configurations it is easy to correlate the entire information only from locally displayed information, because there are many factors related to performance improvement. Rather, it was difficult to consider performance improvements.
- the CMP is a computer in which a plurality of CPUs share memory, and one CPU may have a plurality of processors called cores.
- a multi-strand computer is
- One CPU is a computer that executes multiple jobs (strands) simultaneously.
- the present invention provides a performance simulation apparatus, a performance simulation program, and a performance simulation device that can easily understand a place where a phenomenon causing performance degradation occurs and a cause of occurrence of the phenomenon by a hardware designer. It aims to provide a simulation method. Disclosure of the invention
- the present invention provides a performance simulation which simulates the operation of a computer and collects and displays data on the dynamic situation of hardware elements constituting the computer.
- An apparatus comprising: graphic data creating means for creating graphic data for displaying a graphic by associating the dynamic states of the hardware elements with each other; and using the graphic data created by the graphic data creating means.
- Graphic display means for displaying a dynamic status of the hard element.
- the present invention is a performance simulation program which simulates the operation of a computer, collects and displays data relating to the dynamic situation of hardware elements constituting the computer, and executes the operation of the hardware element.
- Graphic data creation procedure for creating dramatic data for graphically displaying the relevant situations in a graphical manner, and displaying the dynamic situation of the hardware element using the graphics data created by the graphic data creation procedure It is characterized by executing the following graphic display procedure and.
- the present invention is a performance simulation method for simulating the operation of a computer, collecting and displaying data on the dynamic status of hardware elements constituting the computer, and comprising: A graphic data creating step of creating graphic data for displaying a graphic in a correlated manner with a situation, and a graphic display step of displaying a dynamic situation of the hardware element using the graphic data created by the graphic data creating step; It is characterized by including.
- graphic data for graphic display is created by associating the dynamic situations of the hardware elements with each other, and the dynamic situation of the hardware elements is displayed using the created graphic data. For the place where the phenomenon causing the performance degradation has occurred and the hardware designer who caused the phenomenon, Can be easily grasped.
- the present invention is a performance simulation program which simulates the operation of a computer, collects and displays data relating to the dynamic status of hardware elements constituting the computer, and executes the operation of the hardware element.
- graphic data to be displayed graphically is created by associating the dynamic situations of hardware elements with each other, and the display device that displays the dynamic situation of the hardware elements using the created graphic data Since the data is transmitted via the network, the hardware designer who uses the display device should easily understand where the phenomenon causing the performance degradation has occurred and the cause of the phenomenon. Can be.
- the present invention is a performance simulation program which simulates the operation of a computer, collects and displays data relating to the dynamic status of hardware elements constituting the computer, and executes the operation of the hardware element.
- a graphic data creating procedure for creating a darafic data for displaying a graphical display in a correlated manner with a dynamic situation, and displaying a dynamic situation of the hardware element using the graphic data created by the graphic data creating procedure And a graphic data output procedure for outputting the graphic data input by the display device to the storage device.
- a display device that creates graphic data for graphic display by associating the dynamic situations of hardware elements with each other and uses the created graphic data to display the dynamic situation of the hardware elements Since the graphic data input by the computer is output to the storage device, the hardware design using the display device The user can easily understand where the phenomenon causing the performance degradation has occurred and the cause of the phenomenon.
- FIG. 1 is an explanatory diagram for explaining the concept of dynamic data collection by the performance simulation device according to the present embodiment
- FIG. 2 is a configuration of the performance simulation device according to the present embodiment
- FIG. 3 is a diagram showing an example of a simulation parameter for graphic display
- FIG. 4 is a flowchart showing a processing procedure of the performance simulation apparatus according to the present embodiment
- FIG. 5 is a flow chart showing the processing procedure of the traffic data display unit shown in FIG. 2
- FIG. 6 is a flowchart of the graphic display displayed by the performance simulation device according to the present embodiment
- FIG. 7 is a diagram showing another example
- FIG. 7 is a diagram showing another example of a graphic display displayed by the performance simulation apparatus according to the present embodiment.
- FIG. 8 is a diagram illustrating a computer system that executes a performance simulation program according to this embodiment
- FIG. 9 is a functional Proc diagram showing the configuration of the body portion shown in Figure 8.
- FIG. 1 is an explanatory diagram for explaining the concept of dynamic data collection by the performance simulation device according to the present embodiment.
- the figure shows an example of a computer simulated by the performance simulation apparatus according to the present embodiment.
- the computer includes an instruction unit 10, an arithmetic unit 20, a primary cache unit 30, , Secondary cache Knit 40.
- the secondary cache unit 40 has a secondary cache 41 and an external access unit 42.
- Conventional performance simulation equipment collects data indicating the dynamic status of buffers, queues and selectors of these units, that is, dynamic data, and displays the collected dynamic data as local information.
- dynamic data such as the number of accesses, the number of hits, and the type of request are collected, and for the memory system between the secondary cache 41 and the memory, it is stored in the external access unit 42.
- Dynamic data such as the number of buffers waiting to be sent and the number of data waits, was collected.
- the performance simulation apparatus collects the dynamic data of the buffers, queues, and selectors of each unit, and displays the dynamic status of the buffers, queues, and selectors from the arithmetic unit to the memory on the same time axis. It is displayed graphically in line with. Further, when collecting the dynamic data of the buffers, queues and selectors of each unit, the performance simulation apparatus according to the present embodiment adds information indicating the operation of the entire computer to the collected dynamic data. . Then, when displaying the collected dynamic data, it is possible to display the dynamic data in association with the operation of the entire computer.
- a core ID is provided to identify the instruction unit 10 and the operation unit 20 of each core, and the core ID and strand ID are collected.
- This dynamic data can be displayed graphically for each core strand, which is the access request source to the secondary cache 41, by adding the dynamic data to the secondary cache 41.
- the core ID and the strand ID are added when collecting data related to dynamic data such as the number of buffers waiting to be sent and the number of data waits in the external access unit 42.
- the dynamic data can be displayed graphically for each core strand that has calmed down and requested memory access.
- the performance simulation apparatus does not display the dynamic data of the buffers, queues and selectors collected by executing the simulation as local information, but instead executes the operation unit 20. Graphical display of buffers, queues and selectors from the memory to the memory makes it easy for hardware designers to understand the interrelationships.
- the performance simulation apparatus adds buffers and queues by adding core IDs and strand IDs when collecting dynamic data of the buffers, queues and selectors of each unit. ⁇
- the dynamic status of the selector it is possible to display it for each core strand, and the hardware designer can grasp the dynamic status of buffers, queues and selectors in relation to the operation of the entire computer. Is easy.
- FIG. 2 is a functional block diagram showing the configuration of the performance simulation device according to the present embodiment.
- the performance simulation apparatus 200 includes a simulation data input unit 210, a simulation unit 220, a graphic display data creation unit 230, and a graphic display unit 240. It has a simulation data storage unit 250, a collected data storage unit 260, a graphic display data storage unit 270, and a control unit 280.
- the simulation data input unit 210 is a processing unit for inputting execution history data and simulation parameters.
- the execution history data corresponds to a program executed on a computer to be simulated, and is history data when the program is executed on actual hardware.
- the data corresponding to the program executed on the computer that is the target of the simulation includes simulation data that inherits the tendency of the program, processing of the execution history data, or actual hardware. It is also possible to use a program input by.
- the simulation parameters are used to select the specifications for executing the simulation. It is used to make selections and specify the graphical display format of the simulation results.
- FIG. 3 is a diagram showing an example of simulation parameters for graphic display. As shown in the figure, using this simulation parameter, the display time can be specified in 1 if the type of buffer, queue and selector to be displayed, the form of the graph, or the details of the display in the graph.
- the simulation section 220 is a processing section that executes a simulation using the simulation parameters input by the simulation data input section 210 and collects data indicating the dynamic status of buffers, queues and selectors. is there.
- the simulation unit 220 collects information on the job that has requested access to the buffers, queues and selectors, that is, the core ID and the strand ID. Add to the collected data.
- the graphic display data generator 230 generates the graphic display data in the form specified by the simulation parameters based on the data indicating the dynamic status of the buffers, queues and selectors collected by the simulation unit 220. This is the processing unit to be created.
- the graphic display data creating section 230 creates display data so that the dynamic state of the buffer, queue, and selector from the arithmetic section to the memory can be displayed on the same time axis in a graphic manner.
- the graphic display data creation unit 230 creates display data so that graphics can be displayed for each core strand that has requested access to the buffer, queue, and selector.
- the graphic display data creating unit 230 creates data for graphic display by arranging the dynamic status of buffers, queues and selectors from the arithmetic unit to the memory, so that the hardware designer can make hardware It is easy to correlate and grasp the local dynamic data of elements.
- simulation section 220 dynamic buffer, queue and selector When collecting data indicating the status, information on the cores and strands that requested access to the buffers, queues and selectors is added, and the graphic display data creation unit 230 displays the graphic display data for each core and strand.
- the graphical display unit 240 is a processing unit that graphically displays the dynamic status of buffers, queues and selectors on a display device using the graphic display data created by the graphic display data creation unit 230.
- the simulation data storage unit 250 is a storage unit that stores data necessary for the simulation input by the simulation data input unit 210 and is used by the simulation unit 220.
- the collected data storage unit 260 is a storage unit for storing data indicating the dynamic status of the buffers, queues and selectors collected by the simulation unit 220, and is stored in the dynamic display data creation unit 230. Used by
- the graphic display data storage unit 270 is a storage unit for storing the graphic display data created by the dynamic display data creation unit 230, and the graphic display data stored in the graphic display data storage unit 270 is stored.
- the graphic display unit 240 performs graphic display on the display device using the data. .
- the control unit 2 8 0 is a processing unit that performs a performance simulation apparatus 2 0 0 overall control, specifically, the movement and function of the control between the functional unit and transfer of data between the storage unit By doing so, 'the performance simulation device 200 functions as one device.
- FIG. 4 is a flowchart showing a processing procedure of the performance simulation apparatus 200 according to the present embodiment.
- a simulation data input unit 210 inputs simulation parameters (step S401). Then, enter the simulation Based on the specification of the application parameters, the simulation unit 220 executes a simulation using the execution history data, and collects data indicating the dynamic status of the buffers, queues and selectors (step S402).
- the simulation unit 220 adds the IDs of the cores and strands that have requested access to the buffers, queues and selectors, and collects data.
- the graphic display data creating section 230 creates graphic display data based on the collected data (step S403).
- the graphic display data creation unit 230 creates display data so that the dynamic status of the buffer, queue, and selector from the arithmetic unit to the memory is displayed on the same time axis and displayed graphically.
- graphic display data is provided so that the dynamic status of buffers, queues and selectors can be displayed in relation to the operation of the entire computer, such as displaying the dynamic status of buffers, queues and selectors by core and strand. create.
- the graphic display unit 240 performs a graphic display on the display device using the created graphic display data (step S404).
- the dynamic status of the buffer and queue selector from the graphic display data creation unit 230 to the memory to the memory are aligned on the same time axis, and displayed in association with the operation of the entire computer.
- the graphic display data is created on the display device, and the graphic display unit 240 performs the graphic display on the display device using the created graphic display data. Data can be easily correlated and grasped.
- FIG. 5 is a flowchart showing a processing procedure of the graphic display data creating unit 230 shown in FIG.
- the processing of the graphic display data creation unit 230 corresponds to the graphic display data creation processing of step S403 shown in FIG.
- the graphic display data generation unit 230 first selects one CPU (step S501), and creates IPC (instruction per cycle) graphic display data for the selected CPU. Yes (step S502). Then, one buffer, queue or selector for graphic display is selected (step S503), and it is checked whether or not the CPU has a multi-core configuration or a multi-strand configuration (step S504).
- the graphic display data of the selected buffer, queue or selector is created (step S505).
- the form of the graphic display is specified by the simulation parameters.
- the display information is created in a display format in which the dynamic status of the selected buffer, queue or selector is understood for each core strand (step S506).
- examples of the display form in which the dynamic state can be understood for each core or strand include a form in which a different graph is used for each core or strand, and a form in which the color is changed.
- step S507 it is checked whether graphic display data has been created for all buffers, queues and selectors specified by the simulation parameters. If not, the process returns to step S503 and returns to step S503. Create graphical display data for any buffers, queues or selectors. On the other hand, if graphic display data has been created for all buffers, queues and selectors specified in the simulation parameters, it is checked whether graphic display data has been created for all CPUs (step S50). 8) If not, return to step S501 and create graphic display data for another CPU.
- graphic display data for buffers, queues and selectors common to all CPUs is created (step S509), and the process ends.
- graphic display data of buffers, queues and selectors common to PUs is created in a form that allows the dynamic status of each CPU to be understood.
- the graphic display data creating unit 230 has a multi-core configuration or a multi-strand configuration
- the graphic display data is displayed in a display form in which the dynamic status of the buffer and the queue selector can be understood for each core or strand.
- the performance simulation apparatus 200 can perform a graphic display for easily comprehending the operation of a computer having complicated memory access such as a CMP or a multi-strand configuration.
- FIG. 6 is a diagram showing an example of a graphic display displayed by the performance simulation apparatus 200 according to the present embodiment. This figure simulates a computer with a CMP configuration in which each of the two CPUs has a second core, and displays the dynamic status of buffers, queues, and selectors from the arithmetic unit to the memory aligned on the same time axis. An example is shown.
- the dynamic status of the buffers, queues and selectors from the operation unit to the memory, the BUSY state of the operation unit buffer, primary cache misses, and buffer entries between the primary and secondary caches are the cores of each CPU Is displayed for each.
- the secondary cache miss and the request cache entry between the secondary cache and memory are displayed as the dynamic status of the buffer common between CPUs. Each is displayed.
- FIG. 7 is a diagram showing another example of a graphic display displayed by the performance simulation apparatus 200 according to the present embodiment.
- the figure shows an example in which one of a plurality of CPUs simulates a computer executing two strands and displays the dynamic status of each buffer, queue and selector.
- the dynamic status of the instruction buffer and the operation unit buffer is graphically displayed for each strand, allowing hardware designers to efficiently design a computer system with a manolech strand configuration. .
- the simulation unit 220 collects data indicating the dynamic status of the buffers, queues and selectors, and the graphic display data creation unit 230 performs buffering from the arithmetic unit to the memory. Since the dynamic status of the cue and the selector were arranged on the same time axis to create graphic display data, and the created data was used by the graphic display unit 240 for graphic display on the display device, The wear designer intuitively grasps the dynamic state of each buffer, queue and selector in relation to the operation of the entire computer, and understands where the phenomenon causing the performance degradation has occurred and the cause of the phenomenon It is easier to do this.
- the simulation unit 220 adds core and strand information to the data indicating the dynamic status of the buffers, queues and selectors, and the display data creation unit 230 Therefore, data to be displayed graphically in a form that allows the dynamic status of queues and selectors to be identified for each core and strand was created, and the graphic display unit 240 graphically displayed the data on the display device using the created data. This enables hardware designers to efficiently design computer systems with complicated memory access such as CMPs and multi-strand configurations.
- the components of the performance simulation apparatus 200 shown in the figure are functionally conceptual. And it does not necessarily need to be physically configured as shown in the figure.
- the specific form of distribution and integration of the performance simulation device 200 is not limited to the illustrated one, and all or a part thereof may be divided into arbitrary units according to various load conditions and usage conditions.
- Functionally or physically distributed 'integrated' can be configured. For example, it is not always necessary to provide the display unit 240 for displaying the display on the display device in the performance simulation device 200, and it is necessary to provide the display device together with the display device on another device connected via a network. You can also.
- the graphic display data created by the graphic display data creation unit 230 may be stored on a magnetic disk or the like, and the simulation processing may be terminated, and only the graphic display of the simulation result may be performed at another time. it can.
- the performance simulation apparatus has been described. However, by realizing the configuration of the performance simulation apparatus by software, a performance simulation program having the same function can be obtained. Therefore, a computer system that executes this performance simulation program will be described.
- FIG. 8 is a diagram showing a computer system that executes a performance simulation program according to the present embodiment.
- the computer system 100 has a main body 101 and a display device 100 for displaying information such as images on a display screen 102 a in accordance with an instruction from the main body 101. 2, a keyboard 103 for inputting various information to the computer system 100, and a mouse 104 for designating an arbitrary position on the display screen 102a of the display device 102.
- a LAN interface connected to a local area network (LAN) 106 or a wide area network (WAN), and a modem 105 connected to a public line 107 such as the Internet.
- LAN local area network
- WAN wide area network
- modem 105 connected to a public line 107 such as the Internet.
- FIG. 9 is a functional block diagram showing the configuration of the main body 101 shown in FIG.
- the main unit 101 includes a CPU 121, a RAMI 22, a ROM 123, a hard disk drive (HDD) 124, a CD-ROM drive 125, an FD drive 126, and an I0 interface 127. , And a LAN interface 128.
- the computer When executing a performance simulation program in the computer system 100, the computer is connected via a portable storage medium such as a floppy disk (FD) 108, CD-ROM 109, DVD disk, magneto-optical disk, IC card, and a LAN interface 128.
- a server or other computer system (PC) connected to the computer system or a database of another computer system connected via the public line 107, and the performance simulation program stored in the database of the computer system 100 To install. Then, the installed performance simulation program is stored in the HDD 124, and is executed by the CPU 121 using the RAM 22, the ROM 123, and the like.
- dynamic data of hardware elements are correlated with each other to create graphic data for graphic display, and the dynamic data of hardware elements is displayed using the generated graphic data. Therefore, it is possible to make it easy for a hardware designer to easily grasp the location where the phenomenon causing the performance degradation occurs and the phenomenon; Further, according to the present invention, there is provided a display device which creates graphic data for graphic display by associating dynamic states of hardware elements with each other and displays the dynamic states of hardware elements using the created graphic data. Since the system is configured to transmit graphic data via a network, hardware designers using display devices can easily understand where the phenomenon that causes performance degradation has occurred and the cause of the phenomenon. It has the effect of being able to.
- graphic data to be displayed in a graphical manner by correlating the dynamic states of hardware elements with each other is created, and the created graphic data is created.
- the display device which displays the dynamic status of the hardware elements, outputs graphic data that is input to the storage device, so the hardware designer using the display device may experience a phenomenon that causes performance degradation. This has the effect that the location and the cause of the phenomenon can be easily grasped.
- the performance simulation apparatus, the performance simulation program, and the performance simulation method according to the present invention are tools used when designing based on the performance evaluation of computer hardware, in particular, CMPs and multi-processors. It is suitable as a tool used when designing computer hardware with complicated memory access such as a strand configuration.
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Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004560586A JPWO2004055672A1 (ja) | 2002-12-18 | 2002-12-18 | 性能シミュレーション装置、性能シミュレーションプログラムおよび性能シミュレーション方法 |
| PCT/JP2002/013251 WO2004055672A1 (ja) | 2002-12-18 | 2002-12-18 | 性能シミュレーション装置、性能シミュレーションプログラムおよび性能シミュレーション方法 |
| AU2002354215A AU2002354215A1 (en) | 2002-12-18 | 2002-12-18 | Performance simulation apparatus, performance simulation program, and performance simulation method |
| US11/103,471 US20050182611A1 (en) | 2002-12-18 | 2005-04-12 | Apparatus and method for simulating performance, and computer product |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/JP2002/013251 WO2004055672A1 (ja) | 2002-12-18 | 2002-12-18 | 性能シミュレーション装置、性能シミュレーションプログラムおよび性能シミュレーション方法 |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US11/103,471 Continuation US20050182611A1 (en) | 2002-12-18 | 2005-04-12 | Apparatus and method for simulating performance, and computer product |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO2004055672A1 true WO2004055672A1 (ja) | 2004-07-01 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/JP2002/013251 Ceased WO2004055672A1 (ja) | 2002-12-18 | 2002-12-18 | 性能シミュレーション装置、性能シミュレーションプログラムおよび性能シミュレーション方法 |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JPWO2004055672A1 (ja) |
| AU (1) | AU2002354215A1 (ja) |
| WO (1) | WO2004055672A1 (ja) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008123519A (ja) * | 2006-11-10 | 2008-05-29 | Sony Computer Entertainment Inc | グラフィックス処理装置、グラフィックスライブラリモジュール、およびグラフィックス処理方法 |
| WO2009096161A1 (ja) * | 2008-01-29 | 2009-08-06 | Panasonic Corporation | プロセッサ性能解析装置、方法及びシミュレータ |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0535704A (ja) * | 1991-06-21 | 1993-02-12 | Fujitsu Ltd | 並列計算機における動作状況解析装置 |
| JPH08180094A (ja) * | 1994-12-27 | 1996-07-12 | Nec Corp | アーキテクチャ・シミュレータ |
| JPH10283226A (ja) * | 1997-03-31 | 1998-10-23 | Sony Computer Entertainment:Kk | コンピユータ機器の解析装置及びその方法 |
| JPH10320246A (ja) * | 1997-05-20 | 1998-12-04 | Hitachi Ltd | プロセッサ方式性能測定方式 |
-
2002
- 2002-12-18 AU AU2002354215A patent/AU2002354215A1/en not_active Abandoned
- 2002-12-18 JP JP2004560586A patent/JPWO2004055672A1/ja active Pending
- 2002-12-18 WO PCT/JP2002/013251 patent/WO2004055672A1/ja not_active Ceased
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0535704A (ja) * | 1991-06-21 | 1993-02-12 | Fujitsu Ltd | 並列計算機における動作状況解析装置 |
| JPH08180094A (ja) * | 1994-12-27 | 1996-07-12 | Nec Corp | アーキテクチャ・シミュレータ |
| JPH10283226A (ja) * | 1997-03-31 | 1998-10-23 | Sony Computer Entertainment:Kk | コンピユータ機器の解析装置及びその方法 |
| JPH10320246A (ja) * | 1997-05-20 | 1998-12-04 | Hitachi Ltd | プロセッサ方式性能測定方式 |
Non-Patent Citations (1)
| Title |
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| REILLY MATT, EDMONDSON JOHN: "Performance simulation of alpha microprocessor", IEEE COMPUTER, vol. 31, no. 5, May 1998 (1998-05-01), pages 50 - 58, XP000766663 * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008123519A (ja) * | 2006-11-10 | 2008-05-29 | Sony Computer Entertainment Inc | グラフィックス処理装置、グラフィックスライブラリモジュール、およびグラフィックス処理方法 |
| US8149242B2 (en) | 2006-11-10 | 2012-04-03 | Sony Computer Entertainment Inc. | Graphics processing apparatus, graphics library module and graphics processing method |
| WO2009096161A1 (ja) * | 2008-01-29 | 2009-08-06 | Panasonic Corporation | プロセッサ性能解析装置、方法及びシミュレータ |
Also Published As
| Publication number | Publication date |
|---|---|
| AU2002354215A1 (en) | 2004-07-09 |
| JPWO2004055672A1 (ja) | 2006-04-20 |
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