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WO2003105189B1 - CONSTRAINED SEMICONDUCTOR DEVICE STRUCTURES ON INSULATION - Google Patents

CONSTRAINED SEMICONDUCTOR DEVICE STRUCTURES ON INSULATION

Info

Publication number
WO2003105189B1
WO2003105189B1 PCT/US2003/018007 US0318007W WO03105189B1 WO 2003105189 B1 WO2003105189 B1 WO 2003105189B1 US 0318007 W US0318007 W US 0318007W WO 03105189 B1 WO03105189 B1 WO 03105189B1
Authority
WO
WIPO (PCT)
Prior art keywords
strained
layer
forming
substrate
collector
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2003/018007
Other languages
French (fr)
Other versions
WO2003105189A3 (en
WO2003105189A2 (en
Inventor
Anthony J Lochtefeld
Thomas A Langdo
Richard Hammond
Matthew T Currie
Glyn Braithwaite
Eugene A Fitzgerald
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Amber Wave Systems Inc
Original Assignee
Amber Wave Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/264,935 external-priority patent/US20030227057A1/en
Application filed by Amber Wave Systems Inc filed Critical Amber Wave Systems Inc
Priority to AU2003237473A priority Critical patent/AU2003237473A1/en
Publication of WO2003105189A2 publication Critical patent/WO2003105189A2/en
Publication of WO2003105189A3 publication Critical patent/WO2003105189A3/en
Publication of WO2003105189B1 publication Critical patent/WO2003105189B1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76259—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along a porous layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/01—Manufacture or treatment
    • H10D10/021—Manufacture or treatment of heterojunction BJTs [HBT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/051—Manufacture or treatment of FETs having PN junction gates
    • H10D30/0516—Manufacture or treatment of FETs having PN junction gates of FETs having PN heterojunction gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6748—Group IV materials, e.g. germanium or silicon carbide having a multilayer structure or superlattice structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6758—Thin-film transistors [TFT] characterised by the insulating substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76275—Vertical isolation by bonding techniques

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Thin Film Transistor (AREA)
  • Bipolar Transistors (AREA)

Abstract

L'invention consiste à combiner les avantages des semi-conducteurs contraints avec les techniques de silicium sur isolant dans la fabrication de substrats et de dispositifs.The invention consists in combining the advantages of constrained semiconductors with silicon on insulator techniques in the manufacture of substrates and devices.

Claims

AMENDED CLAIMS
[received by the International Bureau on 03 March 2004 (03.03.04); claims 188-190, 192-193, 196-198 and 200-202 are replaced by amended claims, claims 1-187, 191, 194-195 and 199 remain unchanged]
187. A method for forming a structure, the method comprising: providing a substrate having a strained semiconductor layer disposed over a dielectric layer; defining a collector in a portion of the strained semiconductor layer; forming a base over the collector; and forming an emitter over the base.
188. The method of claim 187, wherein the strained semiconductor layer is tensilely strained.
189. The method of claim 188, wherein the strained semiconductor layer comprises tensilely strained silicon.
190. The method of claim 187, wherein the strained semiconductor layer is compressively strained.
191. A method for forming a structure, the method comprising: providing a first substrate having a strained layer disposed thereon, wherein the strained layer includes a first semiconductor material; bonding the strained layer to a second substrate, wherein the second substrate comprises a bulk material; removing the first substrate from the strained layer, the strained layer remaining bonded to the bulk semiconductor material; defining a collector in a portion of the strained layer; forming a base over the collector; and forming an emitter over the base, wherein the strain of the strained layer is not induced by the second substrate and the strain is independent of lattice mismatch between the strained layer and the second substrate.
192. The method of claim 191, wherein the strained layer is tensilely strained.
193. The method of claim 192 wherein the strained layer comprises tensilely strained silicon.
194. The method of claim 187 wherein the strained layer is compressively strained.
65
195. A method for forming a structure, the method comprising: providing a relaxed substrate comprising a bulk material and a strained layer disposed in contact with the relaxed substrate, the strain of the strained layer not being induced by the underlying substrate and the strain being independent of a lattice mismatch between the strained layer and the relaxed substrate; defining a collector in a portion of the strained layer; forming a base over the collector; and forming an emitter over the base.
196. The method of claim 195, wherein the strained layer is tensilely strained.
197. The method of claim 196, wherein the strained layer comprises tensilely strained silicon.
198. The method of claim 195 wherein the strained layer is compressively strained.
199. A method for forming a structure, the method comprising: providing a substrate having a strained semiconductor layer disposed over a substrate dielectric layer; forming a transistor in the strained layer by forming a gate dielectric layer above a portion of the strained semiconductor layer, forming a gate contact above the gate dielectric layer, and forming a source region and a drain region in a portion of the strained semiconductor layer, proximate the gate dielectric layer; removing a portion of the strained layer and the substrate dielectric layer to expose a portion of the substrate; defining a collector in the exposed portion of the substrate; forming a base over the collector; and forming an emitter over the base.
200. The method of claim 199, wherein the strained layer is tensilely strained.
201. The method of claim 200, wherein the strained layer comprises tensilely strained silicon.
66
202. The method of claim 199, wherein the strained layer is compressively strained.
67
PCT/US2003/018007 2002-06-07 2003-06-06 Strained-semiconductor-on-insulator device structures Ceased WO2003105189A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2003237473A AU2003237473A1 (en) 2002-06-07 2003-06-06 Strained-semiconductor-on-insulator device structures

Applications Claiming Priority (8)

Application Number Priority Date Filing Date Title
US38696802P 2002-06-07 2002-06-07
US60/386,968 2002-06-07
US60/404,058 2002-08-01
US40405802P 2002-08-15 2002-08-15
US41600002P 2002-10-04 2002-10-04
US60/416,000 2002-10-04
US10/264,935 US20030227057A1 (en) 2002-06-07 2002-10-04 Strained-semiconductor-on-insulator device structures
US10/264,935 2002-10-04

Publications (3)

Publication Number Publication Date
WO2003105189A2 WO2003105189A2 (en) 2003-12-18
WO2003105189A3 WO2003105189A3 (en) 2004-03-04
WO2003105189B1 true WO2003105189B1 (en) 2004-05-21

Family

ID=29741025

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2003/018007 Ceased WO2003105189A2 (en) 2002-06-07 2003-06-06 Strained-semiconductor-on-insulator device structures

Country Status (2)

Country Link
AU (1) AU2003237473A1 (en)
WO (1) WO2003105189A2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7368308B2 (en) 2002-08-23 2008-05-06 Amberwave Systems Corporation Methods of fabricating semiconductor heterostructures

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7119400B2 (en) * 2001-07-05 2006-10-10 Isonics Corporation Isotopically pure silicon-on-insulator wafers and method of making same
EP1649500A2 (en) * 2003-07-31 2006-04-26 Massachusetts Institute Of Technology Method and structure of strain control of sige based photodetectors and modulators
US7161169B2 (en) 2004-01-07 2007-01-09 International Business Machines Corporation Enhancement of electron and hole mobilities in <110> Si under biaxial compressive strain
US7138302B2 (en) * 2004-01-12 2006-11-21 Advanced Micro Devices, Inc. Method of fabricating an integrated circuit channel region
FR2867310B1 (en) 2004-03-05 2006-05-26 Soitec Silicon On Insulator TECHNIQUE FOR IMPROVING THE QUALITY OF A THIN LAYER TAKEN
US7282449B2 (en) 2004-03-05 2007-10-16 S.O.I.Tec Silicon On Insulator Technologies Thermal treatment of a semiconductor layer
FR2867307B1 (en) 2004-03-05 2006-05-26 Soitec Silicon On Insulator HEAT TREATMENT AFTER SMART-CUT DETACHMENT
US20090114950A1 (en) * 2004-05-25 2009-05-07 Koninklijke Philips Electronics N.V. Semiconductor Device and Method of Manufacturing such a Device
WO2006060054A1 (en) * 2004-12-01 2006-06-08 Amberwave Systems Corporation Hybrid semiconductor-on-insulator and fin-field-effect transistor structures and related methods
JP5018066B2 (en) * 2006-12-19 2012-09-05 信越半導体株式会社 Method for manufacturing strained Si substrate

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5013681A (en) * 1989-09-29 1991-05-07 The United States Of America As Represented By The Secretary Of The Navy Method of producing a thin silicon-on-insulator layer
US5240876A (en) * 1991-02-22 1993-08-31 Harris Corporation Method of fabricating SOI wafer with SiGe as an etchback film in a BESOI process
JP2001036054A (en) * 1999-07-19 2001-02-09 Mitsubishi Electric Corp Method for manufacturing SOI substrate
US6323108B1 (en) * 1999-07-27 2001-11-27 The United States Of America As Represented By The Secretary Of The Navy Fabrication ultra-thin bonded semiconductor layers
US6573126B2 (en) * 2000-08-16 2003-06-03 Massachusetts Institute Of Technology Process for producing semiconductor article using graded epitaxial growth
US6603156B2 (en) * 2001-03-31 2003-08-05 International Business Machines Corporation Strained silicon on insulator structures
US6717213B2 (en) * 2001-06-29 2004-04-06 Intel Corporation Creation of high mobility channels in thin-body SOI devices

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7368308B2 (en) 2002-08-23 2008-05-06 Amberwave Systems Corporation Methods of fabricating semiconductor heterostructures
US7375385B2 (en) 2002-08-23 2008-05-20 Amberwave Systems Corporation Semiconductor heterostructures having reduced dislocation pile-ups

Also Published As

Publication number Publication date
WO2003105189A3 (en) 2004-03-04
AU2003237473A1 (en) 2003-12-22
WO2003105189A2 (en) 2003-12-18
AU2003237473A8 (en) 2003-12-22

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