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WO2003030252A2 - Processus de production d'interconnexions - Google Patents

Processus de production d'interconnexions Download PDF

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Publication number
WO2003030252A2
WO2003030252A2 PCT/US2002/029603 US0229603W WO03030252A2 WO 2003030252 A2 WO2003030252 A2 WO 2003030252A2 US 0229603 W US0229603 W US 0229603W WO 03030252 A2 WO03030252 A2 WO 03030252A2
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WO
WIPO (PCT)
Prior art keywords
layer
dielectric film
metal
vertical
stamp
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Ceased
Application number
PCT/US2002/029603
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English (en)
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WO2003030252B1 (fr
WO2003030252A3 (fr
Inventor
Peter D. Brewer
Carl W. Pobanz
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HRL Laboratories LLC
Original Assignee
HRL Laboratories LLC
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Publication of WO2003030252A2 publication Critical patent/WO2003030252A2/fr
Publication of WO2003030252A3 publication Critical patent/WO2003030252A3/fr
Publication of WO2003030252B1 publication Critical patent/WO2003030252B1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/0006—Interconnects
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/0002—Lithographic processes using patterning methods other than those involving the exposure to radiation, e.g. by stamping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76817—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics using printing or stamping techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/16—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of types provided for in two or more different subclasses of H10B, H10D, H10F, H10H, H10K or H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, the devices being individual devices of subclass H10D or integrated devices of class H10
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
    • H05K1/0219—Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors
    • H05K1/0221—Coaxially shielded signal lines comprising a continuous shielding layer partially or wholly surrounding the signal lines
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
    • H05K1/0219—Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors
    • H05K1/0222—Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors for shielding around a single via or around a group of vias, e.g. coaxial vias or vias surrounded by a grounded via fence
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
    • H05K3/005—Punching of holes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00—Three-dimensional [3D] integrated devices
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2201/00—Manufacture or treatment of microstructural devices or systems
    • B81C2201/03—Processes for manufacturing substrate-free structures
    • B81C2201/036—Hot embossing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6605—High-frequency electrical connections
    • H01L2223/6616—Vertical connections, e.g. vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6605—High-frequency electrical connections
    • H01L2223/6616—Vertical connections, e.g. vias
    • H01L2223/6622—Coaxial feed-throughs in active or passive substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6605—High-frequency electrical connections
    • H01L2223/6627—Waveguides, e.g. microstrip line, strip line, coplanar line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6661—High-frequency adaptations for passive devices
    • H01L2223/6677—High-frequency adaptations for passive devices for antenna, e.g. antenna included within housing of semiconductor device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1903—Structure including wave guides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09036—Recesses or grooves in insulating substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09981—Metallised walls
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/01—Tools for processing; Objects used during processing
    • H05K2203/0104—Tools for processing; Objects used during processing for patterning or coating
    • H05K2203/0108—Male die used for patterning, punching or transferring
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
    • H05K2203/1189—Pressing leads, bumps or a die through an insulating layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits

Definitions

  • the present disclosure relates to processes for producing electrical interconnects, and, more particularly, processes for producing high performance transmission lines and interconnects between integrated circuits, discrete devices, and passive components in highly integrated three-dimensional structures.
  • the present disclosure describes, in part, a process for producing high performance interconnects.
  • Three-dimensional structures are being used to provide the needed levels of electronic circuit integration. These three-dimensional structures generally comprise multiple layers of devices along with multiple layers of interconnects to provide electrical connections between the devices.
  • HDMI high-density multilayer interconnect
  • Licari, et al. disclose dielectric layers formed by curtain coating of ultraviolet photoimageable epoxy material and conductor layers formed on the dielectric layers by thin film printing, sputtering or plating.
  • Vertical interconnects vias are formed through the dielectric layers to interconnect the metallization pattern on adjacent conductor layers.
  • the conventional polyimide materials used for RF packaging are not photoimageable.
  • the metallization patterns and interlay er vias must be formed by photolithography, which typically involves applying, imaging, developing and removing a photoresist layer for each metallization and dielectric layer. Many process steps are thereby required for each layer. Plasma etching using photoresist is generally used to form the interconnect structures.
  • Plasma etching methods are limited in their ability to produce complex structures and are also restricted by practical considerations in the vertical depth of the features (a few microns). The depth restriction is due to the low etch rates of most plasma etching schemes for etching polymers ( ⁇ 300 ⁇ A/min) and the lack of robust material masking. Complex structures such as via holes with tapered sidewalls, terraced structures or asymmetrically shaped features are also difficult to produce using plasma etching. Some laboratories have reported forming via holes in polyimide polymer films with sloped sidewalls. The method employed uses tapered erosion masks to obtain sloped etch features, but is limited in the range of sidewall angles and the depth of the etched features. Producing asymmetric structures (i.e., different sidewall profiles) is beyond the capability of current plasma etching technology.
  • RIE is used to remove PMMA residue from the bottom of the molded via and trench regions.
  • the vias and trenches are then metalized by using an evaporation technique.
  • the molded and etched film may be used as a mask to support the formation of recesses in the substrate by an etching process.
  • the recesses in the substrate can then be used to support further processing steps.
  • high performance interconnection is used herein to refer to any electrical interconnection that supports the connection of high speed signals, such as radio frequency signals or digital signals with fast rise and fall times, among components without detrimentally affecting the quality of the signal.
  • One embodiment of the present invention provides a method for producing high performance electrical interconnections in a three-dimensional semiconductor structure, comprising the steps of: applying a dielectric film to a top portion of the three dimensional semiconductor structure; providing a stamp substrate; etching the stamp substrate to create a stamp pattern with raised areas; aligning the stamp substrate to the dielectric film; imprinting the dielectric film with the stamp pattern on the stamp substrate so as to create via regions and trench regions in the dielectric film; removing residual film from the via and trench regions of the dielectric film; and metallizing the via and trench regions of the dielectric film.
  • Another embodiment of the present invention provides a method for producing high performance electrical interconnections in a three dimensional semiconductor structure, comprising the steps of: providing a stamp substrate; etching the stamp substrate to create a stamp pattern with raised areas; providing a dielectric film; aligning the stamp substrate to the dielectric film; imprinting the dielectric film with the stamp pattern on the stamp substrate so as to create via regions and trench regions in the dielectric film; aligning the dielectric film to a top portion of the three dimensional semiconductor structure; bonding the dielectric film to the three dimensional semiconductor structure; removing residual film from the via and trench regions of the dielectric film; and metallizing the via and trench regions of the dielectric film.
  • interconnects such as coplanar interconnects, coaxial waveguides, shielded, horizontal transmission lines, or electrical structures such as external resonators or spiral inductors.
  • interconnects and structures may be formed by stamping dielectric layers and metallizing those layers as described herein. Those skilled in the art would understand that structures other than those specifically described herein may also be fabricated using methods according to the present invention.
  • FIG. 1 illustrates the interconnects provided by embodiments of the present invention used in a highly integrated three dimensional structure.
  • FIGS. 2A - 2M illustrate the steps of a method according to one embodiment of the present invention.
  • FIGS. 3 A - 3G illustrate the steps of a method according to another embodiment of the present invention.
  • FIG. 4 illustrates a coplanar interconnect provided by a method according to an embodiment of the present invention.
  • FIG. 5 illustrates a coaxial wave-guiding provided by a method according to an embodiment of the present invention.
  • FIG. 6 illustrates shielded, horizontal transmission lines provided by a method according to an embodiment of the present invention.
  • FIG. 7 illustrates an external resonator provided by a method according to an embodiment of the present invention.
  • FIG. 8 illustrates a horizontal, spiral inductor provided by a method according to an embodiment of the present invention.
  • FIGS. 9 A - 9D illustrate the steps of a method according to an embodiment of the present invention used to form the coplanar interconnect depicted in FIG. 4.
  • FIGS. 10A - 10H illustrate the steps of a method according to an embodiment of the present invention used to form the coaxial wave-guiding interconnect depicted in FIG. 5.
  • FIG. 11 A - 1 IL illustrate the steps of a method according to an embodiment of the present invention used to form the shielded, horizontal transmission line interconnect depicted in FIG. 6.
  • the purpose of the present invention is to provide a process for producing vertical and horizontal electrical interconnects to be utilized in a three-dimensional structure, such as the three-dimensional structure shown in FIG. 1.
  • Low loss, controlled-impedance transmission lines and interconnects for both intra- and inter-layer signal propagation are critical to highly integrated three-dimensional assemblies for high-speed digital and RF applications.
  • FIG. 1 shows a typical three-dimensional structure for which the interlevel and intralevel connections are provided by the present invention.
  • Interlevel connections are provided by vias 151.
  • the vias 151 provide interlevel connections to integrated circuits 111 in a substrate 110, integrated circuits 121 embedded in polymer layers 120, horizontal interconnections 156, ground planes 130, and sensor elements 141.
  • Intralevel connections are provided by horizontal interconnections 156 on top of polymer layers 120 or contained within recesses in polymer layers 120.
  • the process of the present invention is provided by stamping uniquely shaped through-layer via holes and recesses that serve as structural pre-forms for metallization of complex interconnect structures.
  • the method uses master stamps fabricated from semiconductor materials that provide a low cost means to produce arrays of precisely shaped recesses in polymer films.
  • the stamp pattern is fabricated using standard IC processes, including photolithography, wet chemical etching and/or dry etching techniques. A wide variety of sidewall shapes and angles can be obtained by employing different etching procedures and/or by selecting different crystallographic orientations and masking procedures on the stamp face.
  • the stamping process is capable of forming micron- size structures with high aspect ratios (-100: 1) and can produce features down to 10 nanometers.
  • the present invention represents a major departure from conventional methods for fabricating multiple layer interconnects, which are limited in the complexity and size of possible pre-form structures.
  • Embodiments of the present invention provide an entirely new class of RF and high-speed digital interconnects for highly integrated 3-D systems-on-a-chip, offering improved performance, simplified fabrication, and reduced cost.
  • FIGS. 2A to 2M One embodiment of the process for producing high performance interconnects is illustrated in FIGS. 2A to 2M.
  • a stamp pattern 201 is formed on a single crystal silicon wafer 200.
  • Single crystal silicon wafers are preferred for the formation of the stamp patterns, since the patterns are easily fabricated using existing techniques.
  • the process to delineate the stamp or relief pattern on the wafer uses semiconductor manufacturing techniques such as photolithographic patterning of the wafer surface followed by etching of the silicon using wet-chemical etching or plasma etching techniques.
  • stamps including high aspect (vertical sidewall) structures, crystallographic (angled sidewall) structures, and isotropic (curved sidewall) structures on the stamp. Dry etching methods, in particular, are capable of fabricating dense arrays of highly anisotropic micron-sized structures.
  • the stamp serves to imprint "pre-form" structures in a dielectric film into which metal films will be deposited to form the required electrical interconnects.
  • Stamp patterns may be formed on any material that is harder than the material that is to be imprinted with the stamp. Accordingly, a stamp pattern may be formed in a silicon dioxide layer deposited on a substrate by using semiconductor fabrication techniques. A stamp pattern may also be formed by recasting a formed exotic material into a metal stamp.
  • non-crystalline materials such as silicon dioxide cannot be crystallographically etched and may be limited in the range of available patterns that can be shaped in such non-crystalline materials. Therefore, formation of a stamp pattern directly on single crystal silicon is preferred.
  • the surface of the silicon wafer 200 with the stamp pattern As shown in FIG 2B, the surface of the silicon wafer 200 with the stamp pattern
  • a release agent 202 is treated with a release agent 202.
  • a spin- on release agent such as dimethlypolysiloxane (commercially available as Dura KoteTM produced by Slide Products Inc., Wheeling, Illinois), applied directly on the surface of the silicon wafer 200 containing the etched stamp pattern 201.
  • the release agent is usable up to 300°C.
  • the silicon surface may be coated with a gold film and the surface of the gold film treated with an alkylthiol compound (C ⁇ oH 22 S). This treatment forms a thick monolayer, chemically -bonded film on the stamp surface that acts as an effective release agent. This treatment, however, is limited to less than 150°C.
  • a dielectric film is applied to a substrate before the film is stamped.
  • FIG. 2C shows the dielectric film 210 after application to a substrate 290.
  • the substrate 290 may comprise materials typically used in semiconductor device fabrication, such as silicon or gallium arsenide.
  • the substrate 290 may also contain one or several areas in which semiconductor devices have been created.
  • FIG. 2C shows one such area 291.
  • the dielectric film 210 may be spun-on using a commercial photoresist spinner.
  • the layer 210 may range from 1 ⁇ m to 2 mm, depending upon the interconnects or devices to be contained within the layer.
  • the layer 210 comprises dielectric material, such as SU-8 photoepoxy, benzocyclobutene (BCB), polyimide, or other such materials known in the art.
  • dielectric material such as SU-8 photoepoxy, benzocyclobutene (BCB), polyimide, or other such materials known in the art.
  • SU-8 photoepoxy commercially available from MicroChem Corporation, Newton, Massachusetts, is particularly suited for this application, since SU-8 may be applied in thicknesses from 1 ⁇ m to 2mm.
  • the layer 210 is baked at a low temperature, preferably around 90°C, to produce a soft, imprintable layer.
  • the stamp wafer 200 containing the stamp pattern 201 is aligned to the substrate 290 with the dielectric layer 210.
  • the stamp wafer 200 and the substrate wafer 290 are preferably registered to one another using a commercially available alignment tool with front-to-back alignment capability.
  • the tool should have 0.5-1.0 ⁇ m accuracy for wafer-to-wafer alignment.
  • the wafers are preferably fixed in position to one another using a bonding tool, such as the one used with the EV501 wafer bonding machine from EV Group, Inc. of Schaerding, Austria.
  • the bond tool with the wafers is next transferred into a hot embossing machine to produce imprinted structures.
  • FIG. 2D shows the stamp wafer 200 pressed into the dielectric layer 210.
  • a hot embossing machine such as the EV520HE hot embossing machine from EV Group, performs the molding process under high vacuum conditions with precise temperature and stamping pressure control.
  • the dielectric layer 210 is imprinted at low pressures, typically less than 6.9 atmospheres (100 psi), and at relatively low temperatures, less than 100°C. These parameters are important since high pressures and high temperatures could possibly damage any circuitry on the underlying wafer.
  • FIG. 2E shows the host substrate 290 and dielectric layer 210 after the stamp wafer 200 is removed. In FIG. 2E, openings 211 for the vias and a region 213 for receiving a semiconductor device are shown.
  • the molding process will generally leave a portion of residual film at the bottom of the imprinted via and trench regions as shown at the bottom of the via regions 211 in FIG. 2E.
  • the residual film must be removed to provide connections to the layer underlying the dielectric layer containing interconnections.
  • the residual film left by the imprinting process is less than one micron thick and is easily removed by a short exposure to a high density argon/oxygen plasma.
  • the surface of the dielectric layer 210 is patterned with photoresist to expose those areas from which the residual film is to be etched. With high density argon/oxygen plasma etching, etch rates of 300 ⁇ A/min can be accomplished, so the etch exposure is relatively short.
  • FIG. 2F shows the dielectric layer 210 after the residual film has been removed from the bottom of the via regions 211.
  • FIG. 2G also shows the deposit of a semiconductor device 217 in the dielectric layer 210.
  • the vias 215 may be created by the vacuum deposition of metal films, which is well known in the semiconductor industry.
  • the metal films may be deposited by either an evaporation or sputtering mechanism.
  • the metal films may comprise one or more of the following metals: titanium (Ti), gold (Au), chromium (Cr), nickel (Ni), platinum (Pt), and aluminum (Al).
  • Ti titanium
  • Au gold
  • Cr chromium
  • Ni nickel
  • Al aluminum
  • One typical metal film consists of a 50 ⁇ A layer of Ti and a 1500A layer of Au. The specific thickness of individual layers will depend upon stress and strain considerations within the structure.
  • Masking of the dielectric layer 210 can either be done prior to the deposit of the metal film, in a lift-off process well-known in the art, or after the deposit of metal, in a subtractive process also well known in the art, to form the metal lines on the surface of the dielectric layer 210 and in the via regions 211.
  • Metallization of the interconnect regions is typically accomplished by a multi-step process where a thin metal film, or seed layer, is deposited by vacuum deposition, which is then followed by the formation of a thicker metal film using an electro-chemical process. Other processes known in the art of semiconductor manufacturing may also be used for metallization.
  • Formation of multiple interconnect layers according to this first embodiment of the present invention is accomplished by repeating the steps described above and shown in FIGS. 2H - 2M.
  • FIG. 2H the deposit of a second dielectric layer 230 on top of the stamped and metallized dielectric layer 210 and substrate 290 is shown.
  • the second dielectric layer 230 may be deposited by the spin-on process described above.
  • a second stamp wafer 250 with a second stamp pattern 251 is created as shown in FIG. 21.
  • the second stamp wafer 250 is then used to stamp the second dielectric layer 230 as shown in FIG. 2J.
  • FIG. 2L shows the removal of the residual film at the bottom of these regions 231, 233 to provide access to the interconnect regions 215 and circuit areas 219 in the first dielectric layer 210. Removal of the residual film in the second dielectric layer 230 is accomplished using the same techniques described above for the first dielectric layer 210. Metallization of the via regions 231 and the interconnect trench regions 233 is accomplished using the same techniques as for the first dielectric layer 210. The structure with two layers of interconnects resulting from the processes described above is shown in FIG. 2M.
  • sheets of polymer dielectric film may be used to provide the dielectric layers to be molded by stamp wafers. Rather than using a spin-on process to form each dielectric layer, a sheet of polymer dielectric film is positioned and bonded to a host substrate (or an underlying dielectric layer). The dielectric film is then molded as described above. Using sheets of polymer dielectric film with decreasing glass transition temperatures, i.e., temperatures at which the film can be molded, allows the upper layers to be molded without affecting the lower layers.
  • FIGS. 3A to 3G Another embodiment of the process for producing high performance interconnects according to the present invention is illustrated in FIGS. 3A to 3G.
  • a stamp pattern 301 is formed on a stamp substrate wafer 300.
  • the stamp pattern can be formed using standard integrated circuit processes to provide the necessary patterns.
  • the materials for the stamp substrate wafer 300 is chosen from those materials that will support the construction of semiconductor-like structures.
  • the substrate wafer 300 containing the stamp pattern 301 is then positioned above a sheet of polymer dielectric film 310.
  • the sheet of polymer dielectric film 310 is not spun onto an underlying substrate before stamping. Instead, the sheet 310 is separately provided and is stamped prior to its attachment to an underlying circuit- carrying substrate. Micro-stamping processes similar to those described above are then used to stamp the dielectric film 310. As above, the stamping process forms the pre-form structures in the polymer dielectric film 310 that will be used for interconnect metallization.
  • FIG. 3C shows the application of the stamp substrate 300 to the polymer dielectric film 310.
  • the polymer dielectric film 310 is preferably a thermoplastic polymer film, commercially available in a variety of compositions. Such films include polyimide, ethylenechlorotrifluroethylene, polyvinylidene fluoride, and polyetherimide.
  • a bonding tool is used to fix the stamp substrate wafer 300 next to the dielectric film 310.
  • the bond tool with the stamp wafer 300 and the dielectric film 310 is then transferred into a hot embossing machine.
  • the embossing machine performs the required molding process for the separate dielectric film 310 using temperatures and pressures similar to those used for molding the dielectric layer on the substrate described above. After stamping and separation of the stamp wafer 300 from the dielectric film 310, the dielectric film 310 is allowed to cool and harden into its final form. Since the dielectric film 310 is fully polymerized, a curing step may not be required.
  • the thermoplastic properties of the materials used for the dielectric film 310 allows the film 310 to be reversibly softened and hardened by heating above and cooling below the glass transition temperature of the materials.
  • FIG. 3D illustrates the polymer dielectric film after the removal of the stamp pattern, in which the polymer dielectric film 310 contains a plurality of recesses 311 and 312.
  • the shallow recesses 312 provide the structures required to support intralayer connections, i. e. horizontal interconnects.
  • the deep recesses 311 provide the structures required to support interlayer connections, i.e. vertical interconnects or vias.
  • FIG. 3E shows the placement of the stamped dielectric film 310 on the top of the three dimensional structure. In FIG.
  • the stamped dielectric film 310 is placed on top of a second dielectric film 330 that has already been stamped, metallized, and contains one or more integrated circuits 332.
  • the second dielectric film 330 may be disposed on a circuit carrying substrate 320 with one or more integrated circuit regions 322 to form a three-dimensional structure.
  • a commercially available wafer bonder/aligner equipped with double-sided alignment capability may be used to precisely register and attached the patterned dielectric film 330 to the top layer of the three-dimensional structure.
  • FIG. 3F shows the dielectric film 310 after the polymer residue 313 has been removed. Removal of this residue is performed using the same techniques described above, that is, patterning with photoresist and removal with plasma etching or laser ablation. Removal of the polymer residue 313 exposes vias 331 or integrated circuits 332 in the layer 330 below.
  • FIG. 3G illustrates the metallization of the interconnect regions 311, 312.
  • Metallization in this embodiment of the process according to the present invention is performed in the same manner as previously discussed. Vacuum deposition is used to apply the metal and a lift-off process or subtractive process is used to form the vias and interconnect trenches.
  • High-performance interconnections are essential for horizontal transport of DC and RF signals among embedded circuits within a layer and for vertical connectivity between layers in a multiple layer structure.
  • the multiple layers of metallized dielectrics of the present invention enable the creation of a wide variety of transmission lines and interconnects.
  • Such structures include conductors with one or two ground planes (microstrip and stripline, respectively), coplanar strips (CPS) and three-conductor coplanar waveguide (CPW). These transmission lines are used extensively in MMICs and conventional RF printed circuits. Using low-loss dielectrics and mode suppression techniques developed for millimeter-wave MMICs and subsystems, operation at frequencies up to 100 GHz will be practical.
  • the vertical dimension adds another degree of freedom through which shielded structures such as coaxial lines and transmission line vias can be formed, as illustrated in FIG. 1.
  • the capacity for vertical RF interconnects between levels with controlled impedance, coupling, and radiation characteristics is one of the unique potential benefits of the present invention.
  • FIGS. 4 - 8 illustrate some of the complex interconnect structures that may be fabricated using the methods described above.
  • a coplanar interconnect between layers can be provided by the present invention.
  • three metal lines 401 form a three conductor coplanar waveguide disposed on a lower layer.
  • Three vertical interconnects 411 provide the electrical connections to a three conductor coplanar waveguide comprising three metal lines 421 formed on an upper layer.
  • FIGS. 9 A - 9 D illustrate the steps used to fabricate the coplanar interconnect illustrated in FIG. 4.
  • the first step is the formation of metal lines 401 on a lower layer 400.
  • the lower layer 400 may comprise a semiconductor substrate or a previously deposited polymer layer.
  • the metal lines 401 may be formed by semiconductor fabrication techniques well known in the art.
  • an upper polymer layer 450 is then deposited on top of the lower layer 400 and the metal lines 401.
  • the polymer layer 450 may comprise polyimide, BCB, SU-8, or other suitable thermoplastic material chosen for suitable RF or other electrical properties and with a glass transition temperature lower than that of the layer 400 below (if it also comprises thermoplastic material).
  • FIG. 9A is the formation of metal lines 401 on a lower layer 400.
  • the lower layer 400 may comprise a semiconductor substrate or a previously deposited polymer layer.
  • the metal lines 401 may be formed by semiconductor fabrication techniques well known in the art.
  • an upper polymer layer 450 is then deposited on top
  • FIG. 9C illustrates the formation of via holes 411 in the upper polymer layer 450 using the imprinting methods described above.
  • the imprinting stamp is accurately aligned to the lower layer 400 to ensure proper placement of the via holes above the metal lines 401.
  • the imprinting allows deep via holes 411 to be created with high aspect ratios, so that the second polymer layer 450 may be relatively thick, if required for proper device operation.
  • FIG. 9D illustrates the final step in the fabrication of the coplanar waveguide interconnects.
  • the via holes 411 are filled with metal and metal is also deposited to form the metal lines 421 on the upper layer 450.
  • the three upper layer metal lines 421 provide the upper layer coplanar waveguide.
  • Coaxial connections can also be provided by the present invention as shown in FIG. 5.
  • a lower layer coaxial transmission line is formed by a center conductor 502 located between two shield lines 501.
  • a coaxial connection to an upper layer device, such as a patch antenna 530 is provided by a center conductor vertical interconnect 512 connected to the center conductor 502 and a ground shield 511 which is connected to the shield lines 501.
  • the center conductor vertical interconnect may then be connected to a patch antenna 530, while the shield structure 511 is connected to a layer of metal 520 that serves as a ground plane for the patch antenna 530.
  • FIGS. 10A - 10H illustrate the fabrication of the coaxial connection depicted in FIG. 5.
  • the first step, as shown in FIG. 10A is the formation of the center conductor 502 and the shield lines 501 on a lower layer 500.
  • the lower layer 500 may comprise a semiconductor substrate or a previously deposited polymer layer.
  • the center conductor 502 and the shield lines 501 may comprise metal lines formed by semiconductor fabrication techniques well known in the art.
  • FIG. 10B depicts the next step, where an upper polymer layer 550 is deposited on top of the lower layer 500.
  • the upper polymer layer 550 is then stamped to form a center conductor recess 552 and a coaxial ground shield recess 551, as shown in FIG. IOC.
  • the high aspect ratios provided by the methods according to the present invention allow these complex structures to be created. Accurate alignment of the imprinting stamp with a host circuit wafer carrying the lower layer 500 allows the recesses to be closely aligned with the center conductor 502 and the shield line 501.
  • FIG. 10E illustrates the fabrication of the ground plane 520 by metal deposition, such as by the evaporation of titanium/gold or gold onto the upper polymer layer 550. Lift-off techniques may be employed to create a cleared circular area 522 (free of metal) for the center conductor vertical interconnect 512 to pass through the ground plane 520.
  • FIG. 10F illustrates the formation of a second polymer layer 560 on top of the first polymer layer 550.
  • the material for the second polymer layer 560 may again be chosen from polyimide, BCB, SU-8, or other thermoplastic materials with a lower glass transition temperature than the first polymer layer 550.
  • a second layer center conductor recess 562 may be formed in the second polymer layer 560 by the stamping techniques previously described.
  • the second layer center conductor recess 562 may also be formed by semiconductor techniques such as plasma etching.
  • the second layer center conductor recess 562 is then filled with metal, such as gold, or titanium/gold, to complete the formation of the center conductor 512, as shown in FIG. 10G.
  • the final step in the formation of the coaxial structure shown in FIG. 5 is the deposition of metal on top of the second polymer layer 560 to form the patch antenna 530, as shown in FIG. 10H.
  • Shielded horizontal transmission lines can be provided by the present invention as shown in FIG. 6.
  • horizontal interconnects 610 are positioned between a lower ground plane 620 and an upper ground plane 640.
  • the horizontal interconnects 610 are further shielded from each other by vertical ground shields 630 disposed between the horizontal interconnects 610.
  • Lower vertical interconnects 601 and upper vertical interconnects 603 are insulated from the lower ground shield 620 and the upper ground shield 640 and connect to the horizontal interconnects 610.
  • FIGS. 11 A - 1 IL One method for forming the shielded horizontal transmission line structure depicted in FIG. 6 is shown in FIGS. 11 A - 1 IL.
  • the first step is depicted in FIG. 11 A, where the lower level interconnects 601 are formed within a lower polymer layer 650 by the stamping techniques previously described or by semiconductor techniques well- known in the art.
  • the lower ground shield 620 is then deposited on top of the lower polymer layer 650.
  • the lower level interconnects 601 may have been chemically-mechanically polished or otherwise prepared to ensure a good electrical connection between the lower level interconnects 601 and the metal deposited on top of the lower polymer layer 620.
  • Lift-off techniques or other metal removal techniques are used to remove the metal from the lower ground shield 620 around the lower vertical interconnects 601 to form insulating gaps between the lower vertical interconnects 601 and the lower ground shield 620, as shown in FIG. 11 C.
  • a middle polymer layer 655 is then deposited on top of the lower ground shield
  • middle polymer layer 655 is then stamped and further fabricated using the techniques previously described to provide the vertical shield recesses 631 and the horizontal interconnect recesses 611 as shown in FIG. 1 IE. Accurate alignment of the stamp or of the imprinted middle polymer layer 655 ensures proper placement of the interconnect structures.
  • the vertical shield recesses 631 and the horizontal interconnect recesses 611 are then metalized as shown in FIG. 1 IF.
  • Multiple metallization steps are preferably used to deposit all of the metal required to completely fill the vertical shield recesses 631 to form the vertical shields 630, while only partially filling the horizontal interconnect recesses 611 to form the horizontal interconnects.
  • additional polymer is deposited to provide insulating layer sections 651 above the horizontal interconnects 610 as shown in FIG. 11 G.
  • FIG. 11H shows the structure from the side of the horizontal interconnects 610 where the upper vertical interconnects 603 are to be provided after the upper ground shield 640 is deposited on top of the middle polymer layer 655.
  • Chemical -mechanical polishing or other preparation techniques may be used to ensure good electrical connectivity between the vertical shields 630 and the upper ground shield 640.
  • Lift-off techniques or other metal removal techniques are used to provide upper interconnect holes 607 in the upper ground shield 640, as shown in FIG. 111.
  • An upper polymer layer 660 is then deposited on top of the upper ground shield 640 and to fill in the upper interconnect holes 607, as shown in FIG. 11 J.
  • Etching is then used to remove the polymer material above the horizontal interconnects 610 to provide upper interconnect recesses 609, as shown in FIG. 1 IK.
  • Plasma etching is preferred for the removal of the polymer material, since the polymer materials in the upper polymer layer 660 and the middle polymer later 655 are likely to have different glass transition temperatures.
  • the upper interconnect recesses 609 are then filled with metal to form the upper vertical interconnects 603, as shown in FIG. 1 IL.
  • FIG. 7 shows a printed-metal spiral inductor 701 used for tuning a RF integrated circuit connected to an integrated circuit by vias 711.
  • the process provided by the present invention results in integration technology that is superior to low-temperature cofired ceramic (LTCC), for example, that is typically used in such an application.
  • LTCC low-temperature cofired ceramic
  • Micro-stamped vias provide a vertically integrated structure that is more compact and repeatable, and produces smaller and more consistent electrical parasitic effects.
  • the present invention provides the capability to produce a horizontal spiral inductor, as shown in FIG. 8.
  • the spiral inductor is provided by the interconnection of lower layer metal lines 801, vertical interconnects 806, and upper layer metal lines 811.
  • the techniques for forming the horizontal inductor shown in FIG. 8 are similar to those used to form the coplanar interconnect shown in FIG. 4.

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Abstract

La présente invention concerne un procédé de fabrication de connexions électriques verticales et horizontales de haute performance. Dans une structure semiconductrice en trois dimensions. Un film diélectrique est imprimé avec un motif estampé sous vide poussé, à température précise et sous commande de pression de l'estampage précise. Ce motif estampé peut être formé sur un substrat par des techniques de fabrication de semiconducteur. Lorsque ce film diélectrique est estampé, le film diélectrique résiduel est retiré de façon à libérer l'accès à une couche sous-jacente. Des régions de trous d'interconnexion et de tranchées formées dans ce film diélectrique par estampage sont ensuite métallisées de façon à obtenir des interconnexions de haute performance. On obtient des couches multiples d'interconnexions dans la structure en trois dimensions par un empilement des couches de films diélectriques métallisés et estampés, les unes sur les autres.
PCT/US2002/029603 2001-09-28 2002-09-18 Processus de production d'interconnexions Ceased WO2003030252A2 (fr)

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US9583473B2 (en) 2013-07-16 2017-02-28 Qualcomm Incorporated Complete system-on-chip (SOC) using monolithic three dimensional (3D) integrated circuit (IC) (3DIC) technology
DE102016116499A1 (de) 2016-09-02 2018-03-08 Infineon Technologies Ag Verfahren zum Bilden von Halbleiterbauelementen und Halbleiterbauelemente
DE102016116499B4 (de) 2016-09-02 2022-06-15 Infineon Technologies Ag Verfahren zum Bilden von Halbleiterbauelementen und Halbleiterbauelemente
US11393784B2 (en) 2016-09-02 2022-07-19 Infineon Technologies Ag Semiconductor package devices and method for forming semiconductor package devices

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