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WO2003019574A3 - Procede de controle haute tension d'un circuit integre - Google Patents

Procede de controle haute tension d'un circuit integre Download PDF

Info

Publication number
WO2003019574A3
WO2003019574A3 PCT/DE2002/001807 DE0201807W WO03019574A3 WO 2003019574 A3 WO2003019574 A3 WO 2003019574A3 DE 0201807 W DE0201807 W DE 0201807W WO 03019574 A3 WO03019574 A3 WO 03019574A3
Authority
WO
WIPO (PCT)
Prior art keywords
word
address bits
memory structure
complements
screening
Prior art date
Application number
PCT/DE2002/001807
Other languages
German (de)
English (en)
Other versions
WO2003019574A2 (fr
Inventor
Friedemann Eberhardt
Hans-Peter Klose
Original Assignee
Bosch Gmbh Robert
Friedemann Eberhardt
Hans-Peter Klose
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Bosch Gmbh Robert, Friedemann Eberhardt, Hans-Peter Klose filed Critical Bosch Gmbh Robert
Publication of WO2003019574A2 publication Critical patent/WO2003019574A2/fr
Publication of WO2003019574A3 publication Critical patent/WO2003019574A3/fr

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/30—Accessing single arrays
    • G11C29/34—Accessing multiple bits simultaneously
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger

Landscapes

  • Tests Of Electronic Circuits (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

L'invention concerne des mesures permettant d'améliorer significativement l'efficacité du contrôle haute tension de circuits intégrés dotés d'une structure de mémoire et d'un décodeur de mots. Plusieurs cellules de mémoire (11) de la structure de mémoire (1) sont respectivement rassemblées en un mot. Les sorties du décodeur de mots (2) sont respectivement reliées à un mot de la structure de mémoire (1) par l'intermédiaire de lignes de mots (12). Tout d'abord, le décodeur de mots (2) détermine, au moyen d'une logique de circuit, les compléments de bits d'adresse à partir des bits d'adresse leur étant adjacents. Puis, ce décodeur de mots (2) détermine pour chaque mot de la structure de mémoire (1), au moyen de ladite logique de circuit et à partir des bits d'adresse ainsi que de leurs compléments, un signal de ligne de mots équivalant à 0 ou 1, et peut ainsi isoler un mot de la structure de mémoire (1) pour un accès, c'est-à-dire pour une opération de lecture et/ou une opération d'écriture. Lors d'un contrôle haute tension, la tension d'alimentation est augmentée pour différents états de circuit appelés vecteurs de contrôle. Selon la présente invention, la logique de circuit comprend des moyens à activation sélective permettant de mettre des bits d'adresse au niveau de leurs compléments, de sorte qu'un mode d'essai puisse être activé pour produire des vecteurs de contrôle. Selon ce mode, tous les bits d'adresse sont mis au même niveau et les compléments des bits d'adresse sont également mis au même niveau que les bits d'adresse.
PCT/DE2002/001807 2001-08-21 2002-05-18 Procede de controle haute tension d'un circuit integre WO2003019574A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE2001140853 DE10140853B4 (de) 2001-08-21 2001-08-21 Verfahren zum Hochvolt-Screening einer integrierten Schaltung
DE10140853.6 2001-08-21

Publications (2)

Publication Number Publication Date
WO2003019574A2 WO2003019574A2 (fr) 2003-03-06
WO2003019574A3 true WO2003019574A3 (fr) 2003-05-22

Family

ID=7696067

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2002/001807 WO2003019574A2 (fr) 2001-08-21 2002-05-18 Procede de controle haute tension d'un circuit integre

Country Status (2)

Country Link
DE (1) DE10140853B4 (fr)
WO (1) WO2003019574A2 (fr)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4956816A (en) * 1986-03-31 1990-09-11 Kabushiki Kaisha Toshiba Non-volatile semiconductor memory having improved testing circuitry
US5432744A (en) * 1992-12-07 1995-07-11 Nec Corporation Dynamic semiconductor memory circuit
EP0878804A2 (fr) * 1997-05-15 1998-11-18 STMicroelectronics, Inc. Architecture de réseau de mémoire dynamique à accès aléatoire à multiple transistors avec rafraichissement simultané d'une pluralité de cellules de mémoire pendant une opération de lecture
US5910921A (en) * 1997-04-22 1999-06-08 Micron Technology, Inc. Self-test of a memory device
US6205067B1 (en) * 1997-03-27 2001-03-20 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device having burn-in mode operation stably accelerated
US6215712B1 (en) * 1997-05-30 2001-04-10 Fujitsu Limited Semiconductor memory device capable of multiple word-line selection and method of testing same

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000156096A (ja) * 1998-11-20 2000-06-06 Fujitsu Ltd 半導体記憶装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4956816A (en) * 1986-03-31 1990-09-11 Kabushiki Kaisha Toshiba Non-volatile semiconductor memory having improved testing circuitry
US5432744A (en) * 1992-12-07 1995-07-11 Nec Corporation Dynamic semiconductor memory circuit
US6205067B1 (en) * 1997-03-27 2001-03-20 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device having burn-in mode operation stably accelerated
US5910921A (en) * 1997-04-22 1999-06-08 Micron Technology, Inc. Self-test of a memory device
EP0878804A2 (fr) * 1997-05-15 1998-11-18 STMicroelectronics, Inc. Architecture de réseau de mémoire dynamique à accès aléatoire à multiple transistors avec rafraichissement simultané d'une pluralité de cellules de mémoire pendant une opération de lecture
US6215712B1 (en) * 1997-05-30 2001-04-10 Fujitsu Limited Semiconductor memory device capable of multiple word-line selection and method of testing same

Also Published As

Publication number Publication date
WO2003019574A2 (fr) 2003-03-06
DE10140853A1 (de) 2003-03-20
DE10140853B4 (de) 2004-11-11

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