WO2003013201A1

WO2003013201A1 - Method for forming device-landing pad of multi-layered printed circuit board

Info

Publication number: WO2003013201A1
Application number: PCT/KR2001/001480
Authority: WO
Inventors: Seong Heon Lee
Original assignee: Dap Corporation
Priority date: 2001-08-02
Filing date: 2001-08-31
Publication date: 2003-02-13
Also published as: KR20030011433A

Abstract

This invention relates to a method for forming device-landing pad of multi-layered PCB, and more particularly, to a method for foring device-landing pad of a multi-layered PCB by plugging a via hole formed by laser drilling for device-landing and/or forming a via and conductive layer. In order to achieve the objects of the present invention, the method for forming device-landing pad of multi-layered PCB including the step of forming at least one via hole for interconnecting different conductive layer patterns, the method comprising the steps of: forming a first external conductive layer over the a surface of the multi-layered PCB having the via hole; forming a via by plugging the via hole; forming masking layer over a surface of the conductive layer; etching back the first external conductive layer for forming conductive pattern; and removing the masking layer.

Description

METHOD FOR FORMING DEVICE-LANDING PAD OF MULTI-LAYERED

PRINTED CIRCUIT BOARD

BACKGROUND OF THE INVENTION

(a) Field of the Invention

This invention relates to a method for forming device-landing pad of

multi-layered printed circuit board (PCB), and more particularly, to a method for

forming device-landing pads of a multi-layered PCB capable of improving an

electrical contact reliability of components such as Integrated Circuit (IC), Ball

Grid Array (BGA) and etc. as well as soldering property of the device-landing pad by plugging a via hole formed on the PCB and forming plating layer over

the landing pad.

(b) Description of the Related Art

A PCB is a primary based device of electronic components being manufactured in the various fields at present. Currently, the multi-layered PCB

as a thin and small size is applied to a semiconductor package substrate such

as cellular phone, PCS, IMT 2000, Notebook Computer, Palmtop Computer, Camcorder, BGA (ball grid array), CSP (chip scale packaging) and MCM (multi chip module).

In the conventional method for manufacturing the multi-layered PCB,

referring to Fig. 1a to Fig. 1g, the conventional method comprises essentially

the steps of forming a multi-layered substrate as a desired number of layer by forming a plurality of conductive layer insulated each other through the

processes a1-a9, the step of forming a via hole by using a laser drill through the processes a10-a18, and forming a exposed conductive pattern for interconnecting through the processes a19-a23.

Referring to Fig. 1 a to Fig. 1g, the step of forming the multi-layered PCB

comprises the steps of forming a buried via hole 2 through a substrate 1 by

mechanical drilling at the process a1 , forming a first conductive layer 3 on a

surface of the buried via hole and the substrate by plating at least one time at

the process a2, forming a buried via 4 by plugging the buried via hole with a

filler 4 at the process a3, hardening the filler at a predetermined temperature

and time at the process a4, flattening the surface of the substrate and the

buried via by grinding at the process a5, applying a photoresist film 5 over the

buried via 4a and the first conductive layer 3 at the process a6, drawing a

pattern on the photoresist film 5 for forming a mask layer at the process a7,

forming a first conductive pattern 3aby etching the first conducive layer at the

process a8, and removing the film from the first conductive pattern at the

process a9. And, a substrate having multi-layered conductive patterns can be

acquired by repeating the processes a1 to a9 at need.

The step of forming the via hole comprises the steps of forming a

second conductive layer 7 on the substrate at a high temperature and pressure

at the process a10, applying a photoresist film 8 over the surface of the first

conductive layer at the process a1 1 , drawing a pattern on the photoresist film

8for forming a masking layer at the process a12, forming a second conductive

pattern 7aby etching the second conductive layer and removing the film from

the second conductive pattern at the process a13, forming a third conductive

layer over the second conductive pattern at a high temperature and pressure at

the process a14, applying a photoresist film 1 1 over the surface of the second conductive layer at the process a15, drawing a pattern on the photoresist film

11 for forming masking layer at the process a16, forming a third conductive

pattern 10a and a laser point 12 by etching the third conductive layer and

removing the film from the third conductive pattern at the process a17, and

forming a via hole 13 by laser drilling at the laser point at the process a18.

The step of forming the exposed conductive pattern for interconnecting

comprises the steps of forming a external conductive layer 14 over the multi-

layered board at the process a 19, applying a photoresist film 15 over the

surface of the external conductive layer at the process a20, drawing a pattern

on the photoresist film for forming a masking layer at the process a21 , forming a

external conductive pattern 14a and a via pad by etching the external

conductive layer 14 and third conductive layer and removing the film from the

external conductive pattern at the process a22, and depositing a solder-resist

on the etch back portion of the multi-layered board at the process a23. As the above, Fig. 2a is a photograph showing the multi-layered PCB

according to the conventional method, and Fig. 2b is an enlarged photo

showing a portion A of Fig. 2a, and Fig. 3 is an enlarged cross-sectional view of

the via pad formed on the multi-layered PCB of Fig. 2a. Referring to Fig. 2a, Fig.

2b and Fig. 3, however, because the conventional laser via hole has a little contact region for bonding electronic components and laser via hole, the

electronic components cannot be accurately landed and bonded to the laser via hole such that the prior art reduces the reliability of the multi-layered PCB. Furthermore, if IC and BGA are landed on the PCB, a solder ball is created at

the lower end of the PCB such that prior art has a disadvantage generating a short between components and a solder ball.

SUMMARY OF THE INVENTION

The present invention has been made in an effort to solve the above

problems of the prior art.

An object of the present invention is to provide a method for forming

device-landing pad of multi-layered printed circuit board (PCB) capable of

improving connecting and bonding property between multi-layered PCB and

electronic components by extending contact region of electronic components

and a board and a via hole created on the multi-layered PCB for landing electronic components.

Another object of the present invention is to provide a method for forming device-landing pad of multi-layered PCB capable of improving an electric connection reliability of components by enhancing the conductivity of an

external conductive pattern.

In order to achieve the above objects, the method for forming device-

landing pad of multi-layered PCB including the step of forming at least one via

hole for interconnecting different conductive layer patterns according to the

present invention, the method comprising the steps of: forming a first external

conductive layer over the a surface of the multi-layered PCB having the via hole; forming a via by plugging the via hole; forming masking layer over a

surface of the conductive layer; etching back the first external conductive layer for forming conductive pattern; and removing the masking layer.

Also, the method for forming device-landing pad according to the present invention further comprises a step of grinding the via for flattening a surface of the via.

The method for forming device-landing pad according to the present

invention further comprises a step of forming a second external conductive layer over the first external conductive layer and the via.

BRIEF DESCRIPTION OF THE DRAWINGS

The above objects and other features of the present invention will

become more apparent by describing the preferred embodiment thereof with

reference to the accompanying drawings, in which:

Fig. 1a to Fig. 1g show respective processes for illustrating the method

for forming the multi-layered PCB according to a prior art.

Fig. 2a is a photograph showing the multi-layered PCB manufactured by the prior art

Fig. 2b is an enlarged photograph showing a portion A of Fig. 2a.

Fig. 3 is a cross-sectional view of the via hole formed on the multi- layered PCB of Fig. 2a

Fig. 4a to Fig. 4h show respective processes for illustrating the method

for forming device-landing pad of the multi-layered PCB according to a

preferred embodiment of the present invention. Fig. 5a is a photograph showing device-landing pads of the multi-layered

PCB manufactured according to the present invention.

Fig. 5b is an enlarged photograph showing a portion B of Fig. 5a.

Fig. 6 is a cross-sectional view of device-landing pad formed on the multi-layered PCB of Fig. 5a.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

A preferred embodiment of the present invention will be described

hereinafter with reference to the accompanying drawings. A preferred embodiment of the present invention provides the method

for forming device-landing pad for mounting electronic components on the multi-

layered PCB having the conductive pattern over at least three layers.

Particularly, the present invention discloses the conductive pattern formed with

three conductive layers in the multi-layered PCB, however the present invention

is not limited by the embodiments to be described hereinbelow, and it should be

obvious to a person skilled in the art that modifications and alterations could be

made to the embodiments hereinbelow.

Fig. 4a to Fig. 4h show respective processes for illustrating the method for forming device-landing pad of the multi-layered PCB according to a preferred embodiment of the present invention.

Referring to Fig. 4a to Fig. 4h, the method for forming device-landing

pad of the multi-layered PCB comprises the steps of forming a first conductive

pattern 103aon a substrate 101 through the processes b1-b9, forming a second

conductive pattern 107a on the surface of the board through the processes b10-

b13, forming a third conductive pattern 110a through the processes b13-b17, forming at least one via hole 113 using a laser drill at the process b18, forming

a first external conductive layer 114 for interconnecting the conductive patterns b19, forming a via 120 by plugging the via hole with a filler such as silver paste, copper paste, or conductive resin at the process b20, grinding the via for flatting

a surface thereof at the process b21 , forming a second external conductive

layer 121 over the first external conductive layer and via at the process b22,

and forming an exposed conductive pattern through the processes b23-b26.

The method for forming the device-landing pad according to the

preferred embodiment of the present invention will be described in more detail

hereinbelow.

Since the processes from b1 to b19 for forming a plurality of conductive

patterns interconnected each other on the substrate are well known in the multi-

layered PCB-manufacturing field as explained in the prior art, only the features

of the present invention will be described.

Once the third conductive pattern 1 10a and laser point 112 are formed

by etching the third conductive layer 110 and removing the photoresist 111 at

the process b17, The via hole 1 13 is formed at the laser point 112 using the

laser drilling at the process b18.

Next, the first external conductive layer 114 is formed over the surface

of the multi-layered board by the copper plating such that the third conductive layer 1 10 is connected to the first or second conductive pattern 103a or 107a at

the process b19.

The via hole 1 13 is plugged with conductive material such as silver

paste, copper paste, or conductive resin so as to form the via 120 at the process b20 and then the via 120 is flatten by grinding at the process b21.

After the surface of the multi-layered board is flattened, the second

external conductive layer 121 is formed over the surface of the first external conductive layer 114 and the via 120 by the copper plating again at the process b22.

Next, a photoresist film 115 is applied over a surface of the second

external conductive layer 121 at the process b23 and a pattern is drawn on the

photoresist film 1 15 so as to forming a masking layer at the process b24.

Consequently, the first and second external conductive layers 114 and

121 and third conductive layer 110 are etched back such that conductive pattern 121a, 1 14a, and 1 10a is formed, and then the photoresist film 1 15 is

removed at the process b25.

Finally, solder-resist 116 is deposited on the etch back portion of the

multi-layered board at the process b26.

Fig. 5a is a photograph showing device-landing pads of the multi-layered

PCB according to the present invention, Fig. 5b is an enlarged photograph

showing a portion B of Fig. 5a, and Fig. 6 is a cross-sectional view of the

device-landing pad formed on the multi-layered PCB of Fig. 5a.

As shown in the drawings, the device-landing pad for mounting electronic component is flatten by plugging the via hole. This enlarges the contacting

surface of the electric component such that the electric connection reliability of the component is enhanced and the bonding property of the soldering is

improved.

Of course, only plugging the via hole with the conductive material, it is

possible to improve the electric connectivity of the component and bonding property of the soldering.

While this invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. As described above, the via hole formed on the multi-layered PCB for interconnecting the conductive patterns is plugged and flatten in the present invention such that the contacting surface of the device-landing pad is enlarged, the soldering can be reliably performed, and it is possible to prevent the sold liquid from being flowed into the neighbor via hole and the printing ink from sputtering during the screen printing process.

Furthermore, since the via hole is plugged with the conductive material and the device landing pad is reinforced by the second external conductive layer formed by the copper plating, electric connectivity between the device landing pad and the component is enhanced, resulting in improving component performance reliability.

Claims

WHAT IS CLAIMED IS:

1. A method for forming device-landing pad of a multi-layered printed circuit board (PCB) including the step of forming at least one via hole for interconnecting different conductive layer patterns, the method comprising the steps of: forming a first external conductive layer over the a surface of the multi- layered PCB having the via hole; forming a via by plugging the via hole; forming masking layer over a surface of the conductive layer; etching back the first external conductive layer for forming conductive pattern; and removing the masking layer.

2. A method for forming device-landing pad of claim Ifurther comprises a step of grinding the via for flattening a surface of the via.

3. A method for forming device-landing pad of claim 1 further comprises a step of forming a second external conductive layer over the first external conductive layer and the via.

4. A method for forming device-landing pad of claim 2 further comprises a step of forming a second external conductive layer over the first external conductive layer and the via.

5. A method for forming device-landing pad of claim 4 further comprises a step of etching back the second external conductive layer.

6. A method for forming device-landing pad of claim 1 wherein the via is a conductive material.

7. A method for forming device-landing pad of claim 5 wherein the conductive material is silver.

8. A method for forming device-landing pad of claim 5 wherein the conductive material is copper.

9. A method for forming device-landing pad of claim 5 wherein the conductive material is a conductive resin.

10. A method for forming device-landing pad of claim 3 wherein the second external conductive layer is formed by using copper plating.