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WO2003005786A1 - Method for manufacturing printed wiring board - Google Patents

Method for manufacturing printed wiring board Download PDF

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Publication number
WO2003005786A1
WO2003005786A1 PCT/JP2002/006711 JP0206711W WO03005786A1 WO 2003005786 A1 WO2003005786 A1 WO 2003005786A1 JP 0206711 W JP0206711 W JP 0206711W WO 03005786 A1 WO03005786 A1 WO 03005786A1
Authority
WO
WIPO (PCT)
Prior art keywords
jig
slope
silicon wafer
film
thickness
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2002/006711
Other languages
French (fr)
Japanese (ja)
Inventor
Makoto Uehara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mejiro Precision KK
Original Assignee
Mejiro Precision KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mejiro Precision KK filed Critical Mejiro Precision KK
Priority to KR1020037016940A priority Critical patent/KR100914376B1/en
Priority to JP2003511605A priority patent/JP4153422B2/en
Publication of WO2003005786A1 publication Critical patent/WO2003005786A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/687Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
    • H01L21/68714Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
    • H01L21/68721Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by edge clamping, e.g. clamping ring
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/02Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/687Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
    • H01L21/68714Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
    • H01L21/68735Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by edge profile or support profile
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/687Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
    • H01L21/68714Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
    • H01L21/68778Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by supporting substrates others than wafers, e.g. chips
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0306Inorganic insulating substrates, e.g. ceramic, glass

Definitions

  • the present invention relates to a method for manufacturing a printed wiring board using an extremely thin silicon wafer as a base material.
  • multilayer printed wiring boards In response to the demand for high-density mounting of electronic components, multilayer printed wiring boards (multilayer printed wiring boards) are used.
  • the multilayer printed wiring board uses a ceramic substrate, a laminate, a composite laminate, or the like as its substrate, and the requirements for the thickness of the substrate and the electrical characteristics did not match. Disclosure of the invention
  • An object of the present invention is to provide a method for manufacturing an extremely thin printed wiring board capable of manufacturing a printed circuit board that can be stacked in multiple stages.
  • the present invention is a method for manufacturing a printed wiring board, comprising the following steps.
  • the thickness is 50! Prepare ⁇ 300 m of silicon wafer;
  • FIG. 1 is a block diagram showing a method for manufacturing a printed wiring board according to the present invention along a flow of main steps.
  • FIG. 2 is a plan view showing a jig used in the method for manufacturing a printed wiring board of the present invention together with a substrate material held thereon.
  • FIG. 3 is a partially enlarged cross-sectional view (cut along the line AA) showing one embodiment of a jig holding the substrate material shown in FIG.
  • FIG. 4 is a partially enlarged sectional view (cut along the line AA) showing another embodiment of the jig holding the substrate material shown in FIG.
  • FIG. 5 is a partially enlarged cross-sectional view (cut along the line AA) showing still another embodiment of the jig holding the substrate material shown in FIG.
  • FIG. 6 is a partially enlarged cross-sectional view (cut along the line AA) showing still another embodiment of the jig holding the substrate material shown in FIG.
  • FIG. 7 is a partially enlarged cross-sectional view showing a state where the jig holding the substrate material shown in FIG. 3 is covered with a film and the front and back surfaces of the substrate material are exposed.
  • FIG. 1 shows a standard process diagram of the present invention.
  • a silicon wafer cut from an ingot is used as the substrate material (20). Its thickness is 50-300 m (for semiconductors, it is 735 m for an 8-inch one. In the state of a chip, it is at least about 30 m thick, but it was cut out from an ingot.) It was reduced by applying a separate grinding process. The surface roughness of about 1,000 to 5,000 A (10-point average roughness specified in JIS B 0601: Rz) is sufficient, and a mirror finish like that for semiconductors is not required.
  • the substrate is held by a special jig (10) in consideration of handling properties and processing accuracy in the subsequent processing.
  • the peripheral part (20a) of the substrate is connected to the main part (10a) of the jig by a step (10b) provided on the inner peripheral part (in the figure, Shape around Although it is configured as described above, it may be formed in a claw shape at predetermined intervals in the circumferential direction. In such a case, the jig and the substrate are integrated with a film in the next step as described below. Usually, mounting is sufficient).
  • the jig (10) shown in FIG. 3 is composed of one member (10a) (hereinafter referred to as the main part of the jig). Force is more secure for holding the substrate on the jig. In order to make the member into two members
  • the height of the cut portion is 1Z2 of the thickness of the substrate, respectively
  • the peripheral portion (20a) of the substrate may be sandwiched between both members (see FIG. 4).
  • a step (11a) (the height is the same as the thickness of the substrate) is provided only on the inner peripheral edge of the member (11), and the other member (12) has a flat lower surface and a front end of the lower surface.
  • the upper surface of the peripheral portion (20a) of the substrate placed on the step portion may be pressed by the portion (see FIG. 5), or the jig may be moved to a main portion having a step portion (11b).
  • the bottom of the step portion has the thickness of the main portion. Formed substantially at a position lower than the center by 12 times the thickness of the substrate), and the depth of the step is set to the width, and the outer peripheral edge of the step is substantially in contact with the deepest part of the step of the jig. Disk (12b) ( The other member shown in Fig. 5
  • reference numeral 14 denotes an opening of the jig
  • FIG. 2 shows the state where the substrate is attached to the jig, so that reference numerals 20 and 14 and 20a and 10b 1 1a, 12a, 12b and force are assigned to the same places, respectively, and reference numerals 10a, 11 and lib and 12 are also viewed from above with their upper and lower surfaces abutting against each other. So it is attached to the same place).
  • the slope portions (10 c, 10 d, lie, lld, 12 c, 11 d) of the members constituting the jig are used to smoothly cover the jig and the substrate in a film coating step described later.
  • the angle of the substrate to be held on the jig The diameter may be set appropriately according to the diameter of the jig, the diameter of the jig, and the properties of the resist to be applied. Generally, it is selected within the range of 3 to 10 °. In addition, an appropriate radius is applied to the corners of the jig, for example, the transition from the outer peripheral surface to the upper and lower surfaces, and the corners, in order to secure coating with the film in the next step. Is preferred.
  • the jig is made of a metal such as aluminum, copper, or brass in that the jig has a certain degree of rigidity and is excellent in conductivity and resistance to chemical agents.
  • the member is preferably made of metal because its weight also contributes to holding the substrate.
  • the step of the jig has a distance H between the upper surface of the jig and the upper surface of the substrate when the substrate is placed thereon (in the embodiment shown in FIGS. 4 and 5, The distance between the upper surface of the other member of the jig and the upper surface of the substrate, in the embodiment shown in FIG.
  • the distance between the upper surface of the main portion of the jig and the upper surface of the substrate is the lower surface of the jig and the upper surface of the substrate.
  • Distance from the lower surface of the substrate: H In the embodiment shown in FIGS. 4 and 5, the distance between the lower surface of one member of the jig and the lower surface of the substrate, and in the embodiment shown in FIG. (The distance between the lower surface of the main part of the tool and the lower surface of the substrate).
  • H In order to use the upper and lower surfaces of the substrate as a formation point thereof in order to increase the density of the conductor pattern, it is possible to easily perform exposure in patterning as a forming operation by overturning the upper and lower surfaces of the substrate. is there.
  • one jig is shown for one silicon wafer as the substrate material, but of course, one jig is used for a plurality of silicon wafers. Needless to say, the one-to-one correspondence is good from the flexibility of securing the exposure work area, while the plural-to-one correspondence is good in terms of the efficiency of forming the metal thin film described later. It should be selected appropriately according to the situation).
  • the jig is shown as being substantially square in the drawing, the outer shape thereof may of course be circular or polygonal.
  • a plurality of radially arranged upper and lower surfaces of the jig and slopes connected to the jig (the number is appropriately selected according to the diameter of the substrate to be held on the jig, and therefore the diameter of the jig)
  • the air vent groove (13) is provided in consideration of the composite distribution of the jig (the starting point or the end point is the outer peripheral end of the jig, and the end point or the starting point is the Is the inner peripheral end of the tool slope). This is for surely performing the film coating described later.
  • the shape (cross section) of the groove is a semicircle
  • Any shape may be used as long as the air existing between the film and the jig and the substrate when the film is coated, such as a semi-ellipse, a corner, or a triangle, can smoothly escape.
  • the transition from the upper end of the wall of the groove to the upper and lower surfaces including the slope portion of the jig is provided with a radius in order to secure the adhesion of the film.
  • the substrate material held by the jig is covered and fixed together with a film (14) together with the jig.
  • a dry resist for example, a negative type dry film can be cited as a candidate from the viewpoint of handleability.
  • the coating with the film is performed by, for example, bringing the film into close contact with the entire jig holding the substrate material by, for example, a vacuum laminating method, and bonding the film to the peripheral portion (20 a) of the substrate. This is done by patterning so that the front and back surfaces of the substrate material are exposed, except for the area near the inside (see Fig. 7. The substrate material exposes most of the front and back surfaces (the area indicated by arrows in the figure)).
  • the coating film should be displayed with diagonal lines, but the display is not complicated. Therefore, diagonal lines have been omitted.
  • the through hole can be formed by a laser, for example, a perforation method using a carbon dioxide laser or a YAG laser, a plasma etching method, or a photolithography method.
  • a metal thin film-1 for example, a thin film (thickness: at least 5 OA) such as IT ⁇ or copper [Cu] is formed on the exposed surface of the substrate material.
  • a vapor deposition method can be used.
  • the metal thin film-1 is formed by an electroless plating method (after forming a nickel [Ni] thin film and then using gold [A u]). (In this case, a part of the nickel thin film is replaced) (in this case, the formed thin film is a composite film of nickel in the lower layer or the base layer and gold in the upper layer or the surface layer). Note that this metal thin film-1 is applied not only to the surface of the substrate material but also to the wall surface of the previously formed through hole. Form.
  • a metal thin film 12 serving as a main component of the conductor pattern, for example, Cu or the like is formed on the surface of the substrate material on which the metal thin film 11 is formed.
  • An example of the method is an electroless plating method (if the electroless plating method is applied in step E, this step is unnecessary). If a thicker metal thin film (thickness: 3 m or more) is desired, an electric plating method is further applied.
  • the metal thin film is formed not only on the surface of the substrate material but also on the wall surface of the previously formed through hole.
  • resist coating Similar to the formation of a conventional conductor pattern, resist coating (the resist coating may be performed in accordance with a conventional method.
  • the application of the AND spin method is preferable because it can reduce the consumption of the resist and can also be applied to the concave portions.
  • the slot core is preferably used for the diameter of the jig (10) and the substrate (20). It is good to rotate the slot core around the center of the jig and the substrate.)
  • Exposure and development exposing the metal thin film other than the desired conductor pattern
  • Etch removal of the exposed metal thin film, and stripping and removal of resist When a negative type dry film is used as a film for fixing the substrate material to the substrate, a positive type resist is used here. This is because the dissolution of the film in the developer used in this step can be prevented.
  • a product having a function as a printed wiring board is manufactured in the steps up to this point.
  • the printed wiring board can be obtained by cutting to a desired size.
  • resist Before cutting, if necessary, apply resist, expose and develop (expose the bumps in the conductor pattern), and form the bumps (by using a solution containing gold ions).
  • the bump since the bump needs a certain height, it is only necessary to first form an underlayer made of copper, nickel, or the like, and then apply gold plating only to the surface layer of the underlayer.) Or a solder ball may be applied to a predetermined position according to a conventional method. So far, a case has been described in which a conductor pattern is newly formed on a substrate.
  • the feature of the manufacturing method using the jig of the present invention is that an ultra-thin substrate (silicon wafer) which has never been seen before. This is also applicable to the case where a conductor pattern has already been formed on a substrate, for example, a case where only bumps are formed on a circuit-formed I, since the problem caused by the thinness can be solved. It is. By the way, in conventional IC manufacturing, bumps are formed after the back surface of a thick substrate (silicon wafer) is physically ground to a desired thickness.
  • a metal thin film 1 (ITO; thickness: 10 OA) was placed on a silicon wafer (both sides, including the inner wall of a through hole) in the work area. Formed (Target: Number of wafers: 1).
  • the electroless plating method (using Melplate Ni-867M1-M2 and Au-601 manufactured by Meltex Co., Ltd.) can also be applied to the metal thin film-1 (1 ⁇ 1 + 8 ⁇ 1; thickness: 0.5 m). ) Was formed (the number of target A eight sheets: 1).
  • a metal thin film 1 (Cu; thickness: 20 im) is further formed on the metal thin film 11 formed in advance by the sputtering method. Formed.
  • a resist (positive resist: s PR-6800, manufactured by Shipley Farst Co., Ltd.) was applied on the metal thin film 1 and the metal thin film 1 formed only by the electroless plating method.
  • a development pattern was formed on the silicon wafer (both sides) by performing development, etching, and resist stripping. The details are as follows.
  • Exposure light source 200 ⁇ PRO J-2001 manufactured by Mejiro Investment Co., Ltd.
  • Etch solution VPositeEtch 746 manufactured by Shipley Far East Co., Ltd.
  • a resist (positive resist manufactured by Shipley Pfist Co., Ltd .: SPR-6800) was applied, and then exposure, development, electric plating, and resist stripping were performed to form gold bumps on the bump lands of the wiring pattern.
  • SPR-6800 positive resist manufactured by Shipley Pfist Co., Ltd .: SPR-6800
  • Exposure light source Use 200 ⁇ PRO J-2001 manufactured by Mejiro Investment Co., Ltd.
  • Mesh liquid Evalon NiBM-2 (for base) and Riptorores SMT 250 (gold plated) manufactured by Rironal. Use each
  • a method for manufacturing a printed wiring board capable of manufacturing an ultrathin printed circuit board that can be stacked in multiple stages and that meets the requirements for the thickness of the substrate and the requirements for electrical characteristics.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A method for manufacturing a very-thin printed wiring board a plurality of which can be stacked, characterized by comprising the steps: A. preparing a silicon wafer (20) having a thickness of 50 to 300 µm; B. attaching the silicon wafer (20) to a jig (10) for holding only the edge of the silicon wafer (20), covering the whole surface of the silicon wafer (20) with a film, and fixing the silicon wafer (20) to the jig (10); C. patterning the film to expose the front and back faces of the silicon wafer (20); D. making a through hole in a predetermined position of the exposed silicon wafer (20), and forming a metallic thin film on the exposed surface of the silicon wafer (20) having the through hole; and E. patterning the metallic thin film, and performing etching so as to produce a predetermined conductor pattern.

Description

明 細 書 プリント配線板の製造方法 技術分野  Description Manufacturing method of printed wiring board Technical field

本発明は、 極薄のシリコンウェハを基材とするプリント配線板の製造方法に関 する。 背景技術  The present invention relates to a method for manufacturing a printed wiring board using an extremely thin silicon wafer as a base material. Background art

電子部品の高密度実装の要請に対応して、 プリント配線板も多層化したもの (多層プリント配線板) が使用されている。 しかしながら、 多層プリント配線板 は、 その基板としてセラミック基板、 積層板、 コンポジット積層板等を用いてお り、 基板の厚みと電気特性上の要求がマッチしていなかった。 発明の開示  In response to the demand for high-density mounting of electronic components, multilayer printed wiring boards (multilayer printed wiring boards) are used. However, the multilayer printed wiring board uses a ceramic substrate, a laminate, a composite laminate, or the like as its substrate, and the requirements for the thickness of the substrate and the electrical characteristics did not match. Disclosure of the invention

本発明は、 多段積層可能なプリント回路板を製造し得る極薄のプリント配線板 の製造方法を提供することを目的とする。  An object of the present invention is to provide a method for manufacturing an extremely thin printed wiring board capable of manufacturing a printed circuit board that can be stacked in multiple stages.

すなわち本発明は、 下記のステップを含んでなることを特徴とするプリント配 線板の製造方法である。  That is, the present invention is a method for manufacturing a printed wiring board, comprising the following steps.

A. 厚みが 5 0 !〜 3 0 0 mのシリコンゥエーハを準備する; A. The thickness is 50! Prepare ~ 300 m of silicon wafer;

B . 該シリコンゥエーハをその周縁部のみを保持し得る治具に取付け、 その全面 を治具ごとフィルムにて被覆し、 該シリコンゥエーハを該治具に固定する ; B. attaching the silicon wafer to a jig capable of holding only the periphery thereof, covering the entire surface with the jig with a film, and fixing the silicon wafer to the jig;

C . 該フィルムをパターニングしてシリコンゥェ一八の表裏面を露出させる (該 露出せしめられた部分が配線パターン、 スルーホール及びバンプランド形成のた めのワークエリアとなる) ; C. patterning the film to expose the front and back surfaces of the silicon wafer (the exposed portions become work areas for forming wiring patterns, through holes and bump lands);

D . 該露出せしめられたシリコンゥェ一八の所定位置にスルーホールを形成する とともに、 該スルーホールを含む該シリコンウーェハの露出面に金属薄膜を形成 する ;そして  D. forming a through hole at a predetermined position of the exposed silicon wafer 18, and forming a metal thin film on an exposed surface of the silicon wafer including the through hole;

E . 該金属薄膜をパターニングし、 次いでエッチングを行って、 所定の導体パ ターンを得る。 図面の簡単な説明 E. Pattern the metal thin film, then perform etching to Get a turn. BRIEF DESCRIPTION OF THE FIGURES

図 1は、 本発明のプリント配線板の製造方法を主要工程の流れに沿って示した ブロックダイヤグラムである。  FIG. 1 is a block diagram showing a method for manufacturing a printed wiring board according to the present invention along a flow of main steps.

図 2は、 本発明のプリント配線板の製造方法に用いる治具をそれに保持した基 板材料とともに示した平面図である。  FIG. 2 is a plan view showing a jig used in the method for manufacturing a printed wiring board of the present invention together with a substrate material held thereon.

図 3は、 図 2図示の基板材料を保持した治具の一態様を示す部分拡大断面図 ( A— A線で切断) である。  FIG. 3 is a partially enlarged cross-sectional view (cut along the line AA) showing one embodiment of a jig holding the substrate material shown in FIG.

図 4は、 図 2図示の基板材料を保持した治具の他の態様を示す部分拡大断面図 (A— A線で切断) である。  FIG. 4 is a partially enlarged sectional view (cut along the line AA) showing another embodiment of the jig holding the substrate material shown in FIG.

図 5は、 図 2図示の基板材料を保持した治具の更に他の態様を示す部分拡大断 面図 (A— A線で切断) である。  FIG. 5 is a partially enlarged cross-sectional view (cut along the line AA) showing still another embodiment of the jig holding the substrate material shown in FIG.

図 6は、 図 2図示の基板材料を保持した治具のまた更に他の態様を示す部分拡 大断面図 (A— A線で切断) である。  FIG. 6 is a partially enlarged cross-sectional view (cut along the line AA) showing still another embodiment of the jig holding the substrate material shown in FIG.

図 7は、 図 3図示の基板材料を保持した治具をフィルムにて被覆し、 そして該 基板材料の表裏面を露出させた状態を示す部分拡大断面図である。  FIG. 7 is a partially enlarged cross-sectional view showing a state where the jig holding the substrate material shown in FIG. 3 is covered with a film and the front and back surfaces of the substrate material are exposed.

ここで、 各符号は  Where each sign is

1 0 治具 1 0 Jig

1 0 a 治具の主体部 1 0a Main part of jig

1 0 b 治具の段部 1 0 b Step of jig

1 0 c 治具のスロープ部 (一方のスロープ部)  1 0 c Slope part of jig (one slope part)

1 0 d 治具のスロープ部 (他方のスロープ部) 10 d Slope of jig (other slope)

1 1 治具の一方の構成部材 1 1 One component of jig

1 1 a 治具の一方の構成部材の段部 1 1 a Step of one component of jig

1 1 b 治具の一方の構成部材 (主体部) 1 1 b One component of jig (main part)

1 1 c 治具の一方の構成部材のスロープ部又は主体部のスロープ部 (一方のス ロープ部)  1 1c Slope of one component of jig or slope of main part (one slope)

1 I d 治具の一方の構成部材 (主体部) のスロープ部 (他方のスロープ部) 12 治具の他方の構成部材 1 Id Slope of one component (main part) of jig (other slope) 12 The other component of the jig

12 a 治具の他方の構成部材の段部  12 a Step of the other component of the jig

12 b 治具の他方の構成部材 (ドーナツ状の部材)  12 b The other component of the jig (donut-shaped member)

12 c 治具の他方の構成部材のスロープ部  12 c Slope of the other component of the jig

13 治具の溝  13 Jig groove

14 開口部  14 Opening

15 被覆フィルム  15 Coating film

20 基板材料  20 Substrate material

20 a 基板材料の周縁部  20a Peripheral edge of substrate material

を、 それぞれ表わす。 発明を実施するための最良の形態 , Respectively. BEST MODE FOR CARRYING OUT THE INVENTION

本発明を、 一実施態様を示す添付図面 (図 1を除き、 各部材の相互関係及び構 造を示すのが目的ゆえ、 図示の寸法は実寸ではない) を参照しつつ詳細に説明す る。  DETAILED DESCRIPTION OF THE INVENTION The present invention will be described in detail with reference to the accompanying drawings showing one embodiment (except for FIG. 1, the dimensions shown in the drawings are not to scale because the purpose is to show the interrelation and structure of each member).

図 1に示したものが本発明の標準的なプロセスダイヤグラムである。  FIG. 1 shows a standard process diagram of the present invention.

A. 基板の準備  A. Board preparation

本発明においては、 基板材料 (20) としてインゴットから切り出されたシリ コンゥエーハを用いる。 その厚さは 50〜300 mである (因みに半導体用の それは 8インチのもので 735 mである。 チップの状態では最小 30 m程度の 厚さであるが、 これはインゴッ卜から切り出されたゥェ一八に別途研削加工を施 して減じたものである) 。 尚、 その表面の粗さは、 1000人〜 5000 A (J I S B 0601に規定する十点平均粗さ : R z ) 程度で充分であり、 半 導体用のそれのような鏡面仕上げを要しない。  In the present invention, a silicon wafer cut from an ingot is used as the substrate material (20). Its thickness is 50-300 m (for semiconductors, it is 735 m for an 8-inch one. In the state of a chip, it is at least about 30 m thick, but it was cut out from an ingot.) It was reduced by applying a separate grinding process. The surface roughness of about 1,000 to 5,000 A (10-point average roughness specified in JIS B 0601: Rz) is sufficient, and a mirror finish like that for semiconductors is not required.

B. 治具への取付  B. Installation on jig

前工程にて準備された基板材料 (20) はその厚さが薄いため、 その後の加工 におけるハンドリング性や加工精度を考慮し、 該基板を特殊な治具 (10) にて 保持する。 具体的には、 図 2に示すように、 該基板の周縁部 (20 a) を該治具 の主体部 (10 a) 内周縁部に設けられた段部 (10 b) (図示では、 全周に形 成された態様となっているが、 周方向に所定間隔にて爪状に飛び飛びに形成して もよい。 その場合には、 保持の安定性確保の観点から少なくとも 3ケ所に設け る) 上に載置する (後述のように、 次工程にて該治具と該基板とはフィルムで 一体化するので、 通常は載置で充分である) 。 尚、 図 3に示す治具 (10) は、 一つの部材 (10 a) (以下では、 治具の主体部という) からなるものである 力 該治具上への該基板の保持をより確実にするために、 該部材を二つの部材Since the thickness of the substrate material (20) prepared in the previous process is thin, the substrate is held by a special jig (10) in consideration of handling properties and processing accuracy in the subsequent processing. Specifically, as shown in FIG. 2, the peripheral part (20a) of the substrate is connected to the main part (10a) of the jig by a step (10b) provided on the inner peripheral part (in the figure, Shape around Although it is configured as described above, it may be formed in a claw shape at predetermined intervals in the circumferential direction. In such a case, the jig and the substrate are integrated with a film in the next step as described below. Usually, mounting is sufficient). The jig (10) shown in FIG. 3 is composed of one member (10a) (hereinafter referred to as the main part of the jig). Force is more secure for holding the substrate on the jig. In order to make the member into two members

(1 1) と (12) に分割し、 両部材の内周縁部にそれぞれ段部 (11 a,(1 1) and (12), and the inner peripheral edges of both members are stepped (11a,

12 a) (断部の高さはそれぞれ該基板の厚みの 1Z2) を設け、 両部材にて該 基板の周縁部 (20 a) を挟み込む形態 (図 4参照) にしてもよいし、 一方の部 材 (1 1) の内周縁部にのみ段部 (1 1 a) (その高さは該基板の厚みに同じ) を設け、 他方の部材 (12) はその下面が平坦で該下面の先端部で該段部に載置 された該基板の周縁部 (20 a) の上面を押える態様 (図 5参照) にしてもよい し、 該治具を、 段部を有する主体部 (1 1 b) (実質的に図 4及び図 5図示の治 具を構成する二つの部材 (1 1, 12) がー体となった形態であって、 該段部の 底部が、 該主体部の厚みの中心より該基板の厚みの 1 2下がった位置となる よう形成) と、 該段部の奥行きをその幅とし、 その外周縁部を該治具の段部の 最深部に当接する実質的にドーナツ状の円板 (12 b) (図 5図示の他方の部材12a) (The height of the cut portion is 1Z2 of the thickness of the substrate, respectively) is provided, and the peripheral portion (20a) of the substrate may be sandwiched between both members (see FIG. 4). A step (11a) (the height is the same as the thickness of the substrate) is provided only on the inner peripheral edge of the member (11), and the other member (12) has a flat lower surface and a front end of the lower surface. The upper surface of the peripheral portion (20a) of the substrate placed on the step portion may be pressed by the portion (see FIG. 5), or the jig may be moved to a main portion having a step portion (11b). (The two members (11, 12) that substantially constitute the jig shown in FIGS. 4 and 5 are in the form of a core, and the bottom of the step portion has the thickness of the main portion. Formed substantially at a position lower than the center by 12 times the thickness of the substrate), and the depth of the step is set to the width, and the outer peripheral edge of the step is substantially in contact with the deepest part of the step of the jig. Disk (12b) ( The other member shown in Fig. 5

(12) がその先端部のみとなつた形態) とからなるものにしてもよい (図 6 参照) 。 図中、 符号 14は該治具の開口部である (図 2は該治具に該基板が取 付けられた状態にて描かれているため、 符号 20と 14、 及び 20 aと 10 b と 1 1 aと 12 aと 12 bと力 それぞれ同一個所に付されている。 また符号 10 aと 11と l i bと 12もそれらの指示する部材の上面と下面が当接した状 態で上から見ているので同一個所に付されている) 。 尚、 該治具を構成する部材 のスロープ部 (10 c, 10 d, l i e, l l d, 12 c, 1 1 d) は、 後述の フィルムによる被覆工程における該治具及び該基板の円滑な被覆並びに金属薄膜 の形成工程 (1) 及び/又は (2) 及び導体パターンの形成工程において塗付 されるレジス卜の厚みの均一化のためにそのようにされているものである (ス ロットコ一ティングーコ一夕一を径方向に配置 ·適用する一 ;スピンコーティン グー余剰レジストの円滑排出一等) 。 その角度は、 該治具上に保持すべき該基板 の径、 したがって該治具の径、 更には塗付するレジストの性質に応じて適宜設定 すれば良い。 一般的には、 3〜 1 0 ° の範囲で選定する。 また、 該治具の角部、 例えば外周面から上下面への移行部分や、 隅部には、 次工程であるフィルムによ る被覆を確実なものとするため、 適度な Rをつけておくことが好ましい。 (12) has only its tip) (see FIG. 6). In the figure, reference numeral 14 denotes an opening of the jig (FIG. 2 shows the state where the substrate is attached to the jig, so that reference numerals 20 and 14 and 20a and 10b 1 1a, 12a, 12b and force are assigned to the same places, respectively, and reference numerals 10a, 11 and lib and 12 are also viewed from above with their upper and lower surfaces abutting against each other. So it is attached to the same place). The slope portions (10 c, 10 d, lie, lld, 12 c, 11 d) of the members constituting the jig are used to smoothly cover the jig and the substrate in a film coating step described later. This is done in order to make the thickness of the resist applied in the step (1) and / or (2) of forming the metal thin film and the step of forming the conductor pattern uniform (slot coating-coating). (1) Spin coating-Smooth discharge of excess resist, etc.) The angle of the substrate to be held on the jig The diameter may be set appropriately according to the diameter of the jig, the diameter of the jig, and the properties of the resist to be applied. Generally, it is selected within the range of 3 to 10 °. In addition, an appropriate radius is applied to the corners of the jig, for example, the transition from the outer peripheral surface to the upper and lower surfaces, and the corners, in order to secure coating with the film in the next step. Is preferred.

ここで、 該治具は、 ある程度の剛性を有し、 導電性及び耐化学薬剤性に優れ る、 という点において、 アルミニウム、 銅、 真鍮等の金属にて作製される (治具 が二つの部材からなり、 それらの一方の部材がドーナツ状の円板である態様にお いては、 その重量も該基板の保持に資するので、 金属製とするのが好ましい) 。 また、 該治具の段部は、 その上に該基板を載置した状態において、 該治具の上面 と該基板の上面との距離: H (図 4及び図 5図示の態様においては、 該治具の 他方の部材の上面と該基板の上面との距離、 図 6図示の態様においては、 該治具 の主体部の上面と該基板の上面との距離) が該治具の下面と該基板の下面との距 離: H (図 4及び図 5図示の態様においては、 該治具の一方の部材の下面と該基 板の下面との距離、 図 6図示の態様においては、 該治具の主体部の下面と該基板 の下面との距離) とが等しくなるように設定する。 導体パターンの高密度化をは かるため該基板の上下面をその形成個所として活用するにあたり、 その形成操作 としてのパターニングにおける露光を該基板の上下面の転倒にて簡単になすこと ができるからである。 更に、 図示では該基板材料としてのシリコンゥエーハ 1枚 に対し該治具が 1個の態様が示されているが、 勿論複数枚のシリコンゥエーハに 対して該治具を 1個とした態様を取り得ること言うまでもない (露光ワークエリ ァの確保の柔軟性からは 1対 1の対応がよく、 一方、 後述の金属薄膜の形成の効 率化という点においては複数対 1の対応がよいので、 状況に応じて適宜選定すれ ばよい) 。 また、 図示では実質的に角形の治具とされているが、 その外形は円形 や多角形としても良いこと勿論である。 尚、 該治具の上面と下面及びそれらに連 なるスロープに放射状に複数 (その数は、 該治具上に保持すべき該基板の径、 し たがって該治具の径に応じて適宜選定すればよい) の空気抜き用の溝 (1 3 ) を 該治具の合成分布に配慮して設ける (その始点又は終点は、 該治具の外周端部 であり、 その終点又は始点は、 該治具のスロープの内周端部である) 。 後述の フィルム被覆を確実に行なうためである。 ここで、 該溝の形状 (断面) は半円、 半楕円、 角、 三角等フィルム被覆時の該治具及び該基板とフィルム間に存在する 空気がスムースに抜けるものであればいずれの形状であってもよい。 但し、 該溝 の壁の上端から該治具のスロープ部を含む上下面への移行部は、 フィルムの密着 性を確保するために Rをつけておくことが好ましい。 Here, the jig is made of a metal such as aluminum, copper, or brass in that the jig has a certain degree of rigidity and is excellent in conductivity and resistance to chemical agents. In an embodiment in which one of the members is a donut-shaped disk, the member is preferably made of metal because its weight also contributes to holding the substrate.) Further, the step of the jig has a distance H between the upper surface of the jig and the upper surface of the substrate when the substrate is placed thereon (in the embodiment shown in FIGS. 4 and 5, The distance between the upper surface of the other member of the jig and the upper surface of the substrate, in the embodiment shown in FIG. 6, the distance between the upper surface of the main portion of the jig and the upper surface of the substrate) is the lower surface of the jig and the upper surface of the substrate. Distance from the lower surface of the substrate: H (In the embodiment shown in FIGS. 4 and 5, the distance between the lower surface of one member of the jig and the lower surface of the substrate, and in the embodiment shown in FIG. (The distance between the lower surface of the main part of the tool and the lower surface of the substrate). In order to use the upper and lower surfaces of the substrate as a formation point thereof in order to increase the density of the conductor pattern, it is possible to easily perform exposure in patterning as a forming operation by overturning the upper and lower surfaces of the substrate. is there. Further, in the drawing, one jig is shown for one silicon wafer as the substrate material, but of course, one jig is used for a plurality of silicon wafers. Needless to say, the one-to-one correspondence is good from the flexibility of securing the exposure work area, while the plural-to-one correspondence is good in terms of the efficiency of forming the metal thin film described later. It should be selected appropriately according to the situation). Although the jig is shown as being substantially square in the drawing, the outer shape thereof may of course be circular or polygonal. A plurality of radially arranged upper and lower surfaces of the jig and slopes connected to the jig (the number is appropriately selected according to the diameter of the substrate to be held on the jig, and therefore the diameter of the jig) The air vent groove (13) is provided in consideration of the composite distribution of the jig (the starting point or the end point is the outer peripheral end of the jig, and the end point or the starting point is the Is the inner peripheral end of the tool slope). This is for surely performing the film coating described later. Here, the shape (cross section) of the groove is a semicircle, Any shape may be used as long as the air existing between the film and the jig and the substrate when the film is coated, such as a semi-ellipse, a corner, or a triangle, can smoothly escape. However, it is preferable that the transition from the upper end of the wall of the groove to the upper and lower surfaces including the slope portion of the jig is provided with a radius in order to secure the adhesion of the film.

C . フィルムによる被覆  C. Coating with film

その後の加工の精度を確保するため、 該治具に保持された該基板材料を、 該治 具共々フィルム (1 4 ) にて被覆 ·固定する。 該フィルムとしては、 取扱性の面 からドライレジスト、 例えばネガ型のドライフィルムを候補として挙げることが できる。 尚、 該フィルムによる被覆は、 該フィルムを、 例えば真空ラミネート法 等にて該基板材料が保持された該治具全体に密着させ、 そして該フィルムを、 該 基板の周縁部 (2 0 a ) の内方近傍部を除く該基板材料の表裏面が露出するよう にパターニングすることによって行う (図 7参照。 該基板材料は、 その表裏面の 大半 (図中の矢印を付した範囲) が露出せしめられた状態にて該治具に緊密に保 持されている。 尚、 図 7は断面図ゆえ、 該被覆フィルムも、 本来は斜線を入れて 表示すべきであるが、 表示の煩雑さを避けるため斜線は割愛した) 。  In order to secure the accuracy of the subsequent processing, the substrate material held by the jig is covered and fixed together with a film (14) together with the jig. As the film, a dry resist, for example, a negative type dry film can be cited as a candidate from the viewpoint of handleability. The coating with the film is performed by, for example, bringing the film into close contact with the entire jig holding the substrate material by, for example, a vacuum laminating method, and bonding the film to the peripheral portion (20 a) of the substrate. This is done by patterning so that the front and back surfaces of the substrate material are exposed, except for the area near the inside (see Fig. 7. The substrate material exposes most of the front and back surfaces (the area indicated by arrows in the figure)). In addition, since the jig is held tightly in this state, since the cross-sectional view is shown in FIG. 7, the coating film should be displayed with diagonal lines, but the display is not complicated. Therefore, diagonal lines have been omitted.)

D . スルーホールの形成  D. Formation of through hole

プリント回路板の多段積層のために該基板材料の所定の位置にスルーホールを 形成する。 該基板材料はその厚さが薄いので、 該スルーホールの形成方法として はレーザ一、 例えば炭酸ガスレーザーや Y A Gレーザ一による穿孔法、 プラズマ エッチング法、 フォトリソグラフィ一法等を適用し得る。  Through holes are formed at predetermined positions in the substrate material for multi-layered printed circuit boards. Since the substrate material has a small thickness, the through hole can be formed by a laser, for example, a perforation method using a carbon dioxide laser or a YAG laser, a plasma etching method, or a photolithography method.

E . 金属薄膜— 1の形成  E. Formation of metal thin film-1

後述する金属薄膜一 2の密着性を確保するため、 該基板材料の露出した表面に 金属薄膜— 1、 例えば I T〇や銅 [ C u ] 等の薄膜 (厚み:少なくとも 5 O A) を形成する。 その方法としては蒸着法が挙げられる。 一方、得られる金属薄膜の 厚みがさほど厚くなくてもよい用途については、 該金属薄膜— 1は、 無電解メッ キ法 (ニッケル [N i ] の薄膜を形成した後、 金 [A u ] で該ニッケル薄膜の一 部を置換する) にても形成することができる (この場合、 形成される薄膜は、 下層又は基層がニッケル、 上層又は表層が金の複合膜となる) 。 尚、 この金属薄 膜— 1は、 該基板材料の表面のみならず、 先に形成したスルーホールの壁面にも 形成する。 In order to secure the adhesion of the metal thin film 12 described later, a metal thin film-1, for example, a thin film (thickness: at least 5 OA) such as IT〇 or copper [Cu] is formed on the exposed surface of the substrate material. As the method, a vapor deposition method can be used. On the other hand, for applications in which the thickness of the obtained metal thin film does not need to be so large, the metal thin film-1 is formed by an electroless plating method (after forming a nickel [Ni] thin film and then using gold [A u]). (In this case, a part of the nickel thin film is replaced) (in this case, the formed thin film is a composite film of nickel in the lower layer or the base layer and gold in the upper layer or the surface layer). Note that this metal thin film-1 is applied not only to the surface of the substrate material but also to the wall surface of the previously formed through hole. Form.

F . 金属薄膜一 2の形成  F. Formation of metal thin film 1

その上に金属薄膜一 1が形成された該基板材料の表面に導体パターンの主体と なる金属薄膜一 2、 例えば C u等を形成する。 その方法としては無電解メツキ 法が挙げられる (工程 Eで無電解メツキ法を適用する場合には、 この工程は不 要) 。 より厚い金属薄膜 (厚み: 3 m以上) を所望の場合には更に電気メツキ 法を適用する。 尚、 この金属薄膜は、 該基板材料の表面のみならず、 先に形成し たスルーホールの壁面にも形成する。  On the surface of the substrate material on which the metal thin film 11 is formed, a metal thin film 12 serving as a main component of the conductor pattern, for example, Cu or the like is formed. An example of the method is an electroless plating method (if the electroless plating method is applied in step E, this step is unnecessary). If a thicker metal thin film (thickness: 3 m or more) is desired, an electric plating method is further applied. The metal thin film is formed not only on the surface of the substrate material but also on the wall surface of the previously formed through hole.

G . 導体パターンの形成  G. Formation of conductive pattern

従来の導体パターンの形成と同様、 レジスト塗付 (常法に従って行えばよい。 但し、 スロットコ一夕一単用又はスロットコ一夕一による塗付の後で該治具を回 転させるスロット ·アンド ·スピン法の適用がレジス卜の消費量が少なく済むと 共に、 凹部にも塗付し得るので好ましい。 尚、 スロットコ一夕一は治具 (1 0 ) 及び基板 (2 0 ) の径方向に配置し、 該スロットコ一夕一を、 該治具及び該基 板のセンターを中心として回転させるとよい) 、 露光 ·現像 (所望する導体パ ターン以外の部分の金属薄膜を露出せしめる) 、 露出せしめられた金属薄膜の エッチング除去、 レジストの剥離 ·除去を行う。 尚、 該基板材料を該洽具に固定 するためのフィルムとしてネガ型のドライフィルムを使用した場合には、 ここで 使用するレジストとしてはポジ型のものを使う。 この工程で使用する現像液への 該フィルムの溶解を防止できるからである。  Similar to the formation of a conventional conductor pattern, resist coating (the resist coating may be performed in accordance with a conventional method. However, the slot for rotating the jig after the coating using the slot co one time only or the slot co one time only) The application of the AND spin method is preferable because it can reduce the consumption of the resist and can also be applied to the concave portions.In addition, the slot core is preferably used for the diameter of the jig (10) and the substrate (20). It is good to rotate the slot core around the center of the jig and the substrate.) Exposure and development (exposing the metal thin film other than the desired conductor pattern) Etch removal of the exposed metal thin film, and stripping and removal of resist. When a negative type dry film is used as a film for fixing the substrate material to the substrate, a positive type resist is used here. This is because the dissolution of the film in the developer used in this step can be prevented.

H. その他  H. Other

一応、 ここまでの工程にてプリント配線板としての機能を有するものが製造さ れるので、 後は所望の大きさに切断することでプリント配線板が得られるが、 更 に該プリント配線板にバンプの形成を行う必要があるならば、 切断の前に、 レジ スト塗付、 露光 ·現像 (導体パターン中のバンプ形成個所を露出せしめる) 、 バ ンプ形成 (金イオンを含む溶液を用いたメツキでよい。 尚、 バンプはある程度の 高さを必要とするので、 先ず銅又はニッケル等からなる下地を形成し、 該下地の 表層にのみ金メッキを施せばよい) 、 レジストの剥離 ·除去という一連の操作を 行なうか又は半田ボールを常法に従って所定の位置に被着させればよい。 ここまで、 基板上に導体パターンを新たに形成するケースにて説明してきた が、 本発明の治具を用いる製法の特徴は、 従来は例のないほど極薄の基板 (シリ コンゥエーハ) であってもその薄さに起因する問題を解消し得ることにあるの で、 基板上に既に導体パターンが形成されたもの、 例えば回路形成済みの I に バンプのみを形成するケースにおいても適用し得ること勿論である。 因みに、 従 来の I C製造においては、 厚いままの基板 (シリコンゥエーハ) の裏面を所望の 厚みに物理研削した後にバンプを形成する方法 (バンプを形成する基板は薄いの で当然にハンドリング性が悪い) や厚いままの基板 (シリコンゥェ一ハ) にバン プを形成した後、 ドライエッチング等にて該基板の裏面を所望の厚みに研削する 方法 (ドライエッチング設備を設けるために相当の費用を要す) が適用されてい た。 For the time being, a product having a function as a printed wiring board is manufactured in the steps up to this point. After that, the printed wiring board can be obtained by cutting to a desired size. Before cutting, if necessary, apply resist, expose and develop (expose the bumps in the conductor pattern), and form the bumps (by using a solution containing gold ions). In addition, since the bump needs a certain height, it is only necessary to first form an underlayer made of copper, nickel, or the like, and then apply gold plating only to the surface layer of the underlayer.) Or a solder ball may be applied to a predetermined position according to a conventional method. So far, a case has been described in which a conductor pattern is newly formed on a substrate. However, the feature of the manufacturing method using the jig of the present invention is that an ultra-thin substrate (silicon wafer) which has never been seen before. This is also applicable to the case where a conductor pattern has already been formed on a substrate, for example, a case where only bumps are formed on a circuit-formed I, since the problem caused by the thinness can be solved. It is. By the way, in conventional IC manufacturing, bumps are formed after the back surface of a thick substrate (silicon wafer) is physically ground to a desired thickness. A method in which a bump is formed on a substrate (silicon wafer) that is still bad or thick, and then the back surface of the substrate is ground to a desired thickness by dry etching or the like (a considerable cost is required to provide dry etching equipment). Was applied.

実施例 Example

8インチのシリコンゥエーハ (厚さ : 2 0 0 ΠΙ ;公称径: 2 0 0腿) を用 レ 下記の要領にてプリント配線板 2 0個を製造した。  Using an 8-inch silicon wafer (thickness: 200 mm; nominal diameter: 200 thighs). 20 printed wiring boards were manufactured in the following manner.

1 . 基板材料保持用治具  1. Jig for holding substrate material

下記の仕様の治具 (具体的態様は図 3図示のもの) を使用。  Uses a jig with the following specifications (specifics are shown in Fig. 3).

•縦: 2 3 0腿 ;  • Vertical: 230 thighs;

•横: 2 3 O mm ;  • Horizontal: 23 O mm;

•厚み: 1腿 ;  • Thickness: 1 thigh;

·開口部の径: 1 9 6腿 ;  · Aperture diameter: 196 thighs;

•段部の幅: 2 mm ;  • Step width: 2 mm;

•段部の形成範囲:全周;  • Step formation range: all around;

•上部ス口一プの傾斜:約 7 . 6。  • Upper mouth slope: about 7.6.

•下部ス口一プの傾斜:約 4 . 6 °  • Inclination of lower mouth: about 4.6 °

2 . フィルム被覆  2. Film coating

前記の治具の段部に載置したシリコンゥエー八の両面を、 真空ラミネーター (二チゴーモートン社製 C VA MO D E L 7 2 5 ) を用い、 ドライフィルム (二チゴ一モートン社製 N I T 3 1 5 ;厚さ : 1 5 // m) で該治具ごと被覆して 該シリコンゥエーハを該治具に密着固定し、 次いで、 常法に従い該被覆ドライフ イルムを露光,現像し、 直径: 190匪のワークエリア (両面) を該シリコン ゥエーハー上に確保した。 Using a vacuum laminator (Nichigo Morton CVA MO DEL 7 25), dry film (Nichigo One Morton NIT 3 1) was applied to both sides of the silicon 5; Thickness: 15 // m), covering the jig together with the jig and fixing the silicon wafer tightly to the jig. The film was exposed and developed to secure a work area (both sides) with a diameter of 190 marauders on the silicon wafer.

3. スルーホールの形成  3. Through-hole formation

ゥエツ卜エッチング法にて該ワークエリァ内のシリコンゥエー八にスルー ホール (径: 100 m) を 10個 Z枚形成した。  10 through-holes (diameter: 100 m) were formed in the silicon layer 8 in the work area by Z-etch etching.

4. 金属薄膜一 1の形成  4. Formation of metal thin film 1

スパッタ装置 (日本真空社製 SH— 450) を使用し、 該ワークエリア内の シリコンゥェ一ハ (両面。 スルーホールの内壁を含む) 上に金属薄膜一 1 ( I TO;厚さ : 10 OA) を形成した (対象ゥエーハ枚数: 1枚) 。  Using a sputtering device (SH-450 manufactured by Nihon Vacuum Co.), a metal thin film 1 (ITO; thickness: 10 OA) was placed on a silicon wafer (both sides, including the inner wall of a through hole) in the work area. Formed (Target: Number of wafers: 1).

また、 無電解メツキ法 (メルテックス社製メルプレート Ni— 867M1〜M 2及び Au— 601を使用) にても、 金属薄膜— 1 (1^ 1 +八\1 ;厚さ : 0. 5 m) を形成した (対象ゥエー八枚数: 1枚) 。  The electroless plating method (using Melplate Ni-867M1-M2 and Au-601 manufactured by Meltex Co., Ltd.) can also be applied to the metal thin film-1 (1 ^ 1 + 8 \ 1; thickness: 0.5 m). ) Was formed (the number of target A eight sheets: 1).

5. 金属薄膜一 2の形成  5. Formation of metal thin film 1

無電解メツキ法 (シプレイファーイ一スト社製 Cu Po s i t 251を使 用) にて、 先にスパッタリング法で形成した金属薄膜一 1上に更に金属薄膜一 2 (Cu ;厚さ : 20 im) を形成した。  In the electroless plating method (using Cu Po sit 251 manufactured by Shipley Furist Co., Ltd.), a metal thin film 1 (Cu; thickness: 20 im) is further formed on the metal thin film 11 formed in advance by the sputtering method. Formed.

6. 導体パターンの形成  6. Formation of conductor pattern

前記の金属薄膜一 2上及び無電解メツキ法のみにて形成した金属薄膜一 1上に それぞれレジスト (シプレイファ一^ rースト社製ポジ型レジス卜 : s PR— 6800) を塗付し、 次いで露光 ·現像 ·エッチング · レジスト剥離を行い、 該 シリコンゥェ一ハ (両面) 上に配線パターンを形成した。 尚、 詳細要領は下記の 通り。  A resist (positive resist: s PR-6800, manufactured by Shipley Farst Co., Ltd.) was applied on the metal thin film 1 and the metal thin film 1 formed only by the electroless plating method. A development pattern was formed on the silicon wafer (both sides) by performing development, etching, and resist stripping. The details are as follows.

'使用コ一夕一:平田機ェ社製スロットコ一夕一 (αコ一夕一)  'Used Koichi Yuichi: Hirata Kiyoshi Co., Ltd. Slot Koichiyuichi

• レジスト塗付厚さ : 10 m (乾燥後: 3 m)  • Resist coating thickness: 10 m (after drying: 3 m)

'マスクパターン: 3 mの LZSを使用  'Mask pattern: use 3m LZS

•露光光源: 目白インべス卜メント社製 200 Φ PRO J - 2001を使用 •エッチング液: シプレイ ·ファーイースト社製 V Po s i t E t c h 746を使用  • Exposure light source: 200 Φ PRO J-2001 manufactured by Mejiro Investment Co., Ltd. • Etch solution: VPositeEtch 746 manufactured by Shipley Far East Co., Ltd.

•剥離液:シプレイ · ファ Γ—スト社製リムーバー 1 177 Aを使用 7. バンプの形成 • Stripper: Shipley Faster remover 1 177 A 7. Bump formation

レジス卜 (シプレイファ Γ一スト社製ポジ型レジスト : SPR— 6800) を塗付し、 次いで露光 ·現像 '電気メツキ · レジスト剥離を行い、 該配線パター ンのバンプランド上に金バンプを形成した。 尚、 詳細要領は下記の通り。  A resist (positive resist manufactured by Shipley Pfist Co., Ltd .: SPR-6800) was applied, and then exposure, development, electric plating, and resist stripping were performed to form gold bumps on the bump lands of the wiring pattern. The details are as follows.

'使用コ一夕一:平田機ェ社製スロットコ一夕一 (αコ一夕一) 。 スロットの 向きは該基板の半径方向。  'Use Koichi Yoichi: Hirata Kiyoshi's slot Koichiichi (αKoichiyuichi). The direction of the slot is the radial direction of the substrate.

• レジスト塗付厚さ : 10 im  • Resist coating thickness: 10 im

•マスクパターン:バンプランド径が 100 ΠΙΦ及び 200 ΠΙΦ  • Mask pattern: Bump land diameter of 100 100Φ and 200ΠΙΦ

•露光光源: 目白ィンべストメント社製 200 Φ PRO J - 200 1を使用 ·メツキ液: リロナ一ル社製のエバロン N i BM- 2 (下地用) 及びォ一口 レブトロレス SMT 250 (金メッキ) をそれぞれ使用  • Exposure light source: Use 200 Φ PRO J-2001 manufactured by Mejiro Investment Co., Ltd. Mesh liquid: Evalon NiBM-2 (for base) and Riptorores SMT 250 (gold plated) manufactured by Rironal. Use each

•剥離液:シプレイファ一^ Γースト社製リムーバー 1 1 77 Aを使用  • Peel off liquid: Use Shipper Faust remover 1 1 77 A

8. ダイシング  8. Dicing

従来の I Cゥエーハダイシングに準拠。  Conforms to conventional IC dicing.

できあがったプリント配線板 (20匪ズ 20隨) を上下方向に 5層積層し、 通 電したところ、 全配線板への導通が確認された。 産業上の利用可能性  When the completed printed wiring boards (20 bandages) were stacked in five layers in the vertical direction and electricity was passed, conduction to all the wiring boards was confirmed. Industrial applicability

上記の通り、 本発明によれば、 基板の厚みと電気特性上の要求がマッチした多 段積層可能な極薄のプリント回路板を製造し得るプリント配線板の製造方法を提 供し得る。  As described above, according to the present invention, it is possible to provide a method for manufacturing a printed wiring board capable of manufacturing an ultrathin printed circuit board that can be stacked in multiple stages and that meets the requirements for the thickness of the substrate and the requirements for electrical characteristics.

Claims

請 求 の 範 囲 The scope of the claims 1 . 下記のステップを含んでなることを特徴とするプリント配線板の製造方法: A. 厚みが 5 0; π!〜 3 0 0 ΠΙのシリコンゥェ一ハを準備する ; 1. A method for manufacturing a printed wiring board, comprising the following steps: A. A thickness of 50; Prepare up to 300 wafers of silicon wafer; Β . 該シリコンゥェ一ハをその周縁部のみを保持し得る治具に取付け、 その全面 をフィルムにて被覆し、 該シリコンゥエーハを該治具に固定する ; Β. Attach the silicon wafer to a jig capable of holding only the periphery thereof, cover the entire surface with a film, and fix the silicon wafer to the jig; C . 該フィルムをパ夕一ニングしてシリコンゥェ一八の表裏面を露出させる ; C. patterning the film to expose the front and back of the silicon wafer; D . 該露出せしめられたシリコンゥエー八の所定位置にスルーホールを形成する とともに、 該スルーホールを含む該シリコンウーェハの露出面に金属薄膜を形成 する; D. forming a through hole at a predetermined position of the exposed silicon wafer and forming a metal thin film on an exposed surface of the silicon wafer including the through hole; Ε . 該金属薄膜をパターニングし、 次いでエッチングを行って、 所定の導体パ ターンを得る。  Ε. The metal thin film is patterned and then etched to obtain a predetermined conductor pattern. 2 . 前記の導体パターンの形成後、 更にレジストの塗付、 パ夕一ニングを行い、 次いで該導体パターン上の所定位置に銅又はニッケルを下地層とする金メッキを 施してバンプを形成する、 請求の範囲第 1項に記載の方法。 2. After the formation of the conductor pattern, a resist is applied and the coating is further performed, and then a bump is formed at a predetermined position on the conductor pattern by gold plating using copper or nickel as a base layer. The method according to paragraph 1 above. 3 . 前記のシリコンゥエーハーが 1 0 0 0人〜 5 0 0 O Aの表面粗さを有するも のである、 請求の範囲第 1項又は第 2項に記載の方法。 3. The method according to claim 1 or 2, wherein said silicon wafer has a surface roughness of 100 to 500 OA. 4. 前記のフィルムがネガ型のドライフィルムであり、 前記の金属薄膜のパ ターニングに用いられるレジス卜がポジ型である、 請求の範囲第 1項乃至第 3項 のいずれか 1に記載の方法。 4. The method according to any one of claims 1 to 3, wherein the film is a negative type dry film, and the resist used for patterning the metal thin film is a positive type. . 5 . 前記の金属薄膜の形成が蒸着と無電解 C uメツキ、 又は無電解 N i— A u メツキにて行われる、 請求の範囲第 1項乃至第 4項のいずれか 1に記載の方法。 5. The method according to any one of claims 1 to 4, wherein the metal thin film is formed by vapor deposition and electroless Cu plating or electroless Ni-Au plating. 6 . 前記の無電解 C uメツキの後で、 更に電気メツキを行なう、 請求の範囲第 5 項に記載の方法。 6. The method according to claim 5, wherein an electric plating is further performed after the electroless Cu plating. 7 . 前記のスルーホールの形成がレーザ一穿孔法、 プラズマエッチング法、 又は フォトリソグラフィ一法にて行われる、 請求の範囲第 1項乃至第 6項のいずれか 1に記載の方法。 7. The method according to any one of claims 1 to 6, wherein the formation of the through hole is performed by a laser drilling method, a plasma etching method, or a photolithography method. 8 . その中心部に開口を有し、 該開口近傍にシリコンゥェ一八の周辺部を載置可 能な段部を有するシリコン製プリント配線板製造用の実質的に角形又は円形の治 具であって、 該段部が該治具の厚み方向の中心軸と該シリコンゥエー八の厚み方 向の中心軸とが同軸となるように形成されていること、 該治具が水平な上面と下 面を有し、 該下面から該段部の水平面の内周端に向かって上る直線状の下方スロ —プと該上面から該段部の壁面上端に向かって又は該下方スロープと同じ傾きを もって下る直線状の上方スロープとを有すること、 及び該上 ·下面、 及び該上 下スロープに該開口の径方向に向かう溝であって、 その始終端が該上 ·下面の外 周端と該段部の壁の上端又は該上部スロープの終端及び該段部の水平面の先端で ある複数の溝を有することを特徴とするシリコン製プリント配線板製造用の治 具。 8. A substantially square or circular jig for manufacturing a silicon printed wiring board having an opening in the center thereof and a step near the opening on which a peripheral portion of the silicon wafer 18 can be placed. The step is formed so that the central axis in the thickness direction of the jig and the central axis in the thickness direction of the silicon wire 8 are coaxial; A linear downward slope that rises from the lower surface toward the inner peripheral end of the horizontal surface of the step and a slope from the upper surface toward the upper end of the wall surface of the step or at the same slope as the lower slope. A downwardly extending linear upper slope; and a groove extending radially of the opening on the upper and lower slopes and the upper and lower slopes, the starting and ending ends of which are outer peripheral ends of the upper and lower faces and the step. The upper end of the section wall or the end of the upper slope and the tip of the horizontal plane of the step Silicon printed circuit board jig manufacturing, characterized in that it comprises a. 9 . 前記の治具が一つの'部材からなるものである、 請求の範囲第 8項に記載の治 具。 9. The jig according to claim 8, wherein said jig is formed of one member. 1 0 . 前記の治具が、 それらの下 ·上面で当接する上 ·下二つの部材からなり、 前記の段部がそれぞれの部材に形成され、 前記のシリコンゥエー八の周辺部の載 置が両段部の水平面による挟持であり、 前記の治具の厚み方向の中心軸がそれら 部材の当接面であり、 該上方の部材のスロープが、 該上方の部材の段部の水平面 の先端に向かって下がるものである請求の範囲第 8項に記載の治具。 10. The jig is composed of two members, upper and lower, which abut on the upper surface and the lower surface thereof. The step is formed on each member, and the peripheral portion of the silicon wafer is placed. Are sandwiched by horizontal surfaces of both steps, the center axis in the thickness direction of the jig is a contact surface of these members, and the slope of the upper member is the tip of the horizontal surface of the step of the upper member. 9. The jig according to claim 8, wherein the jig descends toward. 1 1 . 前記の治具が、 それらの下 ·上面で当接する上 ·下二つの部材からなり、 前記の段部が下方の部材にのみ形成され、 前記のシリコンゥエー八の周辺部の載 置が段部の水平面と上方の部材の下面である水平面とによる挟持であり、 前記の 治具の厚み方向の中心軸がそれら部材の当接面より該基板の厚みの 1 2下方の 部材側に下がった位置にあり、 該上方の部材のスロープが、 該下方の部材のス ロープと同じ傾きをもって下がるものである請求の範囲第 8項に記載の治具。 1 1. The jig is composed of two members, upper and lower, which abut on the upper surface and the lower surface thereof, and the step is formed only on the lower member, and the peripheral portion of the silicon wire 8 is mounted on the jig. Is sandwiched between a horizontal surface of the step portion and a horizontal surface that is the lower surface of the upper member, The center axis in the thickness direction of the jig is located at a position lower than the contact surface of the members by 12 members below the thickness of the substrate, and the slope of the upper member is the same as the slope of the lower member. 9. The jig according to claim 8, wherein the jig descends with the same inclination. 1 2 . 前記の上方スロープの傾きが前記の下方スロープの傾きと同じであるが、 その先端は前記の段部の壁部の上端で終了し、 該段部の壁部の深さが前記のシリ コンゥェ一八の厚みより大であり、 その差分に相当する外周厚みと該上方スロー プと同じ傾きのスロープを上に、 そして該段部の水平面に対向する水平面を下に それぞれ有する押え部材を更に有し、 前記のシリコンゥエー八の周辺部の載置が 該段部の水平面と該押え部材の水平面とによる挟持である、 請求の範囲第 9項に 記載の治具。 1 2. The slope of the upper slope is the same as the slope of the lower slope, but the tip ends at the upper end of the wall of the step, and the depth of the wall of the step is A holding member having a thickness greater than the thickness of the silicon wafer 18, a peripheral thickness corresponding to the difference and a slope having the same inclination as the upper slope above, and a horizontal surface facing the horizontal surface of the step below, is provided. The jig according to claim 9, further comprising: placing the peripheral portion of the silicon wire 8 between the horizontal surface of the step portion and the horizontal surface of the pressing member. 1 3 . 請求の範囲第 8項乃至第 1 2項のいずれか 1に記載の治具を用いる、 請求 の範囲第 1項乃至第 7項のいずれか 1に記載の方法。 13. The method according to any one of claims 1 to 7, wherein the jig according to any one of claims 8 to 12 is used.
PCT/JP2002/006711 2001-07-05 2002-07-03 Method for manufacturing printed wiring board Ceased WO2003005786A1 (en)

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JPWO2003005786A1 (en) 2004-10-28
JP4153422B2 (en) 2008-09-24
KR20040017247A (en) 2004-02-26
CN1290390C (en) 2006-12-13
CN1522557A (en) 2004-08-18
KR100914376B1 (en) 2009-08-28

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