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WO2003056475A3 - Systeme, procede et article de fabrication permettant d'estimer une performance potentielle d'une co-conception a partir d'une specification executable - Google Patents

Systeme, procede et article de fabrication permettant d'estimer une performance potentielle d'une co-conception a partir d'une specification executable Download PDF

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Publication number
WO2003056475A3
WO2003056475A3 PCT/GB2002/005750 GB0205750W WO03056475A3 WO 2003056475 A3 WO2003056475 A3 WO 2003056475A3 GB 0205750 W GB0205750 W GB 0205750W WO 03056475 A3 WO03056475 A3 WO 03056475A3
Authority
WO
WIPO (PCT)
Prior art keywords
codesign
estimating
article
manufacture
potential performance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/GB2002/005750
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English (en)
Other versions
WO2003056475A2 (fr
Inventor
Matthew Philip Aubury
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Celoxica Ltd
Original Assignee
Celoxica Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Celoxica Ltd filed Critical Celoxica Ltd
Priority to AU2002352433A priority Critical patent/AU2002352433A1/en
Publication of WO2003056475A2 publication Critical patent/WO2003056475A2/fr
Publication of WO2003056475A3 publication Critical patent/WO2003056475A3/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3447—Performance evaluation by modeling
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3466—Performance evaluation by tracing or monitoring
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/815—Virtual

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Bioinformatics & Cheminformatics (AREA)
  • Bioinformatics & Computational Biology (AREA)
  • Evolutionary Biology (AREA)
  • Quality & Reliability (AREA)
  • Stored Programmes (AREA)
  • Devices For Executing Special Programs (AREA)

Abstract

L'invention concerne un système, un procédé et un article de fabrication permettant d'estimer une performance potentielle d'une co-conception à partir d'une spécification exécutable. En premier lieu, des commandes relatives à des fonctions sont reçues. Ces commandes sont compilées dans un modèle matériel exécutable. Ce modèle est exécuté dans un environnement à fonctionnement virtuel. Des données de contour sont générées au cours de l'exécution puis analysées. Une liste de transferts de données entre au moins une partie des fonctions est également sortie. Une estimation du temps d'exécution de chaque fonction est aussi sortie.
PCT/GB2002/005750 2001-12-21 2002-12-18 Systeme, procede et article de fabrication permettant d'estimer une performance potentielle d'une co-conception a partir d'une specification executable Ceased WO2003056475A2 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2002352433A AU2002352433A1 (en) 2001-12-21 2002-12-18 System, method and article of manufacture for estimating a potential performance of a codesign from an executable specification

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/026,078 US20030121010A1 (en) 2001-12-21 2001-12-21 System, method, and article of manufacture for estimating a potential performance of a codesign from an executable specification
US10/026,078 2001-12-21

Publications (2)

Publication Number Publication Date
WO2003056475A2 WO2003056475A2 (fr) 2003-07-10
WO2003056475A3 true WO2003056475A3 (fr) 2003-10-16

Family

ID=21829754

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/GB2002/005750 Ceased WO2003056475A2 (fr) 2001-12-21 2002-12-18 Systeme, procede et article de fabrication permettant d'estimer une performance potentielle d'une co-conception a partir d'une specification executable

Country Status (3)

Country Link
US (1) US20030121010A1 (fr)
AU (1) AU2002352433A1 (fr)
WO (1) WO2003056475A2 (fr)

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US7203912B2 (en) * 2004-07-21 2007-04-10 Rajat Moona Compiling memory dereferencing instructions from software to hardware in an electronic design
US7315991B1 (en) * 2005-02-23 2008-01-01 Xilinx, Inc. Compiling HLL into massively pipelined systems
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US7243330B1 (en) * 2005-04-21 2007-07-10 Xilinx, Inc. Method and apparatus for providing self-implementing hardware-software libraries
US7444610B1 (en) * 2005-08-03 2008-10-28 Xilinx, Inc. Visualizing hardware cost in high level modeling systems
US8402409B1 (en) * 2006-03-10 2013-03-19 Xilinx, Inc. Method and apparatus for supporting run-time reconfiguration in a programmable logic integrated circuit
US7921046B2 (en) 2006-06-19 2011-04-05 Exegy Incorporated High speed processing of financial information using FPGA devices
US7840482B2 (en) 2006-06-19 2010-11-23 Exegy Incorporated Method and system for high speed options pricing
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US8578347B1 (en) * 2006-12-28 2013-11-05 The Mathworks, Inc. Determining stack usage of generated code from a model
US8069127B2 (en) * 2007-04-26 2011-11-29 21 Ct, Inc. Method and system for solving an optimization problem with dynamic constraints
US8271911B1 (en) * 2007-09-13 2012-09-18 Xilinx, Inc. Programmable hardware event reporting
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US20090132979A1 (en) * 2007-11-19 2009-05-21 Simon Joshua Waters Dynamic pointer dereferencing and conversion to static hardware
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JP5034955B2 (ja) * 2008-01-08 2012-09-26 富士通株式会社 性能評価シミュレーション装置、性能評価シミュレーション方法および性能評価シミュレーションプログラム
US10229453B2 (en) 2008-01-11 2019-03-12 Ip Reservoir, Llc Method and system for low latency basket calculation
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US10121196B2 (en) 2012-03-27 2018-11-06 Ip Reservoir, Llc Offload processing of data packets containing financial market data
US9990393B2 (en) 2012-03-27 2018-06-05 Ip Reservoir, Llc Intelligent feed switch
US11436672B2 (en) 2012-03-27 2022-09-06 Exegy Incorporated Intelligent switch for processing financial market data
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Publication number Publication date
WO2003056475A2 (fr) 2003-07-10
AU2002352433A1 (en) 2003-07-15
US20030121010A1 (en) 2003-06-26

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