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WO2003046918A3 - High performance semiconductor memory devices - Google Patents

High performance semiconductor memory devices Download PDF

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Publication number
WO2003046918A3
WO2003046918A3 PCT/US2002/011740 US0211740W WO03046918A3 WO 2003046918 A3 WO2003046918 A3 WO 2003046918A3 US 0211740 W US0211740 W US 0211740W WO 03046918 A3 WO03046918 A3 WO 03046918A3
Authority
WO
WIPO (PCT)
Prior art keywords
memory devices
high performance
memory device
semiconductor memory
performance semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2002/011740
Other languages
French (fr)
Other versions
WO2003046918A2 (en
Inventor
Jeng-Jye Shau
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Publication of WO2003046918A2 publication Critical patent/WO2003046918A2/en
Anticipated expiration legal-status Critical
Publication of WO2003046918A3 publication Critical patent/WO2003046918A3/en
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/02—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/002—Isolation gates, i.e. gates coupling bit lines to the sense amplifier
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2281—Timing of a read operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/229—Timing of a write operation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)

Abstract

High performance memory device have been realized by apjjling Evenly Scaled Multiple Level Architecture (ESMLA) using block select arrangement. A single-bit4ine-write (SBLW) mechanism (805) allows us to reduce the number of bit lines (BL) by 50% for static memory device (801). The resulting memory device can be as fast as registers files while its area is smaller than prior art high density memory devices. The scaling method of the memory architecture also assures that the speed of the memory devices will scale in the same rate as logic circuit in future IC manufacture technologies.
PCT/US2002/011740 2001-11-26 2002-04-12 High performance semiconductor memory devices Ceased WO2003046918A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US33369401P 2001-11-26 2001-11-26
US60/333,694 2001-11-26

Publications (2)

Publication Number Publication Date
WO2003046918A2 WO2003046918A2 (en) 2003-06-05
WO2003046918A3 true WO2003046918A3 (en) 2009-06-11

Family

ID=23303876

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2002/011740 Ceased WO2003046918A2 (en) 2001-11-26 2002-04-12 High performance semiconductor memory devices

Country Status (2)

Country Link
CN (1) CN1421861A (en)
WO (1) WO2003046918A2 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6987686B2 (en) * 2003-12-11 2006-01-17 International Business Machines Corporation Performance increase technique for use in a register file having dynamically boosted wordlines
KR102557324B1 (en) * 2016-02-15 2023-07-20 에스케이하이닉스 주식회사 Memory device
WO2018004756A1 (en) * 2016-06-27 2018-01-04 Sukalpa Biswas Memory system having combined high density, low bandwidth and low density, high bandwidth memories
CN106527562B (en) * 2016-12-14 2018-04-03 无锡中微亿芯有限公司 A kind of low-power consumption SRAM word line voltage based on FPGA realizes circuit and method
WO2023092290A1 (en) * 2021-11-23 2023-06-01 华为技术有限公司 Read only memory circuit, read only memory, and electronic device
CN117577162B (en) * 2024-01-16 2024-05-14 长鑫存储技术(西安)有限公司 Redundant address register structure, redundant address register array and memory

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5388067A (en) * 1993-04-01 1995-02-07 Nec Corporation Semiconductor memory cell
US5894434A (en) * 1995-12-22 1999-04-13 Texas Instruments Incorporated MOS static memory array
US6009010A (en) * 1997-02-26 1999-12-28 Nec Corporation Static semiconductor memory device having data lines in parallel with power supply lines
US6084425A (en) * 1998-03-16 2000-07-04 Via Technologies, Inc. Apparatus for adjusting impedance of controlling chip on a computer mainboard
US6208565B1 (en) * 2000-02-18 2001-03-27 Hewlett-Packard Company Multi-ported register structure utilizing a pulse write mechanism
US6314042B1 (en) * 1998-05-22 2001-11-06 Mitsubishi Denki Kabushiki Kaisha Fast accessible semiconductor memory device
US6385074B1 (en) * 1998-11-16 2002-05-07 Matrix Semiconductor, Inc. Integrated circuit structure including three-dimensional memory array

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5388067A (en) * 1993-04-01 1995-02-07 Nec Corporation Semiconductor memory cell
US5894434A (en) * 1995-12-22 1999-04-13 Texas Instruments Incorporated MOS static memory array
US6009010A (en) * 1997-02-26 1999-12-28 Nec Corporation Static semiconductor memory device having data lines in parallel with power supply lines
US6084425A (en) * 1998-03-16 2000-07-04 Via Technologies, Inc. Apparatus for adjusting impedance of controlling chip on a computer mainboard
US6314042B1 (en) * 1998-05-22 2001-11-06 Mitsubishi Denki Kabushiki Kaisha Fast accessible semiconductor memory device
US6385074B1 (en) * 1998-11-16 2002-05-07 Matrix Semiconductor, Inc. Integrated circuit structure including three-dimensional memory array
US6208565B1 (en) * 2000-02-18 2001-03-27 Hewlett-Packard Company Multi-ported register structure utilizing a pulse write mechanism

Also Published As

Publication number Publication date
CN1421861A (en) 2003-06-04
WO2003046918A2 (en) 2003-06-05

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