WO2002037565A2

WO2002037565A2 - Method of connecting conductors on different levels of a microelectronic device and associated apparatus

Info

Publication number: WO2002037565A2
Application number: PCT/US2001/045250
Authority: WO
Inventors: Sundeep N. Nangalia; Robert L. Wood; Philip Alan Deane; Bruce William Dudley
Original assignee: MCNC
Current assignee: MCNC
Priority date: 2000-11-06
Filing date: 2001-11-01
Publication date: 2002-05-10
Anticipated expiration: 2003-05-06
Also published as: AU2002220022A1; WO2002037565A3

Abstract

A method of electrically connecting conductors on different levels of a microelectronic device is provided. A dielectric layer is deposited over a first metallic layer and a via is then formed in the dielectric layer extending through the dielectric layer. A via metal is then deposited in the via such that the via is in electrical contact with the first metallic layer. A second metallic layer is then deposited over the via metal such that the second metallic layer is in electrical contact with the via metal. The via metal thereby forms an electrical connection between the first metallic layer and the second metallic layer on opposing surfaces of the dielectric layer. The dielectric layer thereby forms a stencil for deposition of the via metal and an interlevel dielectric separating the first metallic layer from the second metallic layer, while also functioning as a structural substrate for the microelectronic device. A method according to the present invention is useful, for example, to connect a fine pitch conductor on one side of the dielectric layer to a coarse pitch conductor on the opposing side. An associated apparatus is also provided which may also include a microelectronic circuit electrically connected to at least one of the first metallic layer and the second metallic layer.

Description

METHOD OF CONNECTING CONDUCTORS ON DIFFERENT LEVELS OF A MICROELECTRONIC DEVICE AND ASSOCIATED APPARATUS

FIELD OF THE INVENTION The present invention relates to microelectronic devices and, more particularly, to a method of connecting conductors on different levels of a microelectronic device and associated apparatus.

BACKGROUND OF THE INVENTION Semiconductor devices are typically fabricated according to a layer methodology, wherein, for example, a blanket layer is deposited over a substrate. The blanket layer may then be coated with a photoresist that is patterned to selectively define areas of the photoresist which remain on the blanket layer, the areas of the photoresist remaining on the blanket layer typically defining the portions of the blanket layer to be removed. The blanket layer is then etched to remove the unwanted portions thereof before the photoresist is thereafter removed. The remaining portions of the blanket layer define the desired features in the particular layer of the device. Such features may include, for example, bonding pads or metallization lines corresponding to the device circuitry.

An alternative layer fabrication method typically involves depositing and patterning a photoresist layer over the substrate such that the remaining photoresist defines the desired features for a particular layer. A material is then deposited within the open areas defined by the photoresist. The photoresist is thereafter removed such that the material remains deposited over the substrate and comprises the desired features in the desired configuration.

A typical microelectronic device may comprise many layers fabricated according to one of the above processes. Such devices may include various metallization layers for electrically connecting other metal layers or for allowing electrical connections to be formed externally to the device. However, metallization layers in a microelectronic device are generally more sensitive to manufacturing defects encountered in the fabrication process than are dielectric layers. For instance, a dust particle may be enough to disrupt continuity in a metallization line or an incomplete etching process may cause a short circuit between metallization lines. Defective metallization often results in an unusable device and reduces the yield of the device fabrication process.

One proposed solution to the problem of high sensitivity of the metallization layers to manufacturing defects has been to move certain metallization layers from the device to a separate substrate. Such a process is used in, for example, Seamless High Off-Chip Connectivity (SHOCC) type devices. Removal of metallization layers increases the process yield and reduces the number of manufacturing steps necessary to fabricate the device. However, an ongoing rend in the production of semiconductor devices is the move toward devices with progressively smaller features, wherein a feature may comprise, for example, a metallization line as described herein. Thus, a SHOCC type device is typically configured with very fine pitch electrical conductors for electrically interfacing with the metallization layers on the separate substrate, wherein the separate substrate may be, for example, an interposer. On the opposite side of the separate substrate, the metallization layers are typically connected to larger scale devices or external electrical connections and therefore require large pitch conductors for forming the necessary electrical connections. These large pitch conductors may be configured in, for example, a Ball-Grid- Array (BGA) type coarse pitch. Thus, an interposer may be required to route very fine pitch conductors from one surface thereof to coarse pitch conductors at the opposite surface.

Interposers or separate substrates for metallization layers are commonly fabricated in a build-up process or are formed from pre-existing substrate materials such as, for example, PC board on FR4 or ceramic circuits on ceramic green tape. In order to accommodate fine pitch conductor SHOCC type devices, holes or other features of a correspondingly fine pitch must be formed in the substrate/interposer. Laser ablation has typically been the only method capable of forming the necessary fine pitch holes/features in the substrate. However, laser ablation is limited in processing flexibility and may, for instance, be unable to readily compensate for variances in the parameters defining the substrate. For example, should the thickness or the material composition of the substrate vary from a specified range, the laser may not be able to produce the holes/features according to specification without optimizing the laser power beforehand or reworking the substrate to achieve the desired configuration. In addition, laser ablation of holes/features may be a time-consuming process limited by, for example, the number of laser devices and the speed of the mechanism controlling the position of the lasers for the particular process. Further, laser ablation methods may be limited in the magnitude of the pitch that may be produced, wherein the pitch of the holes/features capable of being produced by the laser device may not be as fine as required by the particular process. Similar situations may be encountered in other instances where an electrical connection through a substrate is required. Thus, there exists a need for a process for forming an electrical connection between conductors on opposite surfaces of a substrate, wherein the process can be relatively easily applied in a cost effective manner while permitting flexibility in the miniaturization of the device electrically connected thereto.

As with any fabrication process, a simpler process is generally more advantageous. Thus, a fabrication method which can achieve the same or better quality product with about the same material cost and with the same or fewer processing steps is highly preferred, especially if elimination of steps in the fabrication process reduces labor costs and eliminates the need for expensive manufacturing equipment. In addition, it is generally desirable to retain flexibility in a fabrication process for semiconductor devices such as integrated circuits. Thus, it would be advantageous to have a process for forming an electrical connection between conductors on opposite surfaces of a substrate in a microelectronic device that can be relatively easily applied in a cost effective manner while permitting flexibility in the configuration and miniaturization of the microelectronic device electrically connected thereto. This process should be simple and flexible, while preferably producing an improved device over prior art methods. SUMMARY OF THE INVENTION The above and other needs are met by the present invention which, in one embodiment, provides a method of electrically connecting conductors on different levels of a microelectronic device. Generally, a dielectric layer is deposited over a first metallic layer before a via is formed in the dielectric layer such that the via extends through the dielectric layer. A via metal is then deposited in the via, using the dielectric layer as a stencil, so as to at least partially fill the via. Preferably, the via metal is deposited such that it is electrically connected to the first metallic layer. A second metallic layer is then deposited over the via metal such that the second metallic layer is also electrically connected to the via metal. The via metal thereby forms an electrical connection between the first metallic layer and the second metallic layer on opposing surfaces of the dielectric layer. The dielectric layer thus forms both a stencil for the deposition of the via metal and an interlevel dielectric between the two metallic layers, while functioning as a structural substrate for the microelectronic device. Preferably, the dielectric layer is insolublized following deposition thereof over the first metallic layer and prior to depositing the via metal in the via. In one particularly advantageous embodiment, the dielectric layer is comprised of a photoimagable spin-on epoxy or polymer. In some instances, the first metallic layer may be configured in a Ball-Grid- Array (BGA) type coarse pitch, while the second metallic layer may be configured in a seamless high off-chip connectivity (SHOCC) type fine pitch. In one embodiment of the present invention, the method may further comprise electrically connecting a microelectronic circuit to at least one of the first metallic layer and the second metallic layer. One advantageous embodiment of the present invention further comprises a particular method of electrically connecting conductors on different levels of a microelectronic device. First, a sacrificial layer is deposited over a microelectronic carrier. A first metallic layer is then deposited over the sacrificial layer. A dielectric layer is then deposited over the first metallic layer, whereafter a via is formed in the dielectric layer extending through the dielectric layer. A via metal is then deposited in the via, using the dielectric layer as a stencil, so as to at least partially fill the via and such that the via metal is electrically connected to the first metallic layer. A second metallic layer is then deposited over the via metal such that the second metallic layer is electrically connected to the via metal. Since the via metal electrically connects the first metallic layer to the second metallic layer on opposing surfaces of the dielectric layer, the dielectric layer forms both a stencil for the deposition of the via metal and an interlevel dielectric, separating the first metallic layer from the second metallic layer, while also functioning as a structural substrate for the microelectronic device.

In some instances, the sacrificial layer may comprise a dissolvable layer deposited over the microelectronic carrier, followed by an etch stop layer deposited over the dissolvable layer, wherein the dissolvable layer may be comprised of phosphosilicate glass and the etch stop layer may be comprised of titanium.

Further, according to one embodiment of the present invention, the first metallic layer may further comprise a plating base deposited over the sacrificial layer, wherein the plating base may be comprised of copper, aluminum, gold, and/or chromium. According to one particularly advantageous embodiment, the method may further include selectively depositing a contact layer over the first metallic layer prior to depositing the dielectric layer, wherein the contact layer may be comprised of, for example, a layer of gold deposited between opposing layers of nickel, nickel, gold, copper, and/or a solder material.

Once the dielectric layer has been deposited over the first metallic layer, the method may further comprise insolublizing the dielectric layer prior to depositing the via metal within the via, wherein the dielectric layer may be comprised of, for example, a photoimagable spin-on epoxy or polymer. After the via is formed in the dielectric layer, a metal fill layer is deposited over the dielectric layer so as to at least fill the via and form the via metal which may be comprised of, for example, copper, nickel, gold, and or a solder material. In one advantageous embodiment, the dielectric layer is then planarized such that the fill layer fills the via and forms a coplanar surface with the dielectric layer.

Following the deposition of the second metallic layer, the sacrificial layer is removed, such as by dissolving the dissolvable layer, so as to separate the dielectric layer from the microelectronic carrier. In some instances, the plating base and a nickel layer of the contact layer may also be removed so as to expose the gold layer of the contact layer. A microelectronic circuit may then be electrically connected to at least one of the contact layer and the second metallic layer. Generally, the first metallic layer may be configured in a BGA type coarse pitch and the second metallic layer may be configured in a SHOCC type fine pitch.

Another advantageous aspect of the present invention comprises an alternate method of electrically connecting conductors on different levels of a microelectronic device. After a sacrificial layer, a first metallic layer, and a dielectric layer have been deposited over the microelectronic carrier, a via is formed in the dielectric layer extending through the dielectric layer. A metallic conformal layer is then deposited over the dielectric layer such that the conformal layer is electrically connected to the first metallic layer through the via. A via metal is then deposited in the via so as to at least partially fill the via and such that the via metal is electrically connected to the conformal layer. A second metallic layer is then deposited over the via metal such that the conformal layer and the via metal thereby form an electrical connection between the first metallic layer and the second metallic layer on opposing surfaces of the dielectric layer. In this manner, the dielectric layer thereby forms a stencil for the deposition of the via metal and an interlevel dielectric, while also functioning as a structural substrate for the microelectronic device.

According to one advantageous embodiment of the present invention, the sacrificial layer further comprises a dissolvable layer over the microelectronic substrate, wherein the dissolvable layer may comprise, for instance, phosphosilicate glass. Further, the first metallic layer may comprise a selectively deposited etch stop layer over the sacrificial layer, wherein the etch stop layer may comprise, for example, titanium. Once the dielectric layer has been deposited over the first metallic layer, the method may further comprise insolublizing the dielectric layer prior to depositing the conformal layer, wherein the dielectric layer may be comprised of, for example, a photoimagable spin-on epoxy or polymer. The conformal layer may further comprise a plating base deposited over the dielectric layer, wherein the plating base may include, for example, a layer of titanium over a layer of phase chromium-copper over a layer of copper, copper, chromium, aluminum, nickel, and/or gold. Once the conformal layer has been deposited, the via metal is deposited as a fill layer over the conformal layer, wherein the via metal at least fills the via and may be comprised of, for example, copper, gold, nickel, and/or a solder material. The dielectric layer is then planarized following deposition of the fill layer such that the fill layer and the conformal layer fill the via and form a coplanar surface with the dielectric layer. Following deposition of the second metallic layer, the sacrificial layer is removed as to separate the dielectric layer from the microelectronic carrier. Thereafter, the first metallic layer is removed so as to expose the conformal layer. Preferably, the first metallic layer is configured in a BGA type coarse pitch while the second metallic layer is configured in a SHOCC type fine pitch. A microelectronic circuit may thereafter be electrically connected to at least one of the conformal layer and the second metallic layer. A further advantageous aspect of the present invention comprises a microelectronic device having an electrical connection through a dielectric layer. According to one embodiment, the device comprises a first conductor, a second conductor, and a dielectric layer. The dielectric layer is deposited over the first conductor and de.fines a via filled with a via metal. The dielectric layer is preferably used as a stencil for deposition of the via metal in the via. The second conductor is thereafter deposited over the via metal to electrically connect the first conductor to the second conductor through the dielectric layer such that the dielectric layer forms both a stencil for the deposition of the via metal and an interlevel dielectric in the microelectronic device, while also functioning as a structural substrate for the microelectronic device. In one advantageous embodiment, one of the conductors is configured in a BGA type coarse pitch while the other conductor is configured in a SHOCC type fine pitch. Preferably, the dielectric layer comprises a photoimagable spin-on epoxy or polymer, while the via metal is comprised of, for example, copper, nickel, gold, and/or a solder material. The microelectronic device may further comprise a microelectronic circuit electrically connected to at least one of the first conductor and the second conductor.

Thus, embodiments of the present invention advantageously provide a process for forming an electrical connection between conductors on opposing surfaces of a substrate in a microelectronic device that is relatively easily applied in a cost-effective manner while permitting flexibility in the configuration miniaturization of the microelectronic device electrically connected thereto. Using a photoimagable spin-on epoxy or polymer as a stencil for the deposition of the via metal, while retaining the epoxy between metal layers as the interlevel dielectric, provides a structural substrate for the microelectronic device while reducing the amount of process steps as compared to the prior art while producing a simpler and more flexible process.

BRIEF DESCRIPTION OF THE DRAWINGS Some of the advantages of the present invention having been stated, others will appear as the description proceeds, when considered in conjunction with the accompanying drawings, which are not necessarily drawn to scale, in which: FIG. 1 is a cross-sectional view schematically illustrating an apparatus for connecting conductors on different levels of a microelectronic device according to one embodiment of the present invention.

FIGS. 2A - 2G are cross-sectional views schematically illustrating a method of connecting conductors on different levels of a microelectronic device according to an embodiment of the present invention.

FIGS. 3A - 3H are cross-sectional views schematically illustrating a method of connecting conductors on different levels of a microelectronic device according to an alternate embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like numbers refer to like elements throughout.

FIG. 1 schematically illustrates a cross-section of a microelectronic device having an electrical connection through a dielectric layer according to one embodiment of the present invention. Some microelectronic devices such as, for example, seamless high off-chip conductivity (SHOCC) type devices, move certain metallization layers from the device to a separate substrate to reduce the number of manufacturing steps necessary to fabricate the device while increasing the yield of the process. Accordingly, the separate substrate having the metallization layers thereafter serves as an interposer for electrically connecting the microelectronic device into corresponding electronic circuitry. A SHOCC type device arrangement is indicated generally by the numeral 100 in FIG. 1 and comprises a microelectronic device 110, an interposer 120, and other electronic circuitry 130. The interposer 120 generally comprises a dielectric layer 122 having a first conductor 124 on one surface and a second conductor 126 on the opposing surface. A via metal 128 electrically connects the first conductor 124 to the second conductor 126 through the dielectric layer 122. Typically, the microelectronic device 110 has a circuit contact 112 that contacts and forms an electrical connection with the second conductor 126, while the electronic circuitry 130 has a corresponding contact 132 that contacts and forms an electrical connection with the first conductor 124. In a particularly advantageous embodiment of the present invention, the circuit contact 112 and the second conductor 126 are scaled in a SHOCC type fine pitch while the contact 132 and the first conductor 124 are configured in a BGA type coarse pitch. The use of the interposer 120 thereby provides a more robust electrical connection than if the circuitry contact 112 were to directly interface with the contact 132. In addition, the interposer 120 provides a more flexible mechanism for interfacing various conductors. For example, the second conductor 126 may be separated into a plurality of portions each engaging a via metal 128 to form an electrical connection with the first conductor 124, thereby allowing multiple circuit contacts 112 to be electrically connected to the contact 132 on the opposing surface of the interposer 120. Still further, according to embodiments of the present invention, the interposer 120 is "built-up" in an layering process, wherein the dielectric layer 122 serves both as a stencil for the deposition of the via metal 128 as well as an interlevel dielectric separating the first conductor 124 from the second conductor 126. The built-up fabrication method thereby provides increased flexibility for varying the scale and configuration of the contacts 112 and 132 while providing a more precise and consistent interposer 120 than with prior art methods which form the necessary features in the interposer 120 using laser ablation.

FIGS. 2A-2G disclose a sequence of cross-sectional views schematically illustrating a method of electrically connecting conductors on different levels of a microelectronic device, indicated generally by the numeral 200, according to one embodiment of the present invention. As shown in FIG. 2 A, the fabrication process starts with a microelectronic carrier 210 such as, for example, a silicon wafer, over which is deposited a sacrificial layer 220. Typically, as with most semiconductor devices, the features of the device are fabricated over a microelectronic carrier comprising, for instance, a silicon wafer. It will thus be understood by those having skill in the art that when a layer or element is described herein as being over another layer or element, it may be formed directly on the layer, at the top, bottom, or side surface area thereof. Alternatively, one or more intervening layers may be provided between the layers.

The sacrificial layer 220 may comprise, for example, a layer of phosphosilicate glass (PSG). In some instances, an etch stop pad 230 may be deposited over the sacrificial layer 220, wherein the pad 230 may be comprised of, for example, titanium. As shown in FIG. 2B, a plating base 240 is then deposited, generally as a blanket layer, over the sacrificial layer 220 and the etch stop pad 230. Preferably, the plating base 240 is comprised of, for example, copper that is evaporated or sputter-coated over the preceding layer(s), but may also be comprised of aluminum, gold, and/or chromium. The purpose of the etch stop pad 230 and the plating base 240 will become more apparent when described further herein.

As shown in FIG. 2C, a photoresist 250 is deposited over the plating base 240 and then patterned to selectively define open an area therein, generally in a location where the etch stop pad 230 is underlying the plating base 240. Spin coating of the photoresist 250 with subsequent patterning is well known to those skilled in the art and will not be described further herein. Once the open area in the photoresist 250 over the etch stop pad 230 has been defined, a contact layer 260 is deposited over the plating base 240 in the open area. In a particularly advantageous embodiment, the contact layer 260 comprises a layer of nickel 260a with a layer of gold 260b deposited thereover, and a second nickel layer 260c deposited over the gold layer 260b. The two nickel layers 260a and 260c and the gold layer 260b may all be deposited using, for example, an electroplating process. However, the contact layer 260 may also comprise nickel, gold, copper, and/or a solder material. Once the contact layer 260 has been deposited, the photoresist 250 is removed.

As shown in FIG. 2D, once the contact layer 260 has been deposited, a dielectric layer 270 is deposited over the contact layer 260. The dielectric layer 270 may comprise, for example, a photoimagable spin-on epoxy or polymer. The dielectric layer 270 may then be patterned and selective portions thereof removed such that the dielectric layer 270 defines a via 280 over the contact layer 260. A via metal 282 is then deposited so as to at least partially fill the via 280, as shown in FIG. 2E. According to one advantageous embodiment of the present invention, the dielectric layer 270 may be insolublized following deposition thereof and prior to deposition of the via metal 282. Further, following deposition of the via metal 282, the dielectric layer 270 is planarized to obtain a flat surface. In some instances, the dielectric layer 270 may be planarized by a chemical-mechanical polishing (CMP) process. Preferably, the planarizing process planarizes both the dielectric layer 270 and the via metal 282 such that the via metal 282 fills the via 280 and forms a coplanar surface with the dielectric layer 270. Thereafter, a thin film circuit 290 is formed over the dielectric layer 270 as shown in FIG. 2F. The circuit 290 may comprise, for example, a benzocyclobutene (BCB) layer 290a, with an opening defined thereby over the via metal 282. A second metallic layer 290b such as, for instance, an aluminum line is then deposited in the opening defined by the BCB layer 290a by an evaporation process such that the second metallic layer 290b is in electrical contact with the via metal 282.

As shown in FIG. 2G, the sacrificial layer 220 is then removed by dissolution such that the microelectronic carrier 210 is separated from the device 200. Preferably, the etch stop 230, the plating base 240, and one of the nickel layers 260a are all removed such that the gold layer 260b is exposed. Accordingly, the via metal 282 forms an electrical connection between the second metallic layer 290b disposed on one side of the dielectric layer 270 to the nickel layer 260c, and thus the gold layer 260b, generally disposed on the opposite surface of the dielectric layer 270. According to this process, the dielectric layer 270 is used as a stencil for the deposition of the via metal 282, but also remains in the final device 200 as a structural substrate for the device 200 that also serves as the interlevel dielectric between the contact layer 260 and the second metallic layer 290b.

FIGS. 3A-3H disclose a cross-sectional sequence schematically illustrating an alternate method of electrically connecting conductors on different levels of a microelectronic device, the microelectronic device being indicated generally by the numeral 300. As shown in FIG. 3A, the process begins with a sacrificial layer 320 deposited over a microelectronic carrier 310, wherein the sacrificial layer 320 may comprise, for example, phosphosilicate glass while the microelectronic carrier 310 may be, for instance, a silicon wafer. An etch stop pad 330 may thereafter be selectively deposited over the sacrificial layer 320 as a first metallic layer 330 and may be comprised of, for example, titanium.

As shown in FIG. 3B, a dielectric layer 340 is then deposited over the first metallic layer 330 and the sacrificial layer 320 in a blanket layer, wherein the dielectric layer 340 may be comprised of a photoimagable spin-on epoxy or polymer. The dielectric layer 340 is thereafter patterned so as to define a via 350 over the first metallic layer 330 extending through the dielectric layer 340. Once the via 350 is formed, the dielectric layer 340 is insolublized.

As shown in FIG. 3D, a plating base 360 is then deposited over the dielectric layer 340, wherein the plating base 360 may be comprised of copper, deposited by an evaporation process to form a conformal coating over the dielectric layer 340 without filling the via 350. In some instances, the plating base 340 may include a layer of phase chromium-copper (not shown) deposited over the copper, further with a layer of titanium (not shown) deposited thereover, wherein the phase chromium-copper comprises the underbump metallurgy as is known in the art. In other instances, the plating base 360 may also be comprised of chromium, aluminum, nickel, and/or gold.

As shown in FIG. 3E, a photoresist 370 is deposited over the plating base 360 and patterned to define an open area corresponding to the via 350. A via metal 380 is thereafter deposited in the via 350, wherein the via metal 380 may be comprised of copper deposited by an electroplating process or other materials such as, for example, nickel, gold, and/or a solder material. After the photoresist 370 is removed, the dielectric layer 340 is planarized by, for example, a CMP process to obtain a flat surface as shown in FIG. 3F. Following the CMP process, the plating base 360 and the via metal 380 combine to fill the via 350 and to form a coplanar surface with the dielectric layer 340.

As shown in FIG. 3G, a thin film circuit 390 is formed over the planarized dielectric layer 340. The thin film circuit 390 may further comprise, for example, an insulating layer 390a and a second metallic layer 390b. In some instances, the insulating layer may comprise spin cast benzocyclobutene (BCB), while the second metallic layer 390b may comprise an aluminum line formed by evaporation within an opening formed in the insulating layer 390a over the via 350. Thus, an electrical connection is formed between the second metallic layer 390b, the via metal 380, and the plating base 360. As shown in FIG. 3H, the sacrificial layer 320 is then dissolved to separate the carrier 310 from the dielectric layer 340 and the first metallic layer 330 also removed to expose the plating base 360. An electrical connection is therefore formed between the second metallic layer 390b and the plating base 360 by way of the. via metal 380. The dielectric layer 340 thereby serves as both a stencil for the deposition of the via metal 380 and the plating base 360 as well as an interlevel dielectric, while functioning as a structural substrate for the device 300.

While these described methods illustrate some embodiments of the present invention, a common feature is the use of a dielectric layer that serves as a stencil for a subsequent deposition process, but also remains in the device as a structural substrate as well as an interlevel dielectric. In this manner, the number of process steps generally required to build up such a device are reduced. For example, the deposition of a dielectric layer would ordinarily require the deposition of the dielectric layer, followed by a photoresist layer and a photoresist patterning step to define portions of the dielectric layer to be removed. The dielectric layer would then have to be etched to form the necessary features before the photoresist is removed. Thus, according to embodiments of the present invention, the same result may be achieved by the deposition of a dielectric layer with subsequent patterning to define the desired features, before the dielectric layer is insolublized to remain in place and to serve as a structural member in the device. Generally, such an elimination of process steps is advantageous in a manufacturing process. However, embodiments of the present invention also provide further advantages in that a build-up method of manufacturing an electronic device as described is more flexible than prior art processes employing laser ablation of existing substrates to form the necessary device. Embodiments of the present invention, therefore, provide a process for forming an electrical connection between conductors on ^* opposite surfaces of a substrate in a microelectronic device that is relatively easily applied, is generally cost effective, and permits flexibility in the configuration of the device so as to be applicable to a wide variety of microelectronic devices, also taking into account the scale of such devices.

Many modifications and other embodiments of the invention will come to mind to one skilled in the art to which this invention pertains having the benefit of the teachings presented in the foregoing descriptions and the associated drawings. Therefore, it is to be understood that the invention is not to be limited to the specific embodiments disclosed and that modifications and other embodiments are intended to be included within the scope of the appended claims. Although specific terms are employed herein, they are used in a generic and descriptive sense only and not for purposes of limitation.

Claims

THAT WHICH IS CLAIMED:

1. A method of electrically connecting conductors on different levels of a microelectronic device, comprising: depositing a dielectric layer over a first metallic layer; forming a via extending through the dielectric layer; depositing a via metal in the via, using the dielectric layer as a stencil, so as to at least partially fill the via and such that the via metal is electrically connected to the first metallic layer; and depositing a second metallic layer over the via metal such that the second metallic layer is electrically connected to the via metal, the via metal thereby forming an electrical connection between the first metallic layer and the second metallic layer on opposing surfaces of the dielectric layer, the dielectric layer thereby forming a stencil and an interlevel dielectric and functioning as a structural substrate for the microelectronic device.

2. A method according to Claim 1 further comprising insolublizing the dielectric layer following deposition thereof and prior to depositing the via metal, the dielectric layer being comprised of at least one of a photoimagable spin-on epoxy and a photoimagable spin-on polymer.

3. A method according to Claim 1 further comprising electrically connecting a microelectronic circuit to at least one of the first metallic layer and the second metallic layer.

4. A method according to Claim 1 wherein depositing a dielectric layer further comprises depositing a dielectric layer over a first metallic layer configured in a Ball-Grid- Array (BGA) type coarse pitch.

5. A method according to Claim 1 wherein depositing a second metallic layer further comprises depositing a second metallic layer configured in a seamless high off-chip connectivity (SHOCC) type fine pitch.

6. A method of electrically connecting conductors on different levels of a microelectronic device, comprising: depositing a sacrificial layer over a microelectronic carrier; depositing a first metallic layer over the sacrificial layer; depositing a dielectric layer over the first metallic layer; forming a via extending through the dielectric layer; depositing a via metal in the via, using the dielectric layer as a stencil, so as to at least partially fill the via and such that the via metal is electrically connected to the first metallic layer; and depositing a second metallic layer over the via metal such that the second metallic layer is electrically connected to the via metal, the via metal thereby forming an electrical connection between the first metallic layer and the second metallic layer on opposing surfaces of the dielectric layer, the dielectric layer thereby forming a stencil and an interlevel dielectric and functioning as a structural substrate for the microelectronic device.

7. A method according to Claim 6 wherein depositing a sacrificial layer further comprises depositing a dissolvable layer over the microelectronic substrate, the dissolvable layer being comprised of phosphosilicate glass.

8. A method according to Claim 7 wherein depositing a sacrificial layer further comprises selectively depositing an etch stop layer over the dissolvable layer, the etch stop layer being comprised of titanium.

9. A method according to Claim 6 wherein depositing a first metallic layer further comprises depositing a plating base over the sacrificial layer, the plating base being comprised of at least one of copper, aluminum, gold, and chromium.

10. A method according to Claim 6 further comprising selectively depositing a contact layer over the first metallic layer, prior to depositing the dielectric layer, the contact layer comprising at least one of a layer of gold deposited between opposing layers of nickel, nickel, gold, copper, and a solder material.

11. A method according to Claim 6 further comprising insolublizing the dielectric layer following deposition thereof and prior to depositing the via metal, the dielectric layer being comprised of at least one of a photoimagable spin-on epoxy and a photoimagable spin-on polymer.

12. A method according to Claim 6 wherein depositing a via metal further comprises depositing a metal fill layer over the dielectric layer so as to at least fill the via, the fill layer being comprised of at least one of nickel, gold, copper, and a solder material.

13. A method according to Claim 6 further comprising planarizing the dielectric layer following deposition of the via metal such that the via metal fills the via and forms a coplanar surface with the dielectric layer.

14. A method according to Claim 6 further comprising removing the sacrificial layer so as to separate the first metallic layer from the microelectronic carrier following deposition of the second metallic layer.

15. A method according to Claim 10 further comprising removing the sacrificial layer so as to separate the plating base from the microelectronic carrier following deposition of the second metallic layer.

16. A method according to Claim 15 further comprising removing the plating base following removal of the sacrificial layer.

17. A method according to Claim 16 wherein the contact layer comprises a layer of gold deposited between opposing layers of nickel and the method further comprising removing a nickel layer of the contact layer so as to expose the gold layer of the contact layer following removal of the plating base.

18. A method according to Claim 10 further comprising electrically connecting a microelectronic circuit to at least one of the contact layer and the second metallic layer.

19. A method according to Claim 6 wherein depositing a first metallic layer further comprises depositing a first metallic layer configured in a Ball-Grid- Array (BGA) type coarse pitch over the sacrificial layer.

20. A method according to Claim 6 wherein depositing a second metallic layer further comprises depositing a second metallic layer configured in a seamless high off-chip connectivity (SHOCC) type fine pitch.

21. A method of electrically connecting conductors on different levels of a microelectronic device, comprising: depositing a sacrificial layer over a microelectronic carrier; depositing a first metallic layer over the sacrificial layer; depositing a dielectric layer over the first metallic layer; forming a via extending through the dielectric layer; depositing a conformal layer over the dielectric layer such that the conformal layer is electrically connected to the first metallic layer through the via; depositing a via metal in the via so as to at least partially fill the via and such that the via metal is electrically connected to the conformal layer; and depositing a second metallic layer over the via metal such that the second metallic layer is electrically connected to the via metal, the conformal layer and the via metal thereby forming an electrical connection between the first metallic layer and the second metallic layer on opposing surfaces of the dielectric layer, the dielectric layer thereby foraiing a stencil and an interlevel dielectric and functioning as a structural substrate for the microelectronic device.

22. A method according to Claim 21 wherein depositing a sacrificial layer further comprises depositing a dissolvable layer over the microelectronic substrate, the dissolvable layer being comprised of phosphosilicate glass.

23. A method according to Claim 21 wherein depositing a first metallic layer further comprises selectively depositing an etch stop layer over the sacrificial layer, the etch stop layer being comprised of titanium.

24. A method according to Claim 21 further comprising insolublizing the dielectric layer following deposition thereof and prior to depositing the conformal layer, the dielectric layer being comprised of at least one of a photoimagable spin-on epoxy and a photoimagable spin-on polymer.

25. A method according to Claim 21 wherein depositing a conformal layer further comprises depositing a plating base over the dielectric layer, the plating base being comprised of at least one of copper, chromium, aluminum, nickel, gold, and a layer of titanium over a layer of phase chromium-copper over a layer of copper.

26. A method according to Claim 21 wherein depositing a via metal further comprises depositing a fill layer over the conformal layer so as to at least fill the via, the fill layer being comprised of at least one of nickel, gold, copper, and a solder material.

27. A method according to Claim 21 further comprising planarizing the dielectric layer following deposition of the via metal such that the via metal and the conformal layer fill the via and form a coplanar surface with the dielectric layer.

28. A method according to Claim 21 further comprising removing the sacrificial layer so as to separate the first metallic layer from the microelectronic carrier following deposition of the second metallic layer.

29. A method according to Claim 28 further comprising removing the first metallic layer so as to expose the conformal layer following the removal of the sacrificial layer.

30. A method according to Claim 29 further comprising electrically connecting a microelectronic circuit to at least one of the conformal layer and the second metallic layer.

31. A method according to Claim 21 wherein depositing a first metallic layer further comprises depositing a first metallic layer configured in a Ball-Grid- Array (BGA) type coarse pitch over the sacrificial layer.

32. A method according to Claim 21 wherein depositing a second metallic layer further comprises depositing a second metallic layer configured in a seamless high off-chip connectivity (SHOCC) type fine pitch.

33. A microelectronic device having an electrical connection through a dielectric layer, comprising: a first conductor; a dielectric layer deposited over the first conductor and defining a via filled with a via metal, wherein the dielectric layer functions as a stencil for deposition of the via metal in the via; and a second conductor deposited over the via metal and dielectric layer, electrically connecting the first conductor to the second conductor through the dielectric layer, the dielectric layer thereby forming a stencil and an interlevel dielectric and functioning as a structural substrate for the microelectronic device.

34. A microelectronic device according to Claim 33 wherein at least one of the first and second conductors is configured in a Ball-Grid- Array (BGA) type coarse pitch.

35. A microelectronic device according to Claim 33 wherein at least one of the first and second conductors is configured in a seamless high off-chip connectivity (SHOCC) type fine pitch.

36. A microelectronic device according to Claim 33 wherein the dielectric layer comprises at least one of a photoimagable spin-on epoxy and a . photoimagable spin-on polymer.

37. A microelectronic device according to Claim 33 wherein the via metal is comprised of at least one of nickel, gold, copper, and a solder material.

38. A microelectronic device according to Claim 33 further comprising a microelectronic circuit electrically connected to at least one of the first conductor and the second conductor.