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WO2002033843A1 - Circuit d'attaque - Google Patents

Circuit d'attaque Download PDF

Info

Publication number
WO2002033843A1
WO2002033843A1 PCT/DE2000/003681 DE0003681W WO0233843A1 WO 2002033843 A1 WO2002033843 A1 WO 2002033843A1 DE 0003681 W DE0003681 W DE 0003681W WO 0233843 A1 WO0233843 A1 WO 0233843A1
Authority
WO
WIPO (PCT)
Prior art keywords
voltage
driver circuit
transmission line
switching element
circuit according
Prior art date
Application number
PCT/DE2000/003681
Other languages
German (de)
English (en)
Inventor
Marten Swart
Original Assignee
Siemens Aktiengesellschaft
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Aktiengesellschaft filed Critical Siemens Aktiengesellschaft
Priority to PCT/DE2000/003681 priority Critical patent/WO2002033843A1/fr
Publication of WO2002033843A1 publication Critical patent/WO2002033843A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B3/00—Line transmission systems
    • H04B3/54—Systems for transmission via power distribution lines
    • H04B3/542—Systems for transmission via power distribution lines the information being in digital form
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B2203/00—Indexing scheme relating to line transmission systems
    • H04B2203/54—Aspects of powerline communications not already covered by H04B3/54 and its subgroups
    • H04B2203/5462—Systems for power line communications
    • H04B2203/547—Systems for power line communications via DC power distribution
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B2203/00—Indexing scheme relating to line transmission systems
    • H04B2203/54—Aspects of powerline communications not already covered by H04B3/54 and its subgroups
    • H04B2203/5462—Systems for power line communications
    • H04B2203/5483—Systems for power line communications using coupling circuits

Definitions

  • the invention relates to a driver circuit for data transmission via a transmission line to a receiver according to the preamble of claim 1.
  • Two-wire bus systems are known in which a so-called master communicates bidirectionally with two so-called slaves via a bus with two lines, the master also supplying the slaves with power via the bus.
  • the data transmission from the master to the individual slaves takes place by modulating the voltage prevailing on the two bus lines, so that the bus has alternating high-voltage phases and low-voltage phases in accordance with the data to be transmitted.
  • the voltage prevailing on the bus lines is modulated by two transistors which connect the two bus lines to a supply voltage or to ground.
  • a resistor is connected in parallel to each of the two transistors, which takes over the current previously flowing through the transistors when the transistors are blocked, the voltage drop across the resistors corresponding to the desired voltage swing on the bus lines.
  • the master has a current source which is arranged between the two bus lines and drives a cross current between the two bus lines.
  • the two transistors are controlled to be conductive, so that one bus line assumes the potential of the supply voltage, while the other bus line assumes ground potential.
  • the two transistors are controlled in a non-conductive manner in the low voltage phase. 'In this state, flows from the supply voltage across the voltage-side resistor, arranged between the two bus lines power source and the ground-side resistor, a shunt current, which determines the voltage level on the two bus lines.
  • the potential of one bus line then corresponds to the voltage drop across the voltage-side resistor, while the potential of the other bus line corresponds to the voltage drop across the ground-side resistor.
  • the cross current flowing in the low voltage phase is made up of the current driven by the current source and the load currents of the slaves connected to the bus. As a result, the current source arranged in the master has to drive more current during the low-voltage phases, the less
  • a disadvantage of the known driver circuit is the fact that the current source in the master must be able to drive a considerable cross current between the two bus lines in order to set the desired voltage swing on the bus lines even when a single slave is operating.
  • the high cross currents thus required when operating a single slave are, however, associated with a corresponding power loss, which is implemented in the two resistors and in the current source and causes thermal problems.
  • the invention is therefore based on the object of improving the known driver circuit described above ensure that even when operating a single slave, the power loss in the master is as low as possible.
  • the invention encompasses the general technical teaching of using a controllable switching element with an adjustable resistor instead of the two resistors for coupling the two bus lines during the low-voltage phase.
  • the volume resistance of this switching element is then set so that the desired voltage is established on the bus during the low voltage phases.
  • a particular advantage of the solution according to the invention is that only a relatively low power loss is required to generate the desired voltage levels during the low-voltage phase, so that no thermal problems occur.
  • a measuring device is preferably provided for detecting the current flowing via the transmission line, the measuring device on the output side with the modulation input. direction is connected to the internal resistance of the driver circuit in accordance with the above 'the transmission line current flowing set.
  • the measuring device has a sampling circuit which samples the current flowing over the transmission line with a predetermined sampling period, the sampling period preferably being equal to the data transmission rate on the transmission line.
  • the scanning circuit therefore scans the current flowing over the transmission line preferably shortly before a switch from the high voltage phase to the low voltage phase, so that the current flowing through the transmission line does not jump when switching from the high voltage phase to the low voltage phase. This is advantageous because an abrupt change in the current flowing through the transmission line is associated with undesired interference radiation.
  • the measuring device therefore preferably has a storage element, for example in the form of a capacitor, in order to temporarily store the measured value of the current flowing through the transmission line during the high voltage phase during the low voltage phase, which ensures that the current flowing through the transmission line is essentially constant during the low voltage phases remains.
  • a storage element for example in the form of a capacitor
  • a regulator is provided in order to regulate the internal resistance of the driver circuit.
  • This controller is preferably connected to the measuring device on the input side in order to regulate the internal resistance of the driver circuit as a function of the current flowing via the transmission line.
  • the controller preferably has a reference voltage element which defines the desired voltage swing for the voltage modulation in order to regulate the internal resistance of the driver circuit in such a way that the voltage modulation takes place with the predetermined voltage swing.
  • the invention is not limited to data transmission between a master and several slaves. Rather, the invention can be used wherever a transmitter sends one or more receivers data over a transmission line, the transmission line being used in addition to the data transmission also for the power supply of the receiver.
  • FIG. 1 shows a bus system with a master and several slaves
  • FIG. 2a shows a pulse diagram of the voltage on the bus lines
  • FIG. 2b shows a pulse diagram of the current through the bus lines
  • FIG. 3 shows the driver circuit of the master as a block diagram, FIGS. 4 and 5 modifications of the driver circuit from FIG. 3.
  • the bus system shown in FIG. 1 enables communication between a master 1 and several slaves 2, 3 via a bus consisting of two lines a, b, only two slaves 2, 3 being shown as examples.
  • FIG. 2a exemplarily showing a signal sequence 6 for line a and a signal sequence 7 for line b.
  • a logic zero is represented by a LOW level on line a and a HIGH level on line b.
  • a logical one is generated in that line a first assumes a HIGH level and then changes to a LOW level, whereas line b initially assumes a LOW level and then changes to a HIGH level.
  • the invention is not limited to the voltage levels mentioned above, but can also be implemented with other voltage levels. Instead of a biphasic code, other codes can also be used for data transmission.
  • the master 1 has a receiver 8 connected to the two lines a, b in order to receive data from the slaves 2, 3.
  • the data transmission from the slaves 2, 3 to the master 1 takes place here by modulating the current flowing over the lines a, b.
  • a pulse sequence 9 of the current flowing via lines a, b is shown as an example in FIG. 2b.
  • the master 1 also has a control and evaluation logic 10, which controls the two transmitters 4, 5 and the receiver 8 and evaluates the data received by the receiver 8.
  • the driver circuit shown in FIG. 3 firstly modulates the electrical voltage on line a in order to transmit data from the master to the slaves.
  • the driver circuit shown in FIG. 3 has the task of adjusting the internal resistance of the driver circuit during the low-voltage phases on lines a and b in such a way that the desired voltage level on the lines results from the electrical current flowing off via lines a and b a, b sets.
  • the electrical voltage during the high voltage phases on line a U HIGH 13 V and on line b U HIGH ⁇ 0V
  • the voltage swing on lines a and b is therefore
  • the voltage swing on lines a and b is therefore significantly less than in conventional driver circuits with a voltage swing of 5 V, which advantageously contributes to a reduction in the interference radiation.
  • the normal load current I LA ⁇ T for supplying power to the slaves not only flows on lines a and b during the high-voltage phases , as in conventional driver circuits, but also during the low-voltage phases .
  • the current swing .DELTA.l is therefore smaller than in conventional driver circuits, which, in addition to the reduced voltage swing described above, leads to a reduction in the interference radiation.
  • the driver circuit shown in FIG. 3 has a transistor Ml, the gate connection of which is connected to a signal source S2 which, depending on the information to be transmitted, makes transistor Ml either conductive or non-conductive controls.
  • Signal source S2 thus generates a HIGH level when high voltages are to be transmitted, whereas signal source S2 generates a LOW level when low voltages are to be transmitted " .
  • the drain connection of transistor Ml is via a low-resistance resistor
  • the signal source S2 is only shown schematically here and specifies the data to be transmitted from the master to the slaves.
  • the driver circuit has a transistor M2, the source connection of which is connected to the drain connection of the transistor Ml, while the drain connection of the transistor M2 is connected to the source connection of the transistor Ml and is therefore connected to the line a ,
  • the transistor M2 has the task of taking over the current flowing via the line a during the low-voltage phases in which the transistor M1 is blocking.
  • transistor Ml conducts, while transistor M2 blocks, so that the following voltage is present on line a:
  • the voltage on line a therefore essentially corresponds to the supply voltage VCC during the high voltage phases.
  • the control of the transistor M2 will be described in detail later.
  • the driver circuit When switching between the high-voltage phase and the low-voltage phase, the driver circuit ensures that the current flowing via line a does not lead to excessively high voltage changes.
  • a constant current source I REF ⁇ which is connected to ground GND, the constant current source I REFI a current of
  • the voltage is therefore at the inverting input of the differential amplifier AI
  • the voltage U_ present at the inverting input of the differential amplifier AI thus reflects the current I ⁇ IGNAL + I LAST on line a.
  • the non-inverting input 'of the differential amplifier AI is connected to the drain terminal of a transistor M3, which is connected to ground GND by its source terminal.
  • the output of the differential amplifier AI is connected to the gate terminal of the transistor M3, which causes feedback to the non-inverting input of the differential amplifier AI, as will be described below.
  • the differential amplifier AI drives the transistor M3 in such a way that the voltage difference at the inputs of the differential amplifier AI is always zero. So the following must apply:
  • the voltage drop across the resistor R3 is therefore equal to the voltage drop across the resistors R1 and R2 in the regulated state, while the drain current I DM3 through the transistor M3 is equal to the sum of the load current I LAST and the signal current I S I GNA .
  • the feedback through the differential amplifier AI therefore leads to the drain currents I DM1 and I DM3 of the transistors ⁇ > NJ M
  • the output of the differential amplifier A2 is connected to the gate connection of a transistor M5, the source connection of the transistor M5 being connected to the supply voltage VCC, while the drain connection of the transistor M5 is connected to ground GND via a further transistor M4.
  • the drain connection of the transistor M5 is connected to the non-inverting input of the differential amplifier, so that the source-drain voltage of the transistor M5 is present at the non-inverting input of the differential amplifier.
  • the feedback of the output of the differential amplifier A2 to the non-inverting input of the differential amplifier A2 has the consequence that the source-drain voltage of the transistor M5 in the steady state is equal to the desired voltage swing ⁇ U for the voltage modulation.
  • line a has the following voltage:
  • the drain connection of transistor M6 is connected to the gate connection of a transistor M4, the source connection of transistor M4 being connected to ground GND, while the drain connection of transistor M4 is connected to the drain connection of the transistor M5 is connected.
  • the gate voltage of the transistor M3 buffered in the capacitor C1 thus drives the transistor M4.
  • the drain current I DM4 through transistor M4 is therefore directly related to the drain current I DM1 through transistor Ml, which is equal to the current flowing via line a. Furthermore, the gate voltage of transistor M2 determines the drain current I DM5 of transistor M5. The buffering of the gate voltage of the transistor M4 by the capacitor C1 therefore not only prevents sudden changes in the drain current I DM4 ⁇ but also counteracts sudden changes in the current flowing through line a due to the above-mentioned functional relationship between the drain currents I DM and I DM1 .
  • Be 4 shows an alternative embodiment of the OF INVENTION ⁇ to the invention the driver circuit, which largely corresponds with the embodiment described above, so that used hereinafter the same reference numerals and reference is made to avoid repetition of the foregoing description of FIG. 3
  • the driver circuit according to FIG. 4 additionally has a transistor M9, the gate connection of which is connected to the drain connection of the transistor M ⁇ , while the source connection of the transistor M9 is connected to ground.
  • the gate connection of transistor M8 is connected to an additional voltage source Vg, the voltage of which is equal to the maximum value of the voltage supplied by signal source S2.
  • the resistor R4 connects the supply voltage VCC to the source terminal of the transistor M5.
  • FIG. 5 shows an alternative exemplary embodiment of the driver circuit according to the invention, which largely corresponds to the exemplary embodiment described above, so that the same reference numerals are used in the following and reference is made to the above description of FIG. 4 in order to avoid repetition.
  • the decisive difference between the driver circuit according to FIG. 5 and the exemplary embodiments described above is that the transistor M1 is omitted, so that the connection to the line a takes place exclusively through the transistor M2. This has the advantage that only a single power transistor is required.
  • the gate connection of the transistor M2 is connected to the output of the differential amplifier A2 via a switching element consisting of two transistors Mll, M12, the source connections of the two transistors Mll, M12 being connected together, while the two gate connections of the transistors Mll, M12 can be controlled by the signal source S2.
  • the driver circuit has two transistors M9 and MIO, the drain connection of transistor M9 being connected to the gate connection of transistor M2, while the two source connections of transistors M9, MIO are connected to one another.
  • the drain connection of the transistor MIO is finally connected to ground via a voltage source Vgl.
  • the driver circuit also has an inverter Inl, which connects the signal source S2 to the gate connections of the two transistors M9, MIO.
  • the functional specialty of the driver circuit shown in FIG. 5 is that the gate voltage of the transistor M2 is switched over. This is done by transistors Mll, M12 and by transistors M9, MIO. In the high voltage phase, transistor M2 is switched through with low resistance, whereas in the low voltage phase transistor M2 is controlled to a defined resistance R DS between the source connection and the drain connection.
  • driver circuit according to the invention described above is not limited to the components described above with regard to its circuitry implementation, since, for example, other transistor types can be used.
  • the transmitter 5 shown in FIG. 1 for line b is analogous to that above Driver circuit described is constructed so that a detailed description of the driver circuit of the transmitter 5 is unnecessary and in this regard reference is made to the above description.
  • the embodiment of the invention is also not limited to the preferred exemplary embodiments specified above. Rather, a number of variants are conceivable which make use of the solution shown, even in the case of fundamentally different types.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Dc Digital Transmission (AREA)

Abstract

L'invention concerne un circuit d'attaque pour transférer des données à un récepteur (2, 3) par l'intermédiaire d'une ligne de transmission (a, b). Ce circuit d'attaque présente un premier élément de commutation (M1) pouvant être commandé, reliant la ligne de transmission (a, b) à une tension d'alimentation (VCC) ou à la masse (GND) pour moduler la tension sur la ligne de transmission (a, b) en fonction des données à transférer. Ce circuit d'attaque présente également un premier élément de couplage (M2) qui est monté en parallèle par rapport au premier élément de commutation (M1). Ce premier élément de couplage reçoit le courant devant traverser le premier élément de commutation (M1) tant que ce dernier (M1) est bloqué. Le premier élément de couplage est constitué par un deuxième élément de commutation (M2) pouvant être commandé et comportant une résistance interne réglable pour permettre de régler la tension voulue sur la ligne de transmission (a, b), tout en limitant les pertes de puissance.
PCT/DE2000/003681 2000-10-19 2000-10-19 Circuit d'attaque WO2002033843A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/DE2000/003681 WO2002033843A1 (fr) 2000-10-19 2000-10-19 Circuit d'attaque

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/DE2000/003681 WO2002033843A1 (fr) 2000-10-19 2000-10-19 Circuit d'attaque

Publications (1)

Publication Number Publication Date
WO2002033843A1 true WO2002033843A1 (fr) 2002-04-25

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ID=5647990

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PCT/DE2000/003681 WO2002033843A1 (fr) 2000-10-19 2000-10-19 Circuit d'attaque

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014052121A1 (fr) * 2012-09-28 2014-04-03 Osram Sylvania Inc. Communication de puissance transitoire
US9065544B2 (en) 2012-09-28 2015-06-23 Osram Sylvania Inc. Pulse-based binary communication

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19725710A1 (de) * 1996-07-01 1998-01-08 Beat Larcher Verfahren und Vorrichtung zur Leistungs- und Datenübermittlung auf gemeinsamen Leitungen
DE19926095A1 (de) * 1999-06-08 2000-12-14 Siemens Ag Interface zum Ankoppeln eines Busteilnehmers an die Busleitung eines Bussystems

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19725710A1 (de) * 1996-07-01 1998-01-08 Beat Larcher Verfahren und Vorrichtung zur Leistungs- und Datenübermittlung auf gemeinsamen Leitungen
DE19926095A1 (de) * 1999-06-08 2000-12-14 Siemens Ag Interface zum Ankoppeln eines Busteilnehmers an die Busleitung eines Bussystems

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014052121A1 (fr) * 2012-09-28 2014-04-03 Osram Sylvania Inc. Communication de puissance transitoire
US9065544B2 (en) 2012-09-28 2015-06-23 Osram Sylvania Inc. Pulse-based binary communication
US9160414B2 (en) 2012-09-28 2015-10-13 Osram Sylvania Inc. Transient power communication
US9949345B2 (en) 2012-09-28 2018-04-17 Osram Sylvania Inc. Transient power communication

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