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WO2002031892A1 - Cellule solaire et procede de fabrication correspondant - Google Patents

Cellule solaire et procede de fabrication correspondant Download PDF

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Publication number
WO2002031892A1
WO2002031892A1 PCT/JP2000/008486 JP0008486W WO0231892A1 WO 2002031892 A1 WO2002031892 A1 WO 2002031892A1 JP 0008486 W JP0008486 W JP 0008486W WO 0231892 A1 WO0231892 A1 WO 0231892A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor layer
solar cell
insulating film
layer exposed
exposed region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2000/008486
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English (en)
Japanese (ja)
Inventor
Hiroyuki Ohtsuka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shin Etsu Chemical Co Ltd
Shin Etsu Handotai Co Ltd
Original Assignee
Shin Etsu Chemical Co Ltd
Shin Etsu Handotai Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shin Etsu Chemical Co Ltd, Shin Etsu Handotai Co Ltd filed Critical Shin Etsu Chemical Co Ltd
Priority to KR1020037004838A priority Critical patent/KR100790956B1/ko
Priority to JP2002535178A priority patent/JP3872428B2/ja
Publication of WO2002031892A1 publication Critical patent/WO2002031892A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/20—Electrodes
    • H10F77/206—Electrodes for devices having potential barriers
    • H10F77/211—Electrodes for devices having potential barriers for photovoltaic cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F10/00—Individual photovoltaic cells, e.g. solar cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F10/00—Individual photovoltaic cells, e.g. solar cells
    • H10F10/10—Individual photovoltaic cells, e.g. solar cells having potential barriers
    • H10F10/14—Photovoltaic cells having only PN homojunction potential barriers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/70—Surface textures, e.g. pyramid structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/70—Surface textures, e.g. pyramid structures
    • H10F77/703—Surface textures, e.g. pyramid structures of the semiconductor bodies, e.g. textured active layers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells

Definitions

  • the present invention relates to a solar cell which has relatively high photoelectric conversion efficiency and can be manufactured at low cost, and a method for manufacturing the same.
  • a solar cell is a semiconductor element that converts light energy into electric power, and includes a pn junction type, a pin type, and a Schottky type.
  • the pn junction type is most widely used.
  • solar cells When solar cells are classified based on their substrate materials, they can be broadly classified into three types: silicon crystalline solar cells, amorphous silicon solar cells, and compound semiconductor solar cells. Silicon crystalline solar cells are further classified into single crystalline solar cells and polycrystalline solar cells.
  • the compound with the highest energy conversion efficiency is a compound semiconductor solar cell, but it is extremely difficult to make a compound semiconductor as a material for the compound semiconductor solar cell, and the cost of manufacturing solar cell substrates is low. There are problems with its widespread use, and its use is limited.
  • a silicon single crystal solar cell follows, and a silicon single crystal substrate for solar cells can be manufactured relatively easily. It is the mainstay of solar cells.
  • the output characteristics of a solar cell are generally evaluated by measuring an output current-voltage curve as shown in Fig. 18 using a solar simulator. On this curve, the point Pm at which the product Ip ⁇ Vp of the output current I and the output voltage Vp is maximum is called the maximum output Pm, and the total light energy incident on the solar cell (Pm) SXI: S is the element area, I is the irradiation light Intensity) divided by:
  • Is defined as the conversion efficiency of the solar cell.
  • fill factor defined by. The closer the value of F F is to 1, the closer the output current-voltage curve becomes to an ideal square shape, and the higher the conversion efficiency ⁇ is.
  • the surface of the silicon layer must be covered with S to prevent the recombination of electrons and holes at the direct contact between the metal electrode for output extraction and the silicon layer and to increase the open-circuit voltage V oc. i 0 structure forming an insulating film such as 2 is employed (-called MIS contact or contact passivating Chillon).
  • MIS contact or contact passivating Chillon a structure forming an insulating film such as 2 is employed.
  • a small contact hole is provided in a part of the insulating film, and a metal electrode is formed here, so that the direct contact between the metal electrode acting as a recombination site and the silicon layer is reduced to a small area.
  • Limitations have been made to improve the photocurrent collection rate.
  • how to form a contact hole in the insulating film becomes a problem.
  • a method of forming a contact hole by etching a dielectric film using a photoresist or the like can be considered.
  • this method requires too much man-hour and cost to use one photolithography technology, and from the viewpoint of mass production of solar cells. Is not realistic.
  • Japanese Patent Application Laid-Open No. Hei 8-333571 proposes a method for forming a contact hole without using photolithography technology. Specifically, a pattern of a metal electrode for taking out output is formed on the insulating film by screen printing of a conductive paste, and then baked. As a result, the metal and the glass frit contained in the paste are melted by heat, break through the insulating film and reach the emitter layer, thereby forming a contact hole.
  • This method is generally referred to as fire-through, and is widely used when fabricating single-crystal or polycrystalline solar cells because of its ability to form a contact horn easily.
  • the dopant concentration of the emitter layer which is the surface n-type layer
  • the dopant concentration of the emitter layer is low, the contact resistance at the direct contact between the metal and silicon formed by the fire-through does not drop sufficiently, and the power that can be extracted is reduced due to the large contact resistance loss Because it leads to things.
  • the dopant concentration in the emitter layer is increased by diffusion, a compound of the semiconductor silicon and the dopant precipitates, and many defect levels are formed on the surface, thereby increasing the surface recombination rate. In such a state, the short-wavelength sensitivity of the solar cell is reduced, and a drawback occurs in that the current that can be extracted is reduced.
  • An object of the present invention is to provide a solar cell which can be manufactured with high conversion efficiency and low power at low cost, and a method for manufacturing the same.
  • a first configuration of a solar cell according to the present invention is a solar cell in which an uneven portion is formed on a main surface of a semiconductor substrate and the main surface is covered with an insulating film.
  • a semiconductor layer exposed region not covered with an insulating film is formed on the main surface so as to cover at least a top of at least a part of the convex portion forming the portion, and the convex portion is formed in the semiconductor layer exposed region.
  • the height of the tip at the top of the semiconductor layer is higher than the maximum height of the insulating film at the outer peripheral edge of the semiconductor layer exposed region, and is directly or at another position on the top of the ⁇ portion in the semiconductor layer exposed region. It is characterized in that an output extraction electrode is formed so as to be indirectly contacted via a conductive layer.
  • the main surface of the semiconductor substrate means at least one of both surfaces (front surface, back surface) in the thickness direction of the semiconductor substrate. Therefore, the uneven portions may be formed only on one main surface of the substrate, or may be formed on both surfaces.
  • the semiconductor layer exposed region is conceptually defined not only when the insulating film is completely removed but also when the insulating film is thick enough to allow a tunnel current to flow (about 3 nm or less). Including.
  • the unevenness is formed on the main surface of the semiconductor substrate.
  • the formation of such uneven portions has been employed in conventional silicon single crystal solar cells mainly for the purpose of preventing reflection loss.
  • the present invention not only the above-mentioned uneven portions are prevented from preventing the reflection loss, but also the specific form thereof is used as an output extraction electrode and a semiconductor. It is characterized in that it is used to form an exposed region of a semiconductor layer which is to function as a contact hole with a body layer.
  • the semiconductor layer exposed region 5 is formed so as to include the top 25 of the convex portion 15 and the height of the tip of the convex portion 15 is increased.
  • the height position is higher than the maximum height position of the insulating film 3 at the outer peripheral edge of the semiconductor layer exposed region 5. Then, the output extraction electrode 7 is formed so as to directly contact (or indirectly via the other conductive layer) the top portion 25 of the convex portion 15 in the semiconductor layer exposed region 5.
  • the semiconductor layer exposed region 5 forms a so-called bottom surface of the contact hole.
  • the semiconductor layer 2 in the exposed region 5 can never project beyond the upper edge of the surrounding insulating film 3.
  • the structure of the solar cell according to the first aspect of the present invention is crucially different from those of conventional solar cells.
  • the semiconductor layer exposed region 5 can be formed extremely simply by the method for manufacturing a solar cell of the present invention described below. That is, the method includes the steps of forming an uneven portion on a main surface of a semiconductor substrate;
  • the semiconductor layer exposed region covers the main surface of the semiconductor substrate with an insulating film including irregularities, and further covers the insulating film with an etching protective film in a region other than the top of the convex portion, and then forms a convex portion by etching. It is characterized by being formed by removing the insulating film at the top of the part.
  • the fill factor of the solar cell can be increased. Further, since the dopant concentration on the surface can be reduced, the short-wavelength sensitivity of the solar cell increases, and the short-circuit current can be improved. Thus, high conversion efficiency High-performance solar cells can be realized.
  • the current from the semiconductor layer exposed region 5 has a relatively high conductivity (that is, the resistivity). After flowing in the transparent conductive layer 6 in the lateral direction, it can be extracted from the output extraction electrode 7. Therefore, the resistance loss when current flows in the lateral direction can be greatly reduced.
  • the distance LP1 to the output extraction electrode 7 must be all lateral conduction paths in the substrate surface layer 2, but in FIG. Regardless of the presence or absence of the electrode 7, the current only needs to flow from the nearest semiconductor layer exposed region 5 to the transparent conductive layer 6, and the lateral conduction length LP 2 is the lateral conduction length of FIG. 13A. It is clear that the length is much shorter than LP 1.
  • the transparent conductive layer is formed, shadowing loss due to the transparent conductive layer itself hardly occurs. Thus, the short-circuit current and the conversion efficiency of the solar cell can be improved.
  • the solar cell according to the third configuration of the present invention on the transparent conductive layer 6, Even if the formation intervals of the provided output extraction electrodes 7, 7 are made considerably large, the series resistance does not increase so much, and as a result, the shadowing loss can be further reduced.
  • the semiconductor layer exposed region not covered with the insulating film is formed on the main surface.
  • the output extraction electrode is formed directly in contact with the semiconductor layer, while the remaining semiconductor layer exposed region where the output extraction electrode is not formed is transparent. It is characterized by being covered with an auxiliary insulating layer.
  • FIG. 4B is a process explanatory view following FIG. 4A.
  • FIG. 9C is an explanatory view following FIG. 9B.
  • FIG. 13B is an explanatory view following FIG. 13A.
  • FIG. 19B is an explanatory view following FIG. 19A.
  • the valley bottom of the projection 15 to be formed is considered. It is desirable that the maximum height from the top to the top be 0.1 ⁇ or more and 30 ⁇ or less.
  • an oxide film or a nitride film can be used for the insulating film 3.
  • the substrate 1 is a silicon single crystal substrate, and the insulating film 3 is formed by heat treatment in a predetermined atmosphere. It is configured as a silicon oxide or nitride film (which can be formed by, for example, a CVD method). Thereby, the insulating film 3 functions as a passivation film having a low surface recombination speed.
  • a coating solution is prepared using a polymer material having sufficient resistance to etching such as hydrofluoric acid, for example, a novolak resin as a resist material.
  • the viscosity of the coating solution can be adjusted using an appropriate solvent.
  • this coating liquid is applied by a known coating method, for example, a spin coating method or a spray method.
  • the coating liquid is accumulated and the coating layer 24 is formed.
  • the solvent is evaporated and dried, as shown in FIG. 8B, the coating layer 24 becomes the resist layer 4 ′, and the shape near the bottom of the concave portion 16 is partially filled.
  • the resist layer 4 ′ is stopped from being further formed, and as shown in FIG. It is used as a simple etching protection film 4.
  • the first main surface side of the substrate is immersed in an etching solution containing hydrofluoric acid or the like to dissolve the insulating film (for example, silicon oxide film) covering the protruding top portion 25 of the projection 15. ⁇ If removed, the semiconductor layer exposed region 5 is formed.
  • the etching protection film 4 is removed using an organic solvent such as acetone or MEK (methyl ethyl ketone).
  • the tops 25 of the projections 15 can be exposed from the liquid surface without excess or shortage.
  • the remaining film has a thin or porous force or an island shape as shown in FIG. 9D.
  • a state where the insulating film 3 is at least partially exposed can be reliably formed.
  • the insulating film 3 where the etching protective film 4a remains can also be removed.
  • the upper surface 11 of the inner peripheral edge of the insulating film 3 forming the outer peripheral edge of the layer exposed region 5 can be formed flat. This makes it possible to form the semiconductor layer exposed region 5 in which the remaining insulating film 3 is small and the variation in the formation area is kept low.
  • a transparent conductive layer 6, for example, can be configured as a conductive oxide film such as tin oxide (Sn0 2) or an acid Ihiinjiumu (I n 2 0 3).
  • a conductive oxide film such as tin oxide (Sn0 2) or an acid Ihiinjiumu (I n 2 0 3).
  • an antimony (Sb) -doped oxidized tin film (so-called Nesa film) or a tin (Sn) -doped oxidized indium film (so-called ITO Mo) has high conductivity.
  • the Nesa film has a high electrical conductivity and contributes particularly to the reduction of the series resistance of solar cells.
  • the ITO film has a slightly lower conductivity than the Nesa film but is inexpensive.
  • Ne support film Ya I TO film for example, C d 2 S N_ ⁇ 4, Zn 2 Sn0 4, Zn Sn_ ⁇ 3, M gln 2 0 4, C d S doped with yttrium (Y) b 2 ⁇ 6 and G a I n0 3 doped with Sn, it may be used as the material of the transparent conductive layer 6.
  • the transparent conductive layer 6 can function as an anti-reflection film by adopting a material having a different refractive index from that of the silicon single crystal constituting the substrate 1.
  • the constituent material of the transparent conductive layer 6 preferably has a refractive index of 1.5 to 2.5.
  • the refractive index is about 2.0, and when the thickness is about 40 to 70 nm, a remarkable antireflection effect can be obtained.
  • an anti-reflection film may be separately formed together with or instead of the transparent conductive layer 6.
  • the output extraction electrode 7 is formed by printing a desired electrode pattern on the transparent conductive layer 6 by using a paste containing a metal powder such as silver powder by a known thick film printing method such as screen printing. Can be formed. Also, by using a thermosetting paste, it is possible to form the output extraction electrode 7 at a lower temperature. As shown in FIG. 17, the first main surface side of the substrate 1 serves as the light receiving surface of the solar cell.Therefore, the output extraction electrode 7 is used to improve the efficiency of light incidence on the p_n junction 48. For example, it has a thick busbar electrode formed at an appropriate interval to reduce internal resistance, and a finger electrode that branches into a comb shape at a predetermined interval from the busbar electrode. However, when the electric conductivity of the transparent conductive layer 6 is sufficiently high, it is possible to omit the finger electrode or to set the interval between the finger electrodes wide even when the finger electrode is formed.
  • an uneven portion is formed on the second main surface of the substrate 1 for preventing back surface reflection, and an insulating film 3 is formed so as to cover the uneven portion.
  • the semiconductor layer exposed portion 5 is formed on the top of the convex portion 15.
  • the second main surface side is not a light receiving surface, the entire surface is covered with the output extraction electrode 8.
  • the thickness of the substrate 1 is reduced in order to reduce the weight of the solar cell, the thickness of the substrate 1 is reduced as shown in Fig. 1B to prevent recombination and disappearance of minority carriers at the electrode 8 on the second main surface side.
  • a high-concentration diffusion layer 9 having the same conductivity type as that of the substrate 1 and a higher concentration can be formed on the second main surface side (so-called BSF (oack surface rield) layer).
  • the solar cell 100 of FIG. 1 when the solar cell 100 absorbs photons having energy equal to or greater than the forbidden band width by light irradiation, electrons and holes are generated by photoexcitation in the P-type region and the n-type region, as shown in FIG. They are generated as minority carriers and diffuse toward the junction. At the junction, an internal electric field (a so-called “build-in” electric field) is generated due to the formation of the electric double layer. The electrons and holes diffused as minority carriers cause the internal electric field to The electrons are in the n-type region and the holes are
  • Each is drawn into and separated from the P-type region and becomes a majority carrier.
  • the P-type region and the n-type region are positively and negatively charged, respectively, and an electromotive force ⁇ E of the solar cell is generated between the electrodes (7, 8 in FIG. 1) provided in each part.
  • the semiconductor layer exposed region 5 serving as a contact horn can be easily formed by a simple etching without using a fire-through method. . Therefore, naturally, the dopant concentration of the semiconductor layer 2 can be set to a value smaller than 3 ⁇ 10 2 ° cm ⁇ 3 (in terms of sheet resistance: 40 ⁇ / port). Further, as shown in FIG. 13B, since the transparent conductive layer 6 is used, the current is longer in the lateral direction in the semiconductor layer 2 than in the case of FIG. 13A without the transparent electrode layer 6. There is no need to flow away.
  • the sheet resistance is about 10 to 25 ⁇ square. Can be lowered.
  • the output resistance electrode 7 provided on the transparent conductive layer 6 has a much smaller series resistance than conventional ones (2 to 3 mm), for example, even if it is doubled, so shadowing loss is greatly reduced. can do.
  • the remaining semiconductor layer exposed region 5 ′ where the output extraction electrode 7 is not formed can be covered with the auxiliary insulating layer 10.
  • the auxiliary insulating layer 10 is assumed to cover the remaining semiconductor layer exposed region 5 ′, the insulating film 3 and the output extracting electrode 7 collectively after forming the output extracting electrode 7. Is formed.
  • an inorganic insulating film such as silicon nitride or silicon oxide can be used. In this case, by appropriately adjusting the formation thickness of the auxiliary insulating layer 10, this can also function as an antireflection film. (Experimental example)
  • the solar cell shown in FIG. 1A was manufactured by the steps shown in the flowchart of FIG. First, a p-type crystalline silicon substrate 1 (boron-doped product having a resistivity of 2 ⁇ ⁇ cm (dopant concentration 7.2 ⁇ 10 15 cm— 3 )) cut out of a silicon single crystal ingot in an as-sliced state was prepared.
  • the thickness of the substrate 1 is 300 / zm.
  • the substrate 1 is sodium hydroxide aqueous solution (concentration:. 4 0 mass / 0) by chemically etching, after removal of the dust image layer by slice, hydroxyl Ihinatoriumu solution (hydroxide plus I isopropyl alcohol Ihinatoriumu concentration.
  • the open-circuit voltage of the example product 1 and the example product 2 is significantly improved. This is probably because the dopant concentration of the emitter layer was reduced, the surface recombination rate was reduced, and the area of the contact hole based on the semiconductor layer exposed region 5 could be limited.
  • the surface area of the substrate 1 used in Example Product 1 and Example Product 2 was determined by scanning electron microscope (SEM) .As a result, the total area ratio of the semiconductor layer exposed region 5 on the first main surface was approximately 1%. I confirmed that it was.
  • a solar cell 103 having the structure shown in FIG. 5 was produced as follows. First, a p-type single crystal silicon substrate 1 (a gallium-doped product having a thickness of 250 ⁇ m and a resistivity of 0.5 ⁇ ⁇ cm) prepared by the CZ method was prepared. After etching, random textured surfaces were formed on both surfaces. After texturing, a coating agent containing P 2 0 5 was coated cloth, 8 5 by thermal diffusion at 0 ° C, the sheet resistance on the surface of about 1 0 0 Omega / mouth of the n-type diffusion layer 2 was formed.
  • a p-type single crystal silicon substrate 1 a gallium-doped product having a thickness of 250 ⁇ m and a resistivity of 0.5 ⁇ ⁇ cm
  • a coating agent containing P 2 0 5 was coated cloth, 8 5 by thermal diffusion at 0 ° C, the sheet resistance on the surface of about 1 0 0 Omega / mouth of the n-type diffusion layer 2 was formed.
  • the short circuit current is reduced in the example product 3 as compared with the example products 1 and 2 described above, while the open circuit voltage is increased. It is considered that the reason why the short-circuit current decreased was that the electrode width and electrode pitch were not different from those of the conventional method. That is, the shadowing area was increased as compared with the products of Examples 1 and 2 shown in Table 1. On the other hand, the reason why the open-circuit voltage increased was thought to be that the substrate resistivity was reduced from 2.0 ⁇ ⁇ 111 to 0.5 ⁇ ⁇ cm. In general, lowering the substrate resistivity decreases the reverse saturation current density and increases the open-circuit voltage.
  • the solar cell 104 shown in FIG. 6 was manufactured as follows (note that in FIG. 6, in order to avoid complication, only the portion near the surface is shown without drawing the uneven portions and the antireflection film). T). First, a p-type single-crystal silicon substrate 1 (boron-doped product having a thickness of 250 m and a resistivity of 2 ⁇ ⁇ cm) prepared by the CZ method was prepared. Square rib-shaped protrusions 45, 45 were formed at intervals of 2 mm (the area between the protrusions 45, 45 can be regarded as a recess). At this time, the height from the first main surface of the substrate 1 to the top of each of the projections 45, 45 was set to about 30 ⁇ .
  • the substrate 1 was immersed in a 10% by mass aqueous hydrofluoric acid solution to form a semiconductor layer exposed portion 5 on the tops 25 of the projections 45, 45. Then, after the resist was washed away using a solvent, the pattern of the output electrode 7 shown in FIG. 6 was formed on the first main surface using silver paste by screen printing, and the aluminum was printed on the second main surface. The pattern of the output electrode 8 was formed on the entire surface using the paste. At this time, it is necessary to align the output extraction electrode 7 on the first main surface side so as to be printed so as to overlap the semiconductor layer exposed portion 5 on the tops of the projections 45, 45.
  • the width of the electrode 7 is about 10 times the width of the semiconductor layer exposed portion 5 with respect to the width, the positioning can be performed relatively roughly. Subsequently, as the anti-reflection film T I_ ⁇ 2 film was formed to a thickness of a (not shown) 6 0 nm by normal pressure CVD, thereby completing the solar cell 1 0 4 (Example Product 4) .
  • Example product 4 was evaluated in the same manner as in Experimental example 1. Open circuit voltage 0.667 V, short-circuit current density 36.9 mA / cm 2 , fill factor 0.770, conversion efficiency 19.0% was obtained, and the characteristics were improved compared to the conventional screen printing fire-through method.

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  • Photovoltaic Devices (AREA)

Abstract

Une cellule solaire comprend un substrat semi-conducteur (1) pourvu d'irrégularités sur sa surface principale recouverte d'une couche isolante (3) telle qu'elle recouvre quelques unes des projections d'irrégularités, à savoir, des zones non recouvertes (5) formées sur la surface principale. Une électrode de sortie (7) est connectée directement ou par le biais d'une couche conductrice aux parties supérieures (25) des projections (15) dans les zones semi-conductrices exposées (5). On forme ces zones (5) en appliquant un film isolant (3) de manière à recouvrir des projections (15) sur la surface principale du substrat semi-conducteur (1), en appliquant un masque de gravure (4) pour recouvrir le film isolant (3) dans les zones ne comprenant pas les pics (25) des projections (15), et en attaquant le film isolant (3) pour exposer lesdits pics (25).
PCT/JP2000/008486 2000-10-06 2000-11-30 Cellule solaire et procede de fabrication correspondant Ceased WO2002031892A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1020037004838A KR100790956B1 (ko) 2000-10-06 2000-11-30 태양전지 및 그 제조방법
JP2002535178A JP3872428B2 (ja) 2000-10-06 2000-11-30 太陽電池の製造方法

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Application Number Priority Date Filing Date Title
JP2000308516 2000-10-06
JP2000/308516 2000-10-06

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WO2002031892A1 true WO2002031892A1 (fr) 2002-04-18

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JP (1) JP3872428B2 (fr)
KR (1) KR100790956B1 (fr)
CN (1) CN1284248C (fr)
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WO (1) WO2002031892A1 (fr)

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WO2008041489A1 (fr) * 2006-09-29 2008-04-10 Sanyo Electric Co., Ltd. Module de pile solaire
JP2009021541A (ja) * 2007-07-13 2009-01-29 Samsung Sdi Co Ltd 太陽電池及びその製造方法
JP2010519732A (ja) * 2007-02-15 2010-06-03 マサチューセッツ インスティテュート オブ テクノロジー 凹凸化された表面を備えた太陽電池
WO2011161813A1 (fr) * 2010-06-25 2011-12-29 三菱電機株式会社 Cellule solaire et son procédé de fabrication
JP2013511838A (ja) * 2009-11-18 2013-04-04 ソーラー ウィンド テクノロジーズ， インコーポレイテッド 光起電力セルの製造方法、それによって製造された光起電力セル、およびその用途
JP2013524514A (ja) * 2010-03-26 2013-06-17 テトラサン インコーポレイテッド 高効率結晶太陽電池における遮蔽された電気接点およびパッシベーション化誘電体層を通じたドーピング、ならびにその構造および製造方法
JP2014512673A (ja) * 2011-03-08 2014-05-22 アライアンス フォー サステイナブル エナジー リミテッド ライアビリティ カンパニー 向上された青色感度を有する効率的なブラックシリコン光起電装置
JP5830147B1 (ja) * 2014-09-04 2015-12-09 信越化学工業株式会社 太陽電池及び太陽電池の製造方法
JP2017135210A (ja) * 2016-01-26 2017-08-03 三菱電機株式会社 太陽電池および太陽電池の製造方法
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CN1284248C (zh) 2006-11-08
JP3872428B2 (ja) 2007-01-24
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KR100790956B1 (ko) 2008-01-03
JPWO2002031892A1 (ja) 2004-02-26
TW480737B (en) 2002-03-21

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