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WO2002006929A3 - Controlling access to multiple isolated memories in an isolated execution environment - Google Patents

Controlling access to multiple isolated memories in an isolated execution environment Download PDF

Info

Publication number
WO2002006929A3
WO2002006929A3 PCT/US2001/022027 US0122027W WO0206929A3 WO 2002006929 A3 WO2002006929 A3 WO 2002006929A3 US 0122027 W US0122027 W US 0122027W WO 0206929 A3 WO0206929 A3 WO 0206929A3
Authority
WO
WIPO (PCT)
Prior art keywords
isolated
memories
execution environment
controlling access
multiple isolated
Prior art date
Application number
PCT/US2001/022027
Other versions
WO2002006929A2 (en
Inventor
Roger Golliver
James Ii Sutton
Derrick Lin
Shreekant Thakkar
Gilbert Neiger
Francis Mckeen
Howard Herbert
Kenneth Reneris
Carl Ellison
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/618,738 external-priority patent/US6678825B1/en
Application filed by Intel Corp filed Critical Intel Corp
Priority to JP2002512776A priority Critical patent/JP3982687B2/en
Priority to AU2001271996A priority patent/AU2001271996A1/en
Priority to DE10196440T priority patent/DE10196440B4/en
Priority to HK03104417.4A priority patent/HK1052237B/en
Priority to GB0303644A priority patent/GB2381626B/en
Publication of WO2002006929A2 publication Critical patent/WO2002006929A2/en
Publication of WO2002006929A3 publication Critical patent/WO2002006929A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory
    • G06F12/1458—Protection against unauthorised use of memory or access to memory by checking the subject access rights
    • G06F12/1466—Key-lock mechanism
    • G06F12/1475—Key-lock mechanism in a virtual system, e.g. with translation means

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Storage Device Security (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
PCT/US2001/022027 2000-07-18 2001-07-13 Controlling access to multiple isolated memories in an isolated execution environment WO2002006929A2 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2002512776A JP3982687B2 (en) 2000-07-18 2001-07-13 Controlling access to multiple isolated memories in an isolated execution environment
AU2001271996A AU2001271996A1 (en) 2000-07-18 2001-07-13 Controlling access to multiple isolated memories in an isolated execution environment
DE10196440T DE10196440B4 (en) 2000-07-18 2001-07-13 Control access to multiple isolated storage in an isolated execution environment
HK03104417.4A HK1052237B (en) 2000-07-18 2001-07-13 Controlling access to multiple isolated memories in an isolated execution environment
GB0303644A GB2381626B (en) 2000-07-18 2001-07-13 Controlling access to multiple isolated memories in an isolated execution environment

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/618,738 2000-07-18
US09/618,738 US6678825B1 (en) 2000-03-31 2000-07-18 Controlling access to multiple isolated memories in an isolated execution environment

Publications (2)

Publication Number Publication Date
WO2002006929A2 WO2002006929A2 (en) 2002-01-24
WO2002006929A3 true WO2002006929A3 (en) 2002-04-25

Family

ID=24478929

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/022027 WO2002006929A2 (en) 2000-07-18 2001-07-13 Controlling access to multiple isolated memories in an isolated execution environment

Country Status (8)

Country Link
JP (1) JP3982687B2 (en)
CN (1) CN1252597C (en)
AU (1) AU2001271996A1 (en)
DE (1) DE10196440B4 (en)
GB (1) GB2381626B (en)
HK (1) HK1052237B (en)
TW (1) TW526416B (en)
WO (1) WO2002006929A2 (en)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2378005A (en) * 2001-07-27 2003-01-29 Chien-Tzu Hou Method for Controlling Paged Memory Access Attributes
US7571318B2 (en) * 2002-03-27 2009-08-04 Advanced Micro Devices, Inc. Method and apparatus for improved security in a data processor
US7325115B2 (en) * 2003-11-25 2008-01-29 Microsoft Corporation Encryption of system paging file
EP1544820B1 (en) * 2003-12-11 2013-07-31 Atos Worldline S.A. Electronic data processing device
US7590867B2 (en) 2004-06-24 2009-09-15 Intel Corporation Method and apparatus for providing secure virtualization of a trusted platform module
KR100917290B1 (en) * 2004-06-24 2009-09-11 인텔 코오퍼레이션 Method and apparatus for secure virtualization of trust platform module
US7636442B2 (en) 2005-05-13 2009-12-22 Intel Corporation Method and apparatus for migrating software-based security coprocessors
US8074262B2 (en) 2005-05-13 2011-12-06 Intel Corporation Method and apparatus for migrating virtual trusted platform modules
US7571312B2 (en) 2005-05-13 2009-08-04 Intel Corporation Methods and apparatus for generating endorsement credentials for software-based security coprocessors
US7587595B2 (en) 2005-05-13 2009-09-08 Intel Corporation Method and apparatus for providing software-based security coprocessors
US7613921B2 (en) 2005-05-13 2009-11-03 Intel Corporation Method and apparatus for remotely provisioning software-based security coprocessors
US8108668B2 (en) 2006-06-26 2012-01-31 Intel Corporation Associating a multi-context trusted platform module with distributed platforms
US7477535B2 (en) * 2006-10-05 2009-01-13 Nokia Corporation 3D chip arrangement including memory manager
US9280659B2 (en) 2006-12-29 2016-03-08 Intel Corporation Methods and apparatus for remeasuring a virtual machine monitor
US8060876B2 (en) 2007-08-10 2011-11-15 Intel Corporation Methods and apparatus for creating an isolated partition for a virtual trusted platform module
US8064605B2 (en) 2007-09-27 2011-11-22 Intel Corporation Methods and apparatus for providing upgradeable key bindings for trusted platform modules
US8249257B2 (en) 2007-09-28 2012-08-21 Intel Corporation Virtual TPM keys rooted in a hardware TPM
US8584229B2 (en) 2007-12-21 2013-11-12 Intel Corporation Methods and apparatus supporting access to physical and virtual trusted platform modules
US8307180B2 (en) * 2008-02-28 2012-11-06 Nokia Corporation Extended utilization area for a memory device
CN103209212B (en) * 2013-03-22 2015-09-16 烽火通信科技股份有限公司 Based on the data cache method in the Web network management client of RIA and system
US9710622B2 (en) * 2015-02-23 2017-07-18 Intel Corporation Instructions and logic to fork processes of secure enclaves and establish child enclaves in a secure enclave page cache
CN106528453B (en) * 2015-09-10 2019-10-18 中国航空工业第六一八研究所 Device and method for page table partition management based on composite scale page

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5075842A (en) * 1989-12-22 1991-12-24 Intel Corporation Disabling tag bit recognition and allowing privileged operations to occur in an object-oriented memory protection mechanism
EP0600112A1 (en) * 1992-11-30 1994-06-08 Siemens Nixdorf Informationssysteme Aktiengesellschaft Data processing system with virtual memory addressing and memory access controlled by keys
WO1999009482A1 (en) * 1997-08-19 1999-02-25 Siemens Nixdorf Informationssysteme Ag Process for improving the controllability of data processing equipment with address translation
WO2001075595A2 (en) * 2000-03-31 2001-10-11 Intel Corporation Controlling accesses to isolated memory using a memory controller for isolated execution
WO2001075565A2 (en) * 2000-03-31 2001-10-11 Intel Corporation Isolated instructions for isolated execution

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5469556A (en) * 1989-12-12 1995-11-21 Harris Corporation Resource access security system for controlling access to resources of a data processing system
US6542919B1 (en) * 1996-03-22 2003-04-01 Koninklijke Philips Electronics N.V. Operating system for use with protection domains in a single address space

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5075842A (en) * 1989-12-22 1991-12-24 Intel Corporation Disabling tag bit recognition and allowing privileged operations to occur in an object-oriented memory protection mechanism
EP0600112A1 (en) * 1992-11-30 1994-06-08 Siemens Nixdorf Informationssysteme Aktiengesellschaft Data processing system with virtual memory addressing and memory access controlled by keys
WO1999009482A1 (en) * 1997-08-19 1999-02-25 Siemens Nixdorf Informationssysteme Ag Process for improving the controllability of data processing equipment with address translation
WO2001075595A2 (en) * 2000-03-31 2001-10-11 Intel Corporation Controlling accesses to isolated memory using a memory controller for isolated execution
WO2001075565A2 (en) * 2000-03-31 2001-10-11 Intel Corporation Isolated instructions for isolated execution

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
J HEINRICH: "MIPS R4000 Microprocessor User's Manual", 1 April 1993, MIPS, MT.VIEW, XP002184449 *

Also Published As

Publication number Publication date
JP3982687B2 (en) 2007-09-26
TW526416B (en) 2003-04-01
DE10196440B4 (en) 2006-03-23
GB0303644D0 (en) 2003-03-19
GB2381626A (en) 2003-05-07
WO2002006929A2 (en) 2002-01-24
CN1252597C (en) 2006-04-19
JP2004504663A (en) 2004-02-12
AU2001271996A1 (en) 2002-01-30
CN1459059A (en) 2003-11-26
GB2381626B (en) 2005-02-09
HK1052237B (en) 2005-06-03
DE10196440T5 (en) 2004-04-29
HK1052237A1 (en) 2003-09-05

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