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WO2002005431A1 - Synthétiseur de fréquences - Google Patents

Synthétiseur de fréquences Download PDF

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Publication number
WO2002005431A1
WO2002005431A1 PCT/US2001/012379 US0112379W WO0205431A1 WO 2002005431 A1 WO2002005431 A1 WO 2002005431A1 US 0112379 W US0112379 W US 0112379W WO 0205431 A1 WO0205431 A1 WO 0205431A1
Authority
WO
WIPO (PCT)
Prior art keywords
circuit
phase
frequency
frequency synthesizer
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2001/012379
Other languages
English (en)
Inventor
Ting-Kuang Chiang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ciena Corp
Original Assignee
Ciena Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ciena Corp filed Critical Ciena Corp
Priority to CA002378338A priority Critical patent/CA2378338A1/fr
Priority to EP01927073A priority patent/EP1301992A1/fr
Publication of WO2002005431A1 publication Critical patent/WO2002005431A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/1806—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop the frequency divider comprising a phase accumulator generating the frequency divided signal
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/02—Digital function generators
    • G06F1/025—Digital function generators for functions having two-valued amplitude, e.g. Walsh functions

Definitions

  • This invention relates generally to the field of frequency synthesizers, and more
  • Phase locked loops have been used to generate a clock pulse based on an input
  • the output clock pulse has a frequency which is a multiple of the input signal frequency.
  • the reference signal is divided by a conventional divider circuit and supplied to the PLL.
  • the divider circuit often divides the reference signal by an
  • M the output clock frequency has less granularity and cannot be finely
  • Phase accumulators have been used in alternative frequency synthesizer circuits.
  • synthesizer that includes, PA, discrete digital synthesizer, and a look-up table.
  • a simplified frequency synthesizer is needed that allows for a finely tuned frequency output with
  • the present invention provides a simplified frequency synthesizer circuit that uses the most significant bit output from a phase accumulator for input to a phase locked loop or bandwidth filter to generate a square wave having a precisely tuned frequency.
  • a frequency synthesizer consistent with the present invention includes a phase
  • Another frequency synthesizer consistent with the present invention includes a phase
  • phase locked loop for removing jitter from a signal processed by the phase
  • Another frequency synthesizer consistent with the present invention includes a phase
  • Fig. 1 is a block diagram of a frequency synthesizer according to the present invention
  • Fig. 2 is a circuit diagram of a frequency synthesizer as shown in Fig. 1 ;
  • Fig. 3 is a block diagram of a frequency synthesizer according to the present invention including a bandpass filter. IV. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • a synthesizer circuit generates a square wave for use as a clock signal, for example, based on the most significant bit (MSB) output from a
  • phase accumulator circuit phase accumulator circuit.
  • the MSB output however, often has jitter (a time varying phase fluctuation), which can be eliminated with a jitter adjustment circuit, such as a PLL or narrow
  • An MSB selector circuit is used to select and supply the MSB to the jitter
  • Fig. 1 is a block diagram of the present invention including a phase locked loop (PLL) 160 as the jitter adjusting circuit. As shown, a phase accumulator section (PAS) 100
  • PLL phase locked loop
  • PAS phase accumulator section
  • MSB selector 150 generates a signal that is output to a most significant bit (MSB) selector 150.
  • MSB 150 may be a bus or other connection coupling the MSB of PAS 100 with PLL
  • Fig. 2 is a more detailed circuit diagram of the system in Fig. 1 showing the frequency
  • synthesizer of the present invention including a phase accumulator section and a phase locked
  • reference clock f r 140 causes register 130 (including a DQ flip-flop, for example) to latch the value of adder circuit 120, which adds an N-byte (N being an
  • each reference clock period causes the phase value output from register 130 to increase linearly, creating a phase ramp.
  • accumulator value is determined by X. The output of register 130 will increase until a
  • phase value output will rollover to a minimum
  • An MSB selector circuit such as a bus or other connection, is coupled to an MSB selector circuit
  • PA 100 and resulting signal 135 typically cannot be used alone as a digital synthesizer
  • PLL 160 can be provided to reduce jitter and generate a stable output.
  • PLL 160 includes an
  • optional frequency divider circuit 162 a phase detector circuit 164, filter circuit 166, voltage
  • VCO control oscillator
  • signal divider circuit 162 and loop divider circuit 170 advantageously
  • MSB 155 is input to signal divider 162 which divides the frequency of signal 155 by
  • Phase detector 164 compares the output from divider 162 and a feed back
  • Filter 166 typically includes a low pass filter circuit that filters the signal output by the phase detector 164. In particular, filter 166 typically has a cutoff frequency lower than
  • VCO 168 is input to VCO 168, which then outputs a square wave signal 175 having frequency/,
  • PLL 160 outputs a stable square wave 175, which is also fed back to phase detector
  • granularity of output 175 is determined, at least in part, by phase increment X 110. Moreover, by appropriately choosing K, X and M, the frequency output from the PLL can
  • Fig. 3 illustrates an alternative embodiment of the present invention similar to Fig. 1.
  • bandpass filter circuit 300 advantageously has a relatively narrow bandwidth of about 1 kHz to thereby significantly reduce jitter.
  • the MSB is supplied via selector 150 to bandpass filter circuit 300 instead of PLL 160.
  • Bandpass filter circuit 300 advantageously has a relatively narrow bandwidth of about 1 kHz to thereby significantly reduce jitter.
  • the embodiment shown in Fig. 3 the
  • PA and PLL circuits may be used.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

L'invention concerne un synthétiseur de fréquences comprenant un accumulateur de phase (200), un sélecteur du bit (250) le plus important et un circuit de réglage de gigue (260). Le sélecteur du bit le plus important transmet à un circuit de réglage de gigue le bit le plus important de la sortie de l'accumulateur de phase avant d'émettre une onde carrée. Le circuit de réglage de gigue peut, par exemple, être une boucle à phase asservie ou un filtre passe-bande.
PCT/US2001/012379 2000-07-10 2001-04-17 Synthétiseur de fréquences Ceased WO2002005431A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CA002378338A CA2378338A1 (fr) 2000-07-10 2001-04-17 Synthetiseur de frequences
EP01927073A EP1301992A1 (fr) 2000-07-10 2001-04-17 Synthetiseur de frequence

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US61268900A 2000-07-10 2000-07-10
US09/612,689 2000-07-10

Publications (1)

Publication Number Publication Date
WO2002005431A1 true WO2002005431A1 (fr) 2002-01-17

Family

ID=24454236

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/012379 Ceased WO2002005431A1 (fr) 2000-07-10 2001-04-17 Synthétiseur de fréquences

Country Status (3)

Country Link
EP (1) EP1301992A1 (fr)
CA (1) CA2378338A1 (fr)
WO (1) WO2002005431A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2399241A (en) * 2003-03-06 2004-09-08 Ifr Ltd Waveform generation
CN103873052A (zh) * 2012-12-12 2014-06-18 普诚科技股份有限公司 数值控制振荡器以及数字锁相回路

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0630129A2 (fr) * 1993-06-09 1994-12-21 Alcatel SEL Aktiengesellschaft Méthode de génération d'un signal d'horloge synchronisé avec un circuit d'oscillateur réglable
US5651035A (en) * 1995-04-28 1997-07-22 International Microcircuits, Inc. Apparatus for reducing jitter of a spectrum spread clock signal and method therefor
US5656976A (en) * 1994-11-26 1997-08-12 Electronics And Telecommunications Research Institute Hybrid frequency synthesizer
DE19653022A1 (de) * 1996-12-19 1998-06-25 Bosch Gmbh Robert Frequenzsynthesizer
US5790614A (en) * 1993-06-09 1998-08-04 Alcatel Network Systems, Inc. Synchronized clock using a non-pullable reference oscillator

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0630129A2 (fr) * 1993-06-09 1994-12-21 Alcatel SEL Aktiengesellschaft Méthode de génération d'un signal d'horloge synchronisé avec un circuit d'oscillateur réglable
US5790614A (en) * 1993-06-09 1998-08-04 Alcatel Network Systems, Inc. Synchronized clock using a non-pullable reference oscillator
US5656976A (en) * 1994-11-26 1997-08-12 Electronics And Telecommunications Research Institute Hybrid frequency synthesizer
US5651035A (en) * 1995-04-28 1997-07-22 International Microcircuits, Inc. Apparatus for reducing jitter of a spectrum spread clock signal and method therefor
DE19653022A1 (de) * 1996-12-19 1998-06-25 Bosch Gmbh Robert Frequenzsynthesizer

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2399241A (en) * 2003-03-06 2004-09-08 Ifr Ltd Waveform generation
GB2399241B (en) * 2003-03-06 2006-04-12 Ifr Ltd Improved waveform generation
CN103873052A (zh) * 2012-12-12 2014-06-18 普诚科技股份有限公司 数值控制振荡器以及数字锁相回路

Also Published As

Publication number Publication date
CA2378338A1 (fr) 2002-01-17
EP1301992A1 (fr) 2003-04-16

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