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WO2002003266A3 - Procede de conception et d'implantation de circuits integres - Google Patents

Procede de conception et d'implantation de circuits integres Download PDF

Info

Publication number
WO2002003266A3
WO2002003266A3 PCT/US2001/021162 US0121162W WO0203266A3 WO 2002003266 A3 WO2002003266 A3 WO 2002003266A3 US 0121162 W US0121162 W US 0121162W WO 0203266 A3 WO0203266 A3 WO 0203266A3
Authority
WO
WIPO (PCT)
Prior art keywords
design
layout
parasitic
blocks
extractions
Prior art date
Application number
PCT/US2001/021162
Other languages
English (en)
Other versions
WO2002003266A2 (fr
Inventor
Gerd Frankowsky
Original Assignee
Infineon Technologies Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Corp filed Critical Infineon Technologies Corp
Priority to EP01952407A priority Critical patent/EP1307835A2/fr
Publication of WO2002003266A2 publication Critical patent/WO2002003266A2/fr
Publication of WO2002003266A3 publication Critical patent/WO2002003266A3/fr

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

Procédé servant à améliorer la conception, l'implantation et la capacité d'un circuit intégré à très grande échelle (VLSI) possédant une pluralité de blocs et comportant des éléments parasites, ce qui consiste initialement à concevoir chacun des blocs de façon séparée et parallèle, à simuler chaque conception de bloc et à extraire des éléments parasites identifiés dans chaque bloc, puis à mémoriser les informations obtenues dans une base de données commune à la totalité des blocs. Ce procédé consiste, de plus, à reporter la notation des extractions parasites sur une base continue pour chacun des blocs afin de tirer avantage de la conception initiale, de la simulation et des étapes suivantes, à élaborer une implantation comportant des extractions parasites pour chaque conception de bloc après la simulation réussie de ce dernier, à réaliser une implantation totale de puce avec extraction parasite et à simuler au moyen de l'annotation des éléments parasites, l'implantation totale de la puce afin d'en optimiser la conception.
PCT/US2001/021162 2000-06-30 2001-07-02 Procede de conception et d'implantation de circuits integres WO2002003266A2 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP01952407A EP1307835A2 (fr) 2000-06-30 2001-07-02 Procede de conception et d'implantation de circuits integres

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US60854200A 2000-06-30 2000-06-30
US09/608,542 2000-06-30

Publications (2)

Publication Number Publication Date
WO2002003266A2 WO2002003266A2 (fr) 2002-01-10
WO2002003266A3 true WO2002003266A3 (fr) 2003-02-27

Family

ID=24436957

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/021162 WO2002003266A2 (fr) 2000-06-30 2001-07-02 Procede de conception et d'implantation de circuits integres

Country Status (3)

Country Link
EP (1) EP1307835A2 (fr)
TW (1) TW518488B (fr)
WO (1) WO2002003266A2 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7137088B2 (en) 2004-05-04 2006-11-14 Hewlett-Packard Development Company, L.P. System and method for determining signal coupling coefficients for lines
US8001514B2 (en) * 2008-04-23 2011-08-16 Synopsys, Inc. Method and apparatus for computing a detailed routability estimation

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5629860A (en) * 1994-05-16 1997-05-13 Motorola, Inc. Method for determining timing delays associated with placement and routing of an integrated circuit
WO2000019343A2 (fr) * 1998-09-30 2000-04-06 Cadence Design Systems, Inc. Methodologie de construction fondee sur des blocs

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5629860A (en) * 1994-05-16 1997-05-13 Motorola, Inc. Method for determining timing delays associated with placement and routing of an integrated circuit
WO2000019343A2 (fr) * 1998-09-30 2000-04-06 Cadence Design Systems, Inc. Methodologie de construction fondee sur des blocs

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
HSIAO-PIN SU ET AL: "A timing-driven soft-macro resynthesis method in interaction with chip floorplanning", DESIGN AUTOMATION CONFERENCE, 1999. PROCEEDINGS. 36TH NEW ORLEANS, LA, USA 21-25 JUNE 1999, PISCATAWAY, NJ, USA,IEEE, US, 21 June 1999 (1999-06-21), pages 262 - 267, XP010344072, ISBN: 1-58113-092-9 *
XIAO SUN: "An integrated open CAD system for DSP design with embedded memory", MEMORY TECHNOLOGY, DESIGN AND TESTING, 1998. PROCEEDINGS. INTERNATIONAL WORKSHOP ON SAN JOSE, CA, USA 24-25 AUG. 1998, LOS ALAMITOS, CA, USA,IEEE COMPUT. SOC, US, 24 August 1998 (1998-08-24), pages 4 - 9, XP010296524, ISBN: 0-8186-8494-1 *

Also Published As

Publication number Publication date
TW518488B (en) 2003-01-21
WO2002003266A2 (fr) 2002-01-10
EP1307835A2 (fr) 2003-05-07

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