[go: up one dir, main page]

WO2002001641A1 - Dispositif semi-conducteur - Google Patents

Dispositif semi-conducteur Download PDF

Info

Publication number
WO2002001641A1
WO2002001641A1 PCT/JP2001/005535 JP0105535W WO0201641A1 WO 2002001641 A1 WO2002001641 A1 WO 2002001641A1 JP 0105535 W JP0105535 W JP 0105535W WO 0201641 A1 WO0201641 A1 WO 0201641A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
active region
semiconductor layer
semiconductor device
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2001/005535
Other languages
English (en)
Japanese (ja)
Inventor
Toshiya Yokogawa
Kunimasa Takahashi
Makoto Kitabatake
Osamu Kusumoto
Takeshi Uenoyama
Koji Miyazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to EP01943848A priority Critical patent/EP1231640A4/fr
Priority to US10/069,654 priority patent/US6674131B2/en
Publication of WO2002001641A1 publication Critical patent/WO2002001641A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/035—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon carbide [SiC] technology
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/637—Lateral IGFETs having no inversion channels, e.g. buried channel lateral IGFETs, normally-on lateral IGFETs or depletion-mode lateral IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/80—FETs having rectifying junction gate electrodes
    • H10D30/87—FETs having Schottky gate electrodes, e.g. metal-semiconductor FETs [MESFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/213—Channel regions of field-effect devices
    • H10D62/221—Channel regions of field-effect devices of FETs
    • H10D62/228—Channel regions of field-effect devices of FETs having delta-doped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/213—Channel regions of field-effect devices
    • H10D62/221—Channel regions of field-effect devices of FETs
    • H10D62/235—Channel regions of field-effect devices of FETs of IGFETs
    • H10D62/314—Channel regions of field-effect devices of FETs of IGFETs having vertical doping variations 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/60—Impurity distributions or concentrations
    • H10D62/605—Planar doped, e.g. atomic-plane doped or delta-doped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/81—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation
    • H10D62/815—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation of structures having periodic or quasi-periodic potential variation, e.g. superlattices or multiple quantum wells [MQW]
    • H10D62/8171—Doping structures, e.g. doping superlattices or nipi superlattices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/60—Schottky-barrier diodes 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/05—Manufacture or treatment characterised by using material-based technologies using Group III-V technology
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/811—Combinations of field-effect devices and one or more diodes, capacitors or resistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00—Three-dimensional [3D] integrated devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325—Silicon carbide
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/931—Silicon carbide semiconductor
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/957—Making metal-insulator-metal device

Definitions

  • the present invention relates to a semiconductor power device suitable for high power consumption type devices such as lighting devices and air conditioners and used for high withstand voltage and high current under high temperature.
  • Silicon carbide is a semiconductor with a larger band gap than silicon (Si), so it has a high dielectric strength and is stable even at high temperatures. Therefore, the application of semiconductor devices formed by using the SiC substrate to next-generation power devices and high-temperature operating devices is expected.
  • a power device is a general term for a device that performs conversion and control of large power, and is called a power diode, a power transistor, or the like.
  • Applications of power devices include, for example, transistors, diodes, etc., which are placed in the inverter control unit in devices such as vacuum cleaners, washing machines, refrigerators, fluorescent lights, and air conditioners. The field of application is expected to expand further.
  • a plurality of semiconductor chips are connected by wiring according to the application and purpose, and are housed in one package to form a module.
  • wiring is formed on a substrate to form a circuit according to the application, and by attaching each semiconductor chip on the substrate, a desired circuit is formed by the semiconductor chip and the wiring. is there.
  • an inverter circuit of a fluorescent lamp using a Schottky diode and a MOS field-effect transistor will be described.
  • FIG. 18 is a cross-sectional view showing the structure of a conventional bulb-type fluorescent lamp device 250 disclosed in PCT application JP 00/0254.
  • the fluorescent lamp device 250 turns on a fluorescent lamp 201 and a fluorescent lamp 201 which are formed by connecting three substantially U-shaped arc tubes by a bridge.
  • Lighting circuit 202 including elements, cover 203 for housing lighting circuit 202, base 204 attached to the tip of cover 203, and globe 2005 surrounding fluorescent lamp 201
  • cover 203 for housing lighting circuit 202
  • base 204 attached to the tip of cover 203
  • globe 2005 surrounding fluorescent lamp 201
  • FIG. 18 is a cross-sectional view showing the structure of a conventional bulb-type fluorescent lamp device 250 disclosed in PCT application JP 00/0254.
  • the fluorescent lamp device 250 turns on a fluorescent lamp 201 and a fluorescent lamp 201 which are formed by connecting three substantially U-shaped arc tubes by a bridge.
  • Lighting circuit 202 including elements, cover 203 for housing lighting circuit 202, base 204 attached to
  • FIG. 19 is an electric circuit diagram showing the configuration of the lighting circuit 202 in the fluorescent lamp device 250.
  • the lighting circuit 202 includes a line filter circuit 212, a rectifier circuit 211, a power supply smoothing capacitor 214, an inverter circuit 211, and a choke coil. 207 and a resonance capacitor 216 are arranged.
  • the inverter circuit 215 includes an inverter driver IC 217, FETs 208 and 209 that are switching elements driven by the inverter driver IC 217, and an inverter driver IC 217. And a capacitor 2 18.
  • the fluorescent lamp 201 is arranged in parallel with the resonance capacitor 2 16 and emits fluorescent light by flowing a discharge current between the electrodes 22 1 and 22 2 at both ends of the fluorescent lamp 201. Configuration.
  • the surface 206a of the circuit board 206 has a line-fill circuit 211, a power supply smoothing circuit.
  • IC for driving overnight and FETs 208 and 209 are arranged.
  • components with relatively low heat resistance, such as the rectifier circuit 2 13 and the FIM 210, 209 in the circuit driver circuit 215 are the heat-generating chokes. It is arranged on a different surface from the coil 207 and so on and away from it.
  • the FETs 208 and 2 disposed in the simulated circuit 2 15 As 09 power transistors pMOSFETT and nMOSFETT are used.
  • a power diode is used as a diode disposed in the rectifier circuit 2 13.
  • the basic function of the power device including the power transistor and the power diode is an AC-DC-AC converter for converting 50 / 60 ⁇ to, for example, 50 k ⁇ z.
  • powered Power devices provided on a SiC substrate such as those described above are often employed as power transistors or power diodes.
  • the conventional fluorescent lamp device has the following disadvantages.
  • solder or the like is used to attach a transistor or a diode to a substrate.
  • this solder has no durability at high temperatures, it cannot be placed, for example, near a fluorescent lamp that generates a large amount of heat, and the size of the entire fluorescent lamp system increases.
  • the lighting circuit 202 is formed by mounting individual components on the circuit board 206 and connecting them to each other by wiring. Therefore, there are severe positional restrictions. As a result, the lighting circuit 202 itself has to be large, although the positional relationship of each component is devised in various ways.
  • the high heat resistance of the SiC substrate is used.
  • the conventional power-transistor power-supply diode provided on the SiC substrate is a discrete device, it is difficult to avoid the lighting circuit 202 from becoming large in size. there were.
  • An object of the present invention is to provide means for providing at least one of an active element and a passive element on a compound semiconductor substrate having high heat resistance, so that the operating temperature and the space restrictions are severe.
  • An object of the present invention is to provide a semiconductor device suitable for being arranged in a semiconductor device. Disclosure of the invention
  • a first semiconductor device includes: a compound semiconductor layer provided on a substrate; at least one first semiconductor layer provided on the compound semiconductor layer and functioning as a carrier traveling region; The first semiconductor layer containing a carrier impurity of An active region formed by alternately laminating at least one second semiconductor layer having a smaller film thickness and capable of carrying a carrier by a quantum effect; and a plurality of active elements provided on the active region.
  • the carrier in the second semiconductor layer spreads to the first semiconductor layer, and carriers are distributed over the entire active region. Since the impurity concentration in the first semiconductor layer is low, the scattering of impurity ions in the first semiconductor layer is reduced. Therefore, when the MISFET or the diode is provided on the active region, the traveling speed of the carrier is particularly high. Is obtained. Moreover, in spite of the fact that the average impurity concentration in the active region is not low, the entire active region is depleted in the off state and no carriers are present in the active region. The withstand voltage is specified, and a high withstand voltage value can be obtained in the entire active region.
  • a high-performance active element integrated on the compound semiconductor layer can be obtained, so that the semiconductor device can be arranged at a desired portion without using solder even when used at a high temperature, for example. Therefore, the degree of freedom in arranging the semiconductor devices in the device is improved, and the size of the device itself using the semiconductor device can be reduced.
  • the plurality of active elements include the MISFET having the first semiconductor layer immediately below the gate insulating film, the impurity concentration of the first semiconductor layer is low. The number of charges trapped near the interface between the insulating film and the active region is also reduced, and the effect of the trapped charges on the carrier running is reduced. Therefore, an integrated semiconductor device having a higher channel mobility and having a MISFET is obtained.
  • a second conductivity type MISFET is provided in a portion where the first active region is exposed, while a first conductivity type MISFET is provided in the second active region.
  • the compound semiconductor layer is one semiconductor layer selected from a SiC layer, a GaN layer, an InP layer, a 1103 layer, and a 1 nGaPN layer, these compounds can be used.
  • a semiconductor device having particularly high heat resistance and high pressure resistance can be obtained.
  • a second semiconductor device includes a semiconductor layer selected from a SiC layer, a GaN layer, an InP layer, an InGaAs layer, and an InGaPN layer provided on a substrate; And an inductor provided on the semiconductor layer.
  • the semiconductor layer has at least one first semiconductor layer functioning as a carrier traveling region, and has a carrier concentration higher than that of the first semiconductor layer and has a thickness smaller than that of the first semiconductor layer.
  • At least one possible second semiconductor layer is alternately laminated, and further comprising a plurality of active elements provided on the semiconductor layer, the first semiconductor device can also be configured as a semiconductor. A highly functional semiconductor device provided on the layer is obtained.
  • FIG. 1 shows a semiconductor device in which a short-circuit diode, a MOS FET, a capacitor and an inductor are integrated on a SiC substrate according to a first embodiment of the present invention.
  • FIG. 2 is a plan view schematically showing a plane pattern of the semiconductor device according to the first embodiment.
  • FIGS. 3A to 3C are cross-sectional views showing steps from the formation of the first and second active regions to the formation of the element isolation region in the manufacturing process of the semiconductor device of the first embodiment. .
  • FIGS. 4A to 4C are cross-sectional views showing steps from the formation of a source / drain region to the formation of an electrode or a conductor film of each element in the manufacturing process of the semiconductor device of the first embodiment. is there.
  • FIGS. 5A and 5B are cross-sectional views showing steps from the formation of the upper electrode in the capacitor to the formation of the contact hole in the conductor of each element in the manufacturing process of the semiconductor device of the first embodiment.
  • FIG. 6 is a sectional view showing the structure of the fluorescent lamp device according to the second embodiment.
  • FIG. 7 is an electric circuit diagram illustrating a configuration of a lighting circuit in the fluorescent lamp device according to the second embodiment.
  • FIG. 8 is a diagram comparing the size of the lighting circuit of the second embodiment with the size of a conventional lighting circuit.
  • FIG. 9 is a diagram showing the results of measuring the impurity concentration of the short-circuit diode according to the first embodiment by the C-V method.
  • FIG. 10 is a diagram showing a measurement result of a band edge photoluminescence spectrum of a 5-doped layer in the 6 H—SiC substrate according to the first embodiment.
  • FIGS. 11A and 11B are data respectively showing the temperature dependence of the electron mobility and the temperature dependence of the electron concentration of the 6 H—S i C layer in the first embodiment.
  • FIG. 12 is data showing the temperature dependence of the electron mobility in samples A and B according to the first embodiment.
  • FIGS. 13 (a) and 13 (b) are diagrams showing the results of simulating the band structure at the conduction band edge of sample A in the first embodiment, and the results of simulating the carrier concentration distribution. .
  • FIGS. 14 (a) and 14 (b) show the conduction band of sample B in the first embodiment.
  • FIG. 9 is a diagram showing a result of simulating a band structure at an end, and a diagram showing a result of simulating a carrier concentration distribution.
  • FIG. 15 is a cross-sectional view of the ACCUFET according to the second embodiment.
  • FIG. 16 is a diagram illustrating the I-V characteristics of the ACCUFET created in the second embodiment.
  • Figure 17 is a diagram showing the gate voltage dependence of the effective channel mobility obtained by the calculation based on the data of Figure 16.
  • FIG. 18 is a cross-sectional view showing the structure of a conventional fluorescent lamp device.
  • FIG. 19 is an electric circuit diagram showing a configuration of a lighting circuit in a conventional fluorescent lamp device.
  • FIG. 1 is a cross-sectional view of an integrated semiconductor device in which a short-circuit diode, a MOS FET, a capacitor, and an inductor are integrated on a SiC substrate according to a first embodiment of the present invention. is there.
  • the S i C S i C substrate 1 0 is a substrate, and an average concentration of about 1 x 1 0 17 atoms • c m_ first active region 1 2 nitrogen doped n-type 3, A p-type second active region 13 doped with aluminum having an average concentration of about 1 ⁇ 10 17 atoms ⁇ cm— 3 is provided in order from the bottom, and the second active region 13 Is removed to expose a part of the first active region 12 on the substrate. Then, an element isolation region 11 in which a silicon oxide film is buried in a trench is provided for partitioning each of the active regions 12 and 13 for each element.
  • the first active region 12 has a thickness of about 1 O nm containing a high concentration (for example, 1 ⁇ 10 18 atoms ⁇ cm— 3 ) of nitrogen.
  • a high concentration for example, 1 ⁇ 10 18 atoms ⁇ cm— 3
  • An n-type doped layer 12a and an undoped 4H—SiC single crystal and a so-called undoped layer 12b with a thickness of about 50 nm are alternately stacked in layers of 20 layers each. I have.
  • the second active region 13 has a high concentration (for example, 1 ⁇ 10 18 atoms ⁇ cm— 3 ) of aluminum.
  • a p-type doped layer 13a with a thickness of about 10 nm, and an And-doped layer 13b with a thickness of about 5 O nm made of an unbound 4H—SiC single crystal. are alternately stacked, each having 20 layers.
  • Each of the n-type doped layer 12 a and the p-type doped layer 13 a has such a size that the carriers can seep into the AND layers 12 b and 13 b due to the quantum effect. It is formed thin.
  • a Schottky diode 20 rectifying element
  • a PMO SFET 30 switching element
  • nMOSFET 40 switching element
  • a capacitor 50 Capacitive element
  • 60 inductive element
  • the above-mentioned short-circuit diode 20 has a short-circuit electrode 21 made of nickel (Ni) in short-circuit contact with the first active region 12, and a high-concentration nitrogen in the first active region 12.
  • the electrode lead-out layer 2 2 which is formed by implanting, nickel (N i) of O seemingly Dzukukontaku preparative the electrode lead-out layer 22 O seemingly brute electrode 2 And three.
  • the pMOS SFET 3 0 has a S i 0 2 or Ranaru gate insulating film 3 1 formed on the first active region 1 2, the N i alloy film formed on the gate insulating film 3 1
  • 3a and the drain region 33b, and the source region 33a and the drain region 43b each include a source electrode 34 and a drain electrode 35 made of a Ni alloy film which are mixed together. ing.
  • the NMO S FE T 40 includes a S i 0 2 or Ranaru gate insulating film 4 1 formed on the second active region 1 3, N i alloy film formed on the gate insulating film 4 1 And an n-type electrode formed by injecting nitrogen at a concentration of 1 ⁇ 10 18 cm 3 into regions of the second active region 13 located on both sides of the gate electrode 42.
  • the semiconductor device includes a source region 43a and a drain region 43b, and a source electrode 44 and a drain electrode 45 made of a Ni alloy film, which are mixed in the source region 43a and the drain region 43b, respectively.
  • the capacity 50 is composed of a base insulating film 51 made of a SiN film provided on the second active region 13 and a platinum (Pt) provided on the base insulating film 51. ), A lower electrode 52 made of a film, a capacitor insulating film 53 made of a high dielectric film such as BST provided on the lower electrode 52, and a lower electrode 52 sandwiching the capacitor insulating film 53. And an upper electrode 5 made of a platinum (Pt) film opposed thereto.
  • the inductor 60 includes a dielectric film 61 made of a SiN film provided on the first active region 12, and a spiral Cu film formed on the dielectric film 61. And a conductor film 62 made of.
  • the width of the conductive film 62 is about 9 mm
  • the thickness is about 4 mm
  • the gap between the conductive films 62 is about 4 mm.
  • the conductor film 62 can be miniaturized depending on the amount of current, and a finer pattern, for example, having a width of l Shapes of ⁇ 2 / m and gaps of about 1-2 m are also possible.
  • An interlayer insulating film 70 made of a silicon oxide film is formed on the substrate, and a wiring 72 made of an aluminum alloy film, a Cu alloy film, or the like is provided on the interlayer insulating film 70. .
  • the conductor of each of the elements 20, 30, 40, 50, 60 has a contact 71 made of an aluminum alloy film or the like that fills a contact hole formed in the interlayer insulating film 70. It is connected to the wiring 72 through.
  • FIG. 2 is a plan view schematically showing a plane pattern of the semiconductor device according to the present embodiment.
  • a rectifier circuit including four Schottky diodes 20 an inverter circuit including pMO SFET 30 and nMO SFET 40, a capacitor 50, and an inductor 60 are connected to a wiring 72.
  • a control signal is inputted to each of the gate electrodes 32 and 42 of the pMOSFET 30 and the HMOSFET 40 of the inverter circuit via a pad 75.
  • a smoothing capacitor (corresponding to the capacitor capacitor 214 shown in FIG. 19) may be inserted between the rectifier circuit and the inverter circuit.
  • the Schottky diode 20, the pMOS FET 30, the nMOS FET 40, the capacitor 50 and the inductor 60 are placed on the common SiC substrate 10. Since it is integrated, it provides semiconductor devices that have high power and high withstand voltage characteristics and are suitable for equipment such as vacuum cleaners, washing machines, refrigerators, fluorescent lights, and air conditioners. Can be In particular, by mounting the inductor 60, which was conventionally externally attached by soldering, etc., together with other elements on the SiC substrate 10, the limited space in the device is not restricted by temperature. Semiconductor devices can be arranged freely.
  • the dielectric film 61 of the above-described inductor 60 be formed of a BC film (benzocycloptene film).
  • the BCB film refers to a film containing BCB in the structure obtained by dissolving BCB-DVS monomer in a solvent, applying the solution, and then baking.
  • the BCB film has a characteristic that the relative dielectric constant is as small as about 2.7 and a thick film of about 30 ⁇ m can be easily formed by one application.
  • the dielectric film is tan [delta] of the BCB film since 6 0 GH z 1 order of magnitude less than 0.0 0 6 degrees and S i 0 2 in, BCB film particularly constituting Indakuta and microstrip flop line Excellent characteristics can be exhibited.
  • the first active region 12 and the second active region 13 having the structure shown in the lower part of FIG. Such a remarkable effect as described above can be exerted.
  • the Schottky diode 20 when a forward bias is applied to the Schottky diode 20, the potential of the first active region 12 is increased, and the n-type doped layer 12a and the undoped The energy level at the conduction band edge in layer 12b increases. At this time, the carriers in the n-type doped layer 12 a also seep into the undoped layer 12 b by the quantum effect, so that the n-type doped layer 12 a of the first active region 12 and the AND layer 1 2 Through both b and b, a current easily flows through the short-circuit electrode 21. That is, not only the n-type doped layer 12a of the first active region 12 but also the undoped layer 12b functions as a carrier traveling region.
  • the impurity concentration in the undoped layer 12b is low because the impurity concentration in the undoped layer 12b is low. Pure object scattering is reduced. Therefore, the resistance value can be kept low, and low power consumption and large current can be realized.
  • the depletion layer spreads from the AND layer 12 b of the first active region 12 to the n-type dopant layer 12 a, Since the entire active region 1 2 is easily depleted, a large breakdown voltage can be obtained. Therefore, a power diode with a low on-resistance, a high power, and a high withstand voltage can be realized. In particular, by making this power diode a horizontal structure, it became easy to integrate the power diode together with the power MOSFET on a common SiC substrate.
  • the driving voltage is applied to the gate electrode 32, and in the inversion state in which the carrier travels, it is bent upward by the potential e V corresponding to the applied voltage V. Holes are collected at the end of the valence electrons, and the holes travel along the channel layer of the first active region 12 according to the potential difference between the source region 33a and the drain region 33b. Will do.
  • the concentration of carriers here, holes
  • the gate insulating film of the MOSFET is almost always an oxide film formed by heat treatment of the substrate, the positive electrode trapped in the gate insulating film 31 formed by thermally oxidizing the undoped layer 12 is The charge is small. Therefore, the holes in the first active region 12, particularly the holes flowing through the uppermost amplifier layer 12 b, are hardly subject to the traveling hindrance due to the interaction with the charge in the gate insulating film 31. The lack of this also improves channel mobility.
  • the driving voltage is not applied to the gate electrode 32, even if a high voltage is applied between the source region 33a and the drain region 33b, the short-circuit diode 20 is not applied. As in the case, the depletion layer easily spreads from the AND layer 12 b to the n-type doped layer 12 a, so that a high withstand voltage is exhibited. Can be.
  • nMO SFET 40 As in the case of the pMOFET, electrons traveling in the channel region are scattered by impurity ions in the channel region due to negative charges trapped by impurities in the gate insulating film. Since it is hardly affected by interference, it can exhibit high withstand voltage, low on-resistance, large current capacity, and high transconductance characteristics.
  • FIGS. 3A to 3C are cross-sectional views showing steps from the formation of the first and second active regions to the formation of the element isolation region in the manufacturing process of the semiconductor device of the present embodiment.
  • FIGS. 4 (a) to 4 (c) are cross-sectional views showing steps from the formation of the source and drain regions to the formation of the electrodes or conductor films of each element in the manufacturing steps of the semiconductor device of the present embodiment.
  • FIGS. 5A and 5B are cross-sectional views showing steps from the formation of the upper electrode in the capacity to the formation of a contact hole in the conductor of each element in the manufacturing process of the semiconductor device of the present embodiment. .
  • a p-type SiC substrate 10 is prepared.
  • a 4H—SiC substrate having a main surface having an orientation coinciding with the ⁇ 11-20 ⁇ plane (eight faces) is used as the SiC substrate 10.
  • an S i C substrate whose main surface has an orientation shifted from the (00001) plane (C plane) by several degrees may be used.
  • the SiC substrate 10 was thermally oxidized at 110 ° C. for about 3 hours, and a surface having a thickness of about 40 nm was formed.
  • hydrogen gas at a flow rate of 2 (1 / min) and argon gas at a flow rate of 1 (1 / min) are supplied as dilution gases into the chamber, Assuming that the pressure in the chamber is 0.093 MPa, the substrate temperature is controlled at about 160 ° C. While maintaining the flow rates of hydrogen gas and argon gas at the above-mentioned fixed values, propane gas with a flow rate of 2 (ml / min) and silane gas with a flow rate of 3 (ml / min) are introduced into the chamber as raw material gases. I do. The source gas is diluted with 50 (ml / min) hydrogen gas.
  • nitrogen which is an n-type impurity
  • the main surface of the SiC substrate 10 is An n-type doped layer 12a (high concentration doped layer) with a thickness of about 1 O nm is formed.
  • nitrogen is housed in a high-pressure cylinder as a doping gas, and a pulse valve is provided between the high-pressure cylinder and a doping gas supply pipe.
  • the supply of the doping gas is stopped, that is, while the pulse valve is completely closed, the propane gas and the silane gas are mixed with the SiC substrate 10a.
  • the propane gas and the silane gas are mixed with the SiC substrate 10a.
  • the n-type doping layer 12a is formed by simultaneously opening and closing the pulse valve and introducing the driving gas while supplying the source gas, and the doping gas is not supplied while the pulse valve is closed.
  • the formation of the n-type doped layer 12 b and the formation of the n-type doped layer 12 b are alternately repeated 20 times each by repeating the formation of the n-type doped layer 12 b only 20 times.
  • a first active region 12 formed by lamination is formed.
  • an AND layer 12b is formed as the uppermost layer, and its thickness is made about 15 nm thicker than the other undoped layers 12b.
  • the average nitrogen concentration in the first active region 12 is about lxl 0 17 atoms ⁇ cm— 3 , and the total thickness of the first active region 12 after completion of thermal oxidation is 110 O nm It is.
  • the doping gas is switched to a gas containing aluminum, which is a p-type impurity (doping gas), while keeping the source gas and the diluent gas as they are, so that a thickness of about 10 nm p-type doped layer 13a (highly doped Layer).
  • a gas containing aluminum which is a p-type impurity (doping gas)
  • the source gas and the diluent gas as they are, so that a thickness of about 10 nm p-type doped layer 13a (highly doped Layer).
  • the driving gas for example, a hydrogen gas containing about 10% of trimethylaluminum (A 1 (CH 3 ) 3 ) is used.
  • the p-type doping layer 13a is formed by introducing a doping gas (hydrogen gas containing trimethylaluminum) by simultaneously opening and closing the pulse valve while supplying the raw material gas, and the pulse valve closed.
  • a doping gas hydrogen gas containing trimethylaluminum
  • the p-type doped layer 13 a and the AND layer 13 b Are alternately stacked for 20 periods to form a second active region 13.
  • an AND layer 13b is formed on the uppermost layer, and its thickness is set to another AND layer. Make it about 15 nm thicker than 13 b.
  • Average aluminum concentration in the range 1 3 is about 1 X 1 0 1 7 atoms' cm 3, the thickness of the bets one barrel in the second active region 1 3 after the completion of thermal oxidation, about 1 1 0 O nm It is.
  • a portion of the second active region 13 where the short-circuit diode 20 and the pMOSFET 30 are to be formed is removed by selective etching. Then, the first active region 12 is exposed in a region where the Schottky diode 20 and the pMOSFET 30 are to be formed.
  • a trench for forming an element isolation region is formed in the substrate, and a silicon oxide film is buried in the trench to form an element isolation region 11.
  • a p-type impurity for example, aluminum ion A 1 +
  • a p-type impurity for example, aluminum ion A 1 +
  • the source region 33a and the drain region 33b are formed.
  • the substrate temperature is reduced.
  • Heating is performed between 500 and 800 ° C., and ions such as aluminum ions (A 1 +) are implanted from above the implantation mask.
  • ions such as aluminum ions (A 1 +) are implanted from above the implantation mask.
  • the activity of impurities By annealing for 10 minutes at a temperature of 150 ° C. for 10 minutes, the p-type impurity concentration is about 1 ⁇ 10 18 atoms ⁇ cm— 3 , the electrode extraction layer 22, the source region 33a and A drain region 33b is formed.
  • aluminum ions (A 1+) are implanted into the substrate in, for example, six ion implantation steps having different implantation energies.
  • the condition of the first ion implantation is an acceleration voltage of 180 keV, a dose of 1.5 xl 0 14 atoms ⁇ cm— 2
  • the condition of the second ion implantation is an acceleration voltage of 130 keV
  • the third ion implantation conditions are an acceleration voltage 1 1 0 ke V
  • de Ichizu amount 5 x 1 0" de Ichizu weight 1 X 1 0 in atoms' cm- 2
  • 4th ion implantation conditions are an acceleration voltage 1 0 0 ke V
  • the fifth ion implantation conditions are an acceleration voltage 6 0 ke V
  • 6th ion implantation conditions are an acceleration voltage of 3 0 k eV
  • the source region 43a and the drain region 43b of the nMOS FET 40 are formed by implanting n-type impurities (for example, nitrogen ions N +).
  • n-type impurities for example, nitrogen ions N +
  • the substrate temperature is decreased. Heating is performed at 500 to 800 ° C., and ions such as nitrogen ions (N +) are implanted from above the implantation mask. Further, annealing for activating the impurities is performed at a temperature of 1500 ° C. for 10 minutes, so that the implantation depth is about 0.8 and the n-type impurity concentration is about 1 ⁇ 10 18 atoms ⁇ cm.
  • - 3 of the source region 4 3 forms a and the drain region 4 3 b.
  • a plasma CVD method is used to form a SiON film having a thickness of about 0.4 ⁇ m.
  • a base insulating film 51 and a dielectric film 61 are formed on a region of the second active region 13 where the capacitor 50 and the inductor 60 are to be formed.
  • the MOS FET formation region in the MOS FET formation region, the uppermost undoped layer 1 of the first and second active regions 12 and 13 at a temperature of about 110 ° C.
  • gate insulating films 31 and 41 consisting of a thermal oxide film with a thickness of about 30 nm are formed.
  • portions of the gate insulating films 31 and 41 located above the source region 33a and the drain region 33b were removed to form openings, and N formed in the openings by vacuum evaporation was used.
  • Source electrodes 34 and 44 and drain electrodes 35 and 45 made of an i-alloy film are formed.
  • an ohmic electrode 23 made of a Ni alloy film is also formed on the electrode lead layer 22 of the Schottky diode 20.
  • a titanium (T i) alloy film is deposited on the gate insulating films 31 and 41 to form gate electrodes 32 and 42 made of a titanium alloy film and having a gate length of about 1 m.
  • a Nitrogen (Ni) vapor deposition is performed on a region of the first active region 12 where the Schottky diode 20 is to be formed, thereby forming a Schottky electrode 21 made of Nikel and forming a capacitor.
  • platinum (Pt) is deposited on the base insulating film 51 to form a lower electrode 52 made of platinum.
  • a resist film having a spiral opening is formed in the region where the inductor 60 is to be formed, and then a CI film having a thickness of about 4 m is deposited thereon, and lift-off is performed.
  • the spiral conductive film 62 is left on the dielectric film 61.
  • the conductor film may be formed of an aluminum alloy film instead of the Cu film. In that case, after depositing an aluminum alloy film, to form a C l 2 gas and BC 1 3 gas and the Aruminiumu alloy film Pas evening by-learning by RIE Doraiedzuchingu who were use to scan Pairaru like conductor film 6 2 .
  • a BST film is formed on the lower electrode of the capacitor 50 by a sputtering method, and then a platinum (Pt) film is formed on the BST film by a vapor deposition method. Form. Then, the platinum film and the BST film are patterned into a predetermined shape to form the upper electrode 54 and the capacitance insulating film 53.
  • an interlayer insulating film 70 made of a silicon oxide film is deposited on the substrate, and a short-circuit electrode 21 and a short-circuit electrode 23 of a short-circuit diode 20 are deposited on the interlayer insulating film 70.
  • the source electrode 34 and the drain electrode 35 of p MOSFET 30 and n M 0 Contacts reaching the source electrode 44 and drain electrode 45 of the SFET 40, the upper electrode 54 and the lower electrode 52 of the capacitor 50, and the center of the spiral of the conductor film 62 of the inductor 60, respectively.
  • a hole 74 is formed.
  • the SiC layer is used, but not only the semiconductor device provided on the SiC layer, but also, for example, a GaAs layer, a GaN layer, an AlGaAs layer, a SiGe layer, a Si
  • This embodiment can be applied to general semiconductor devices such as a GeC layer, an InP layer, an InGaAs layer, and an InGaPN layer, which are provided on a compound semiconductor substrate made of a compound of a plurality of elements.
  • the active region in which the ⁇ -doped layer and the lightly doped layer (including the AND layer) are stacked is provided below the gate insulating film to reduce impurity ion scattering and reduce the off-state.
  • the SiC layer, the InP layer, the InGaAs layer, the InGaPN layer, and the GaN layer are used, a device having extremely high channel mobility can be obtained.
  • FIG. 6 is a cross-sectional view showing the structure of the bulb-type fluorescent lamp device 80 according to the present embodiment.
  • the fluorescent lamp device 80 includes a fluorescent lamp 81 formed by connecting three substantially U-shaped arc tubes by a bridge, and a fluorescent lamp 81 for lighting the fluorescent lamp 81.
  • a lighting circuit 82 including elements such as a semiconductor chip, a cover 83 for accommodating the lighting circuit 82, a base 84 attached to the tip of the cover 83, a globe 85 for surrounding the fluorescent lamp 81, and lighting.
  • a circuit board 86 on which the circuit 82 is mounted.
  • FIG. 7 is an electric circuit diagram showing a configuration of a lighting circuit 82 in the fluorescent lamp device 80.
  • the lighting circuit 82 includes a line filter circuit 87 and a rectifier circuit. 88, a power supply smoothing capacitor 89, an inverter circuit 90, an inductor 91, and a resonance capacitor 92.
  • the inverter circuit 90 is composed of a pMOSFET, an nMOSFET, and an inverter capacitor.
  • the fluorescent lamp 81 is arranged in parallel with the resonance capacitor 92, and is configured to emit fluorescent light by flowing a discharge current between the electrodes 93, 94 at both ends of the fluorescent lamp 81. I have.
  • the feature of the fluorescent lamp device 80 in the present embodiment is that, as shown in FIG. 6, each member in the lighting circuit 82 is mounted on one SiC substrate, and the entire lighting circuit 82 is It is a point that it is miniaturized. That is, as described later, the lighting circuit 82 in the present embodiment can be reduced in size to, for example, about 10 to 15 mm square, and the entire thickness thereof is smaller than the thickness of the SiC substrate.
  • the lighting circuit 82 as a whole has an extremely thin structure because the thickness of the stacked film and the interlayer insulating film is only added. As a result, the lighting circuit 82 can be arranged at the small-diameter portion near the base 84, and the size of the lamp itself can be reduced.
  • the active elements such as the MOS FET and the short-circuit diode have a horizontal structure, and the MOS FET and the short-circuit diode are provided in the common SiC substrate. This enabled the integration to be easier.
  • passive elements such as inductors can be mounted on a common SiC substrate, further miniaturization can be achieved.
  • FIG. 8 is a diagram showing a comparison between the size of the lighting circuit 82 of the present embodiment and the size of the conventional lighting circuit (see the broken line) described in the above-mentioned publication.
  • the space occupied by each member can be reduced as described below.
  • the MOS FET has a gate length of 1 m
  • the area of the invertor can be accommodated in an area of several 10 m to several 100 m square.
  • a rectifier circuit consisting of four short-circuit diodes can be accommodated in the same or smaller area, while Inductor has a spiral conductor film with a line width of 9 / m in an area of about 5 mm square. If the interval is set at 4 ⁇ m, the number of evenings will be about 160 times and the inductance will be 780 ⁇ H.
  • an inductor used in a lighting circuit of a fluorescent lamp device is used. Since the inductance of the cubic element is about 400 to 700H in total, it is possible to provide an inductor that satisfies this specification if it has an area of about 5 mm square.
  • the BST film can be made as thin as about 100 nm with a relative dielectric constant of about 100 nm. Therefore, a capacity of about 22 ⁇ F is obtained.
  • the capacity of the capacitor used for the smoothing capacitor in the lighting circuit of the fluorescent lamp device is about 20 to 30 / F.
  • the capacity arranged in other circuits only needs to have a capacity of the order of nF, so that a large area is not required. Therefore, as shown in FIG. 8, an area for arranging the capacity of the entire lighting circuit can be secured on the SiC substrate of 10 to 20 mm square.
  • the temperature at which the normal operation of the MOSFET and the Schottky diode formed on the SiC substrate can be ensured is around 400 ° C, so that the conventional SiC substrate was installed on the SiC substrate.
  • various restrictions imposed by the severe upper limit of 150 ° C are greatly reduced.
  • the temperature due to the heat generated by the choke coil exceeds 150 ° C., and considering the heat dissipation from the lamp, there is no difference between the FET in the inverter circuit and the diode in the rectifier circuit. , Chiyo-It was necessary to arrange it at a position away from the coil.
  • the heat resistance of the MOS FET and the short-circuit diode on the SiC substrate is high, even if all the elements are arranged close to each other, almost no trouble occurs due to the heat resistance.
  • the lighting circuit can be significantly reduced in size, a high degree of freedom in arrangement within the lamp can be ensured, and since the SiC substrate has high thermal conductivity and good heat dissipation, the lighting circuit Each element in 82 can be easily prevented from being adversely affected by the heat dissipation of the fluorescent lamp 81.
  • the lighting circuit 82 of the present embodiment it is also possible to arrange a part of the induction circuit or the capacity circuit on the back surface of the SiC substrate to effectively utilize the area of the substrate.
  • a structure in which the entire chip of the SiC substrate is buried in glass such as quartz glass and arranged in a bulb can be adopted.
  • the semiconductor device of the present invention is arranged in a device such as an air conditioner, a vacuum cleaner, a washing machine, and a refrigerator when the device is used at a high temperature or a control circuit needs to be housed in a narrow space.
  • a device such as an air conditioner, a vacuum cleaner, a washing machine, and a refrigerator
  • the effects described in the above embodiment can be exerted.
  • strict heat resistance and intensiveness are required for devices that are particularly small and generate a large amount of heat, such as lamp lighting circuits, so that the application of the present invention exerts a remarkable effect. be able to.
  • the SiC layer is used.
  • semi-insulating layers other than the SiC layer for example, GaAs layer, GaN layer, AlGaAs layer, SiGe layer.
  • a substrate composed of a SiGeC layer, an InP layer, an InGaPN, and the like can be used.
  • an InP substrate or an InGaPN substrate is used, an extremely high-speed transistor can be obtained.
  • a horizontal diode and a MOS FET are provided as active elements.
  • the active element of the present invention is not limited to such an embodiment, and a vertical diode and a vertical diode are used. It can also be applied to power MOSFETs. That is, the vertical type active element and the horizontal type active element may be provided on a common substrate such as a SiC substrate, or a plurality of vertical type active elements may be provided on a common substrate such as a SiC substrate. May be provided.
  • FIG. 9 is a diagram showing the result of performing the above.
  • the measurement by the C—V method is as follows: a bias is applied to a shot diode having a circular Ni shot electrode having a diameter of 300 ⁇ between 0.5 V and 0.2 V, and The voltage was changed from 2 V to 12 V, and a high-frequency signal of 1 MHz with a small amplitude was applied to the voltage.
  • the profile of the impurity concentration shown in the figure is for a 6-dope layer extracted from a stack of a 5-dop layer having a thickness of 1 O nm and an AND layer having a thickness of 50 nm. belongs to.
  • the concentration profile in the depth direction Are almost vertically symmetrical, indicating that the epitaxial method of the embodiment of the present invention can neglect the doping memory effect (done-don residual effect) during epitaxial growth by CVD.
  • the planar carrier concentration of the five-doped layer is 1.5 ⁇ 10 12 cm— 2
  • the planar carrier concentration obtained from the measurement of the Hall coefficient is about 2.5. It is relatively well matched to X 10 12 cm- 2 .
  • the half-width of this pulse-like profile is formed to be 12 nm, indicating a remarkable steepness.
  • FIG. 10 is a diagram showing the measurement results of the band-edge photoluminescence spectrum of the ⁇ 5 doped layer in the 6 H—SiC substrate. This spectrum was obtained at a temperature of 8 K, and a 0.5 mW He-Cd laser was used as the excitation source.
  • the spectrum obtained from the layer obtained by stacking a ⁇ -doped layer with a thickness of 1 O nm and an amplifier layer with a thickness of 5 O nm, and an amplifier layer with a thickness of l ⁇ m It is compared with the spectrum obtained from. As shown in the figure, both spectrum patterns have the same intensity of emission peak in the same wavelength region, and thus it can be seen that both have the same impurity concentration.
  • the undoped layer in the stacked structure composed of the five-doped layer and the doped layer has almost no increase in the impurity concentration due to the diffusion of the impurity from the five-doped layer.
  • the impurity concentration of the AND layer is controlled to a low value of about 5 xl 0 16 atoms ⁇ cm- 3.
  • the impurity concentration of the AND layer in the active region obtained by alternately stacking the doped layer and the undoped layer of the present invention is about 5 ⁇ 10 16 atoms ⁇ cm— 3. It was confirmed that the concentration was low.
  • Figures 11 (a) and 11 (b) show the data showing the temperature dependence of the electron mobility and the electron concentration of the 6H—SiC layer, respectively.
  • the symbols marked with a triangle indicate a five-doped layer with a thickness of 10 nm (dopant is nitrogen) and an and-doped layer with a thickness of 50 nm.
  • 6H—SiC layer Sample A
  • the data in the image shows the data for the low-concentration uniform doping layer (1.8 ⁇ 10 16 cm— 3 ) of 6 H—S i C.
  • a de Isseki for the high density uniformity de one flops layer C (1.
  • the electron concentration is as high as the highly doped layer, and the electron mobility is high. That is, since the active region of the present invention can realize high electron mobility while having a high electron concentration, it has a structure suitable for a region where electrons in a diode transistor travel. You can see that In addition, even if the carrier is a hole, there is no difference in principle from the case of an electron.Therefore, it is possible to realize high hole mobility while increasing the hole concentration in the five ⁇ -type layers. You can think.
  • Figure 12 shows a sample A having an active region formed by laminating a 10 nm thick (5 doped layer and an undoped layer having a thickness of 50 nm) described above, and a 20 nm thick d-doped layer.
  • This is data showing the temperature dependence of electron mobility in sample B having an active region formed by laminating a layer and an undoped layer having a thickness of 100 nm. It is measured in the range of up to 300 K.
  • the ratio of the thickness of the 5-doped layer to the undoped layer is made common to 1: 5, and
  • the electron mobility of sample A is larger than that of sample B, even though the average impurity concentrations of B and B are the same.
  • the electron mobility in Sample B is As the temperature decreases, the electron mobility decreases due to scattering by ionized impurities, but Sample A shows that high electron mobility is maintained even at lower temperatures.
  • Figs. 13 (a) and 13 (b) show the results of simulating the band structure at the conduction band edge in sample A having a 10-nm-thick five-doped layer, and the carrier concentration. It is a figure showing the result of having simulated distribution.
  • Fig. 7 shows a result of simulating the band structure at the conduction band edge in sample B having a thickness of 20 nm (5 having a 5-doped layer, and a result of simulating the carrier concentration distribution.
  • (a) As shown in Fig. 14 (a), in the cross section perpendicular to the ⁇ -dove layer, the electrons move to the V-type Coulomb potential (quantum well) composed of one positively charged donor layer.
  • the effective mass of the electrons is 1.1
  • the relative permittivity of the 6 ⁇ -SiC layer is 9.66.
  • the carrier concentration in the background of the 6H—SiC layer obtained is about lxl 0 15 cm— 3
  • the carrier concentration in the n-type 6-doped layer is 1 ⁇ 10 18 cm— 3 .
  • the thickness of the high-concentration doping layer is preferably one monolayer or more and less than 20 nm when using a SiC layer. I understand. Also, the thickness of the low concentration dove layer (including the AND layer) is preferably about 10 nm or more and about 100 nm or less. The thickness of these high-concentration doped layers and low-concentration doped layers should be appropriately selected according to the type and purpose of active elements (diodes, transistors, etc.) formed using these layers. Can be.
  • a laminated structure of a lead layer and an AND layer is used.
  • An AC CU FET (Accumulation Mode FET) functioning as a switching transistor of a large current is used instead of the M 0 SFET of the integrated semiconductor device in the first embodiment.
  • FIG. 15 is a cross-sectional view showing the structure of only the ACCUFET portion in the present embodiment.
  • the p-type SiC substrate 130 doped with aluminum (p-type impurity) having a concentration of 1 ⁇ 10 18 atoms cm 3 , an average concentration of about 1 ⁇ 10 A p-type lower active region 13 1 in which aluminum of 17 atoms.cm 3 is doped, and nitrogen having an average concentration of about 1 ⁇ 10 17 atoms cm 3 formed on the lower active region 13 1
  • the gate electrode 135 made of the Ni alloy film and the source electrode 13 made of the Ni alloy film which are mixed
  • the lower active region 13 1 has a thickness of about 10 nm containing a high concentration (for example, 1 ⁇ 10 18 atoms.cm 3 ) of aluminum.
  • a high concentration for example, 1 ⁇ 10 18 atoms.cm 3
  • Approximately 40 layers are alternately laminated with p-type doped layers 13a and undoped SiC single-crystal AND-layers 13b with a thickness of about 50 nm. .
  • the total thickness is about 240 nm.
  • the p-type doped layer 13 la is formed so thin that the carrier can seep into the undoped layer 13 1 b due to the quantum effect. Negative charges are trapped in the layer 13 la.
  • the upper active region 13 2 has a high concentration (for example, 1 ⁇ 10 18 atoms ⁇ cm 3 ) of about 10 nm thick n. It is constituted by alternately laminating five types of doped layers 13a and five undoped layers 1332b each having a thickness of about 50 nm and made of an AND SiC single crystal. That is, the thickness of the tower is about 300 nm. And the n-type doped layer 1 3 2 a by the quantum effect Then, a quantum level is generated, and the wave function of the localized electrons in the n-type doped layer 132a has a certain degree of spread.
  • a quantum level is generated, and the wave function of the localized electrons in the n-type doped layer 132a has a certain degree of spread.
  • the distribution state is such that electrons are present not only in the n-type doped layer 132a but also in the undoped layer 132b.
  • the n-type doped layer Electrons are constantly supplied to 1 32 a and undoped layer 1 32 b. Since electrons flow through the undoped layer 132b having a low impurity concentration, high channel mobility can be obtained by reducing impurity ion scattering.
  • the entire upper active region 132 is depleted, and no electrons are present in the upper active region 132, so that the withstand voltage is regulated by the low impurity concentration of the AND layer 132b.
  • a high breakdown voltage can be obtained in the entire upper active region 132. Therefore, high channel mobility and high withstand voltage can be achieved in an AC CUFET configured to allow a large current to flow between the source and drain regions 133a and 133b using the upper active region 133. Can be realized at the same time.
  • the gate insulating film 134 and the gate insulating film 134- Channel mobility can be improved by reducing charges trapped near the interface between the upper active regions 132, channel mobility can be improved by reducing impurity ion scattering, and withstand voltage can be improved.
  • the gate voltage dependence of the current-voltage characteristics (the relationship between the drain current and the drain voltage) of the ACCUFET of the present embodiment was examined.
  • the saturation current amount was lower than that of the n-channel type MOSFET in the first embodiment. It is clear that the number has increased further.
  • the drain voltage is 400 V or more, a stable drain current can be obtained without breakdown, the breakdown voltage in the off state is 600 V or more, and the on resistance is as low as ⁇ 'cm 2 The value has been realized.
  • AC CUP 1 ET is characterized in that the saturation current value is large and the on-resistance is small.
  • one of the major reasons that it has not yet been put to practical use is that it has poor pressure resistance in the off state.
  • a high withstand voltage in the off state can be ensured by using the stacked structure of the 6-doped layer and the undoped layer as described above. It can be said that it has made great strides toward practical use.
  • the manufacturing process of the integrated semiconductor device having the AC CUFET according to the present embodiment is basically the same as the manufacturing process of the integrated semiconductor device according to the first embodiment, and a description thereof will be omitted.
  • the lower active region 131 formed by alternately stacking 6-doped layers and AND-doped layers is provided, but the lower active region is not necessarily required. Further, a uniformly doped low concentration doped layer or an AND layer may be provided in place of the lower active region. However, by providing the lower active region 131 in which the five-doped layers and the and-doped layers are alternately stacked, the breakdown voltage in the region below the channel can be further increased.
  • FIG. 16 shows the IV characteristics of the AC CUT of the present embodiment when the gate bias V g is changed from 15 V to 25 V in steps of 5 V (drain current changes with change in drain voltage).
  • FIG. 16 shows the IV characteristics of the AC CUT of the present embodiment when the gate bias V g is changed from 15 V to 25 V in steps of 5 V (drain current changes with change in drain voltage).
  • FIG. 16 shows the IV characteristics of the AC CUT of the present embodiment when the gate bias V g is changed from 15 V to 25 V in steps of 5 V (drain current changes with change in drain voltage).
  • FIG. 16 shows the IV characteristics of the AC CUT of the present embodiment when the gate bias V g is changed from 15 V to 25 V in steps of 5 V (drain current changes with change in drain voltage).
  • FIG. 16 shows the IV characteristics of the AC CUT of the present embodiment when the gate bias V g is changed from 15 V to 25 V in steps of 5 V (drain current changes with change in drain voltage).
  • FIG. 16 shows the IV characteristics of the
  • Fig. 17 is a diagram showing the dependence of the effective channel mobility on the gate voltage, obtained by calculation based on the data in Fig. 16.
  • the AC CUFET of the present embodiment has an effective channel mobility of 50 (cm 2 / V s) or more even when the gate bias is increased.
  • the current driving force of the FET is proportional to the effective channel mobility.
  • the AC CUT of the present embodiment has a structure in which the 6-doped layer and the AND layer are alternately stacked as described above. It shows that it has a high effective channel mobility and consequently a large current driving force.
  • a semiconductor layer other than the SiC layer can be used.
  • an InP layer, an InGaAs layer or an InGaPN layer on an InP substrate can be used.
  • a GaN layer on a sapphire substrate, a GaN substrate, or the like can be used.
  • known compound semiconductor layers such as a GaAs layer, an AlGaAs layer, a GaN layer, an AlGaN layer, a SiGe layer, and a SiGeC layer can be used.
  • the thickness of the high-concentration doped layer (5-doped layer) is determined appropriately according to the material.
  • the breakdown voltage can be maintained at the same thickness.
  • the thickness of the high-concentration doping layer ((5 doping layer) is smaller).
  • the structure of the semiconductor device in this case is basically the same as the structure shown in FIG. 1, and a Schottky diode, a MOS FET, a capacitor, and an inductor are formed using the InGaAs layer on the InP substrate. To form an integrated semiconductor device.
  • a semi-insulating InP substrate having a thickness of about 100 .mu.m and doped with high-concentration iron (Fe) is used instead of the Si substrate 10.
  • an InGaAs single crystal (component) containing a high concentration (for example, 1 ⁇ 10 20 atoms ⁇ cm ⁇ 3 ) of Si (silicon) and having a thickness of about 1 nm is used instead of the first active region 12.
  • the ratio for example I n o. S3 G a o . 47 A s) or a Ranaru ri type de one flop layer, I NGAA s single crystal (composition ratio is, for example, I n .. 53 G a ..
  • a layer of about 10 nm in thickness and alternately stacked in layers instead of the second active region 13, a p-type doped layer containing a high concentration (for example, 1 ⁇ 10 20 atoms ⁇ cm 3 ) of Zn (Be) and having a thickness of about 1 nm, I n a 1 a s monocrystalline Ichipu (component ratio is for example I no. 52 a 1 0. 48 a s) Tona Ru lamination thickness and and one-flop layer of about 1 0 nm by multiple layers alternating Use
  • a p-type doped layer containing a high concentration (for example, 1 ⁇ 10 20 atoms ⁇ cm 3 ) of Zn (Be) and having a thickness of about 1 nm I n a 1 a s monocrystalline Ichipu (component ratio is for example I no. 52 a 1 0. 48 a s) Tona Ru lamination thickness and and one-flop layer of about 1 0 nm by multiple layers alternating Use
  • the conductor film forming the inductor can be miniaturized, and a finer pattern, for example, Shapes with widths of 1-2 m and gaps of 1-2 m are also possible.
  • the semiconductor device of the present invention is used for devices such as MOSFET, ACCUFET, and DMOS devices mounted on electronic equipment, in particular, devices that handle high-frequency signals and power devices.

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

L'invention concerne une première région active (12) comprenant des couches dopées de type n hautement dopées (12a) alternées avec des couches non dopées (12b), et une seconde région active (13) comprenant des couches dopées de type p hautement dopées (13a) alternées avec des couches non dopées (13b), formées dans cet ordre sur un substrat SIC (10). La première région active (12) comprend une diode Schottky (20) et un transistor MOSFET p (30), et la seconde région active (13) comprend un transistor MOSFET n (40), un condensateur (50) et une bobine d'inductance (60). La diode Schottky (20) et les transistors MOSFET (30, 40) possèdent une caractéristique de tension de claquage et une caractéristique de migration de porteur attribuée à la structure multicouche de la couche dopée δ alternée et des couches non dopées et sont intégrés sur le même substrat.
PCT/JP2001/005535 2000-06-27 2001-06-27 Dispositif semi-conducteur Ceased WO2002001641A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP01943848A EP1231640A4 (fr) 2000-06-27 2001-06-27 Dispositif semi-conducteur
US10/069,654 US6674131B2 (en) 2000-06-27 2001-06-27 Semiconductor power device for high-temperature applications

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2000-192182 2000-06-27
JP2000192182 2000-06-27

Publications (1)

Publication Number Publication Date
WO2002001641A1 true WO2002001641A1 (fr) 2002-01-03

Family

ID=18691351

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2001/005535 Ceased WO2002001641A1 (fr) 2000-06-27 2001-06-27 Dispositif semi-conducteur

Country Status (3)

Country Link
US (1) US6674131B2 (fr)
EP (1) EP1231640A4 (fr)
WO (1) WO2002001641A1 (fr)

Families Citing this family (94)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW475268B (en) * 2000-05-31 2002-02-01 Matsushita Electric Industrial Co Ltd Misfet
CN1254026C (zh) * 2000-11-21 2006-04-26 松下电器产业株式会社 通信系统用仪器
TWI288435B (en) * 2000-11-21 2007-10-11 Matsushita Electric Industrial Co Ltd Semiconductor device and equipment for communication system
WO2002061842A1 (fr) * 2001-01-31 2002-08-08 Matsushita Electric Industrial Co., Ltd. Film cristallin a semi-conducteurs
KR100475122B1 (ko) * 2002-12-20 2005-03-10 삼성전자주식회사 실리콘 접촉저항을 개선할 수 있는 반도체 소자 형성방법
US7253015B2 (en) * 2004-02-17 2007-08-07 Velox Semiconductor Corporation Low doped layer for nitride-based semiconductor device
KR101205115B1 (ko) * 2004-04-27 2012-11-26 엔엑스피 비 브이 반도체 디바이스 및 그 제조 방법
US7268409B2 (en) * 2004-05-21 2007-09-11 Taiwan Semiconductor Manufacturing Company, Ltd. Spiral inductor with electrically controllable resistivity of silicon substrate layer
US7215000B2 (en) * 2004-08-23 2007-05-08 Texas Instruments Incorporated Selectively encased surface metal structures in a semiconductor device
EP1734647B1 (fr) * 2004-08-26 2008-10-22 Matsushita Electric Industrial Co., Ltd. Dispositif semi-conducteur et module utilisant celui-ci
US7247922B2 (en) * 2004-09-24 2007-07-24 Taiwan Semiconductor Manufacturing Company, Ltd. Inductor energy loss reduction techniques
JP2006100645A (ja) * 2004-09-30 2006-04-13 Furukawa Electric Co Ltd:The ＧａＮ系半導体集積回路
US7268410B1 (en) * 2005-01-24 2007-09-11 National Semiconductor Corporation Integrated switching voltage regulator using copper process technology
US20080303121A1 (en) * 2005-06-07 2008-12-11 University Of Florida Research Foundation, Inc. Integrated Electronic Circuitry and Heat Sink
US8482035B2 (en) * 2005-07-29 2013-07-09 International Rectifier Corporation Enhancement mode III-nitride transistors with single gate Dielectric structure
US8183595B2 (en) 2005-07-29 2012-05-22 International Rectifier Corporation Normally off III-nitride semiconductor device having a programmable gate
WO2007052273A2 (fr) * 2005-11-02 2007-05-10 Ben Gurion University Of The Negev Research And Development Authority Nouveau materiau et procede pour puce a ions integree
KR100854927B1 (ko) * 2006-08-29 2008-08-27 동부일렉트로닉스 주식회사 반도체 소자 및 그 제조방법
JP5061538B2 (ja) * 2006-09-01 2012-10-31 株式会社デンソー 半導体装置
JP5511124B2 (ja) * 2006-09-28 2014-06-04 セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー 絶縁ゲート型半導体装置
JP2008085188A (ja) * 2006-09-28 2008-04-10 Sanyo Electric Co Ltd 絶縁ゲート型半導体装置
US8749021B2 (en) * 2006-12-26 2014-06-10 Megit Acquisition Corp. Voltage regulator integrated with semiconductor chip
US7718513B2 (en) * 2007-04-13 2010-05-18 International Business Machines Corporation Forming silicided gate and contacts from polysilicon germanium and structure formed
US7863706B2 (en) * 2007-06-28 2011-01-04 Stats Chippac Ltd. Circuit system with circuit element
JP5298470B2 (ja) * 2007-07-11 2013-09-25 三菱電機株式会社 半導体装置、半導体装置の製造方法
US8558275B2 (en) * 2007-12-31 2013-10-15 Alpha And Omega Semiconductor Ltd Sawtooth electric field drift region structure for power semiconductor devices
JP5337470B2 (ja) * 2008-04-21 2013-11-06 セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー 絶縁ゲート型半導体装置
JP2011024094A (ja) * 2009-07-17 2011-02-03 Panasonic Corp 半導体装置、高周波回路、および高周波電力増幅装置
CN102473675B (zh) * 2009-07-22 2015-08-26 株式会社村田制作所 反熔丝元件
US20110079861A1 (en) * 2009-09-30 2011-04-07 Lucian Shifren Advanced Transistors with Threshold Voltage Set Dopant Structures
US8273617B2 (en) 2009-09-30 2012-09-25 Suvolta, Inc. Electronic devices and systems, and methods for making and using the same
US8421162B2 (en) 2009-09-30 2013-04-16 Suvolta, Inc. Advanced transistors with punch through suppression
JP2011199267A (ja) 2010-02-26 2011-10-06 Sumitomo Chemical Co Ltd 電子デバイスおよび電子デバイスの製造方法
US8530286B2 (en) 2010-04-12 2013-09-10 Suvolta, Inc. Low power semiconductor transistor structure and method of fabrication thereof
US8569128B2 (en) 2010-06-21 2013-10-29 Suvolta, Inc. Semiconductor structure and method of fabrication thereof with mixed metal types
US8759872B2 (en) 2010-06-22 2014-06-24 Suvolta, Inc. Transistor with threshold voltage set notch and method of fabrication thereof
FR2966975B1 (fr) * 2010-10-27 2013-04-12 Commissariat Energie Atomique Procede de fabrication d'un substrat muni de deux zones actives avec des materiaux semi-conducteurs differents.
US8404551B2 (en) 2010-12-03 2013-03-26 Suvolta, Inc. Source/drain extension control for advanced transistors
US8461875B1 (en) * 2011-02-18 2013-06-11 Suvolta, Inc. Digital circuits having improved transistors, and methods therefor
US8525271B2 (en) 2011-03-03 2013-09-03 Suvolta, Inc. Semiconductor structure with improved channel stack and method for fabrication thereof
US8400219B2 (en) 2011-03-24 2013-03-19 Suvolta, Inc. Analog circuits having improved transistors, and methods therefor
US8748270B1 (en) 2011-03-30 2014-06-10 Suvolta, Inc. Process for manufacturing an improved analog transistor
US8796048B1 (en) 2011-05-11 2014-08-05 Suvolta, Inc. Monitoring and measurement of thin film layers
US8999861B1 (en) 2011-05-11 2015-04-07 Suvolta, Inc. Semiconductor structure with substitutional boron and method for fabrication thereof
US8811068B1 (en) 2011-05-13 2014-08-19 Suvolta, Inc. Integrated circuit devices and methods
US8569156B1 (en) 2011-05-16 2013-10-29 Suvolta, Inc. Reducing or eliminating pre-amorphization in transistor manufacture
US8735987B1 (en) 2011-06-06 2014-05-27 Suvolta, Inc. CMOS gate stack structures and processes
US8995204B2 (en) 2011-06-23 2015-03-31 Suvolta, Inc. Circuit devices and methods having adjustable transistor body bias
US9030855B2 (en) 2011-07-14 2015-05-12 Macronix International Co., Ltd. Semiconductor device, start-up circuit having first and second circuits and a single voltage output terminal coupled to a second node between the semiconductor unit and the first circuit, and operating method for the same
CN102882363B (zh) * 2011-07-15 2015-06-17 旺宏电子股份有限公司 半导体装置、启动电路及其操作方法
US8629016B1 (en) 2011-07-26 2014-01-14 Suvolta, Inc. Multiple transistor types formed in a common epitaxial layer by differential out-diffusion from a doped underlayer
US8748986B1 (en) 2011-08-05 2014-06-10 Suvolta, Inc. Electronic device with controlled threshold voltage
KR101891373B1 (ko) 2011-08-05 2018-08-24 엠아이이 후지쯔 세미컨덕터 리미티드 핀 구조물을 갖는 반도체 디바이스 및 그 제조 방법
US9184226B2 (en) * 2011-08-15 2015-11-10 Texas Instruments Incorporated Embedded tungsten resistor
US8614128B1 (en) 2011-08-23 2013-12-24 Suvolta, Inc. CMOS structures and processes based on selective thinning
US8645878B1 (en) 2011-08-23 2014-02-04 Suvolta, Inc. Porting a circuit design from a first semiconductor process to a second semiconductor process
US8713511B1 (en) 2011-09-16 2014-04-29 Suvolta, Inc. Tools and methods for yield-aware semiconductor manufacturing process target generation
US9236466B1 (en) 2011-10-07 2016-01-12 Mie Fujitsu Semiconductor Limited Analog circuits having improved insulated gate transistors, and methods therefor
US8895327B1 (en) 2011-12-09 2014-11-25 Suvolta, Inc. Tipless transistors, short-tip transistors, and methods and circuits therefor
US8819603B1 (en) 2011-12-15 2014-08-26 Suvolta, Inc. Memory circuits and methods of making and designing the same
US8883600B1 (en) 2011-12-22 2014-11-11 Suvolta, Inc. Transistor having reduced junction leakage and methods of forming thereof
US8599623B1 (en) 2011-12-23 2013-12-03 Suvolta, Inc. Circuits and methods for measuring circuit elements in an integrated circuit device
US8970289B1 (en) 2012-01-23 2015-03-03 Suvolta, Inc. Circuits and devices for generating bi-directional body bias voltages, and methods therefor
US8877619B1 (en) 2012-01-23 2014-11-04 Suvolta, Inc. Process for manufacture of integrated circuits with different channel doping transistor architectures and devices therefrom
US9093550B1 (en) 2012-01-31 2015-07-28 Mie Fujitsu Semiconductor Limited Integrated circuits having a plurality of high-K metal gate FETs with various combinations of channel foundation structure and gate stack structure and methods of making same
US9406567B1 (en) 2012-02-28 2016-08-02 Mie Fujitsu Semiconductor Limited Method for fabricating multiple transistor devices on a substrate with varying threshold voltages
US8863064B1 (en) 2012-03-23 2014-10-14 Suvolta, Inc. SRAM cell layout structure and devices therefrom
US9299698B2 (en) 2012-06-27 2016-03-29 Mie Fujitsu Semiconductor Limited Semiconductor structure with multiple transistors having various threshold voltages
JP2014013813A (ja) * 2012-07-04 2014-01-23 Mitsubishi Electric Corp 半導体装置
KR20140013247A (ko) * 2012-07-23 2014-02-05 삼성전자주식회사 질화물계 반도체 소자 및 그의 제조 방법
US8637955B1 (en) 2012-08-31 2014-01-28 Suvolta, Inc. Semiconductor structure with reduced junction leakage and method of fabrication thereof
US9112057B1 (en) 2012-09-18 2015-08-18 Mie Fujitsu Semiconductor Limited Semiconductor devices with dopant migration suppression and method of fabrication thereof
US9041126B2 (en) 2012-09-21 2015-05-26 Mie Fujitsu Semiconductor Limited Deeply depleted MOS transistors having a screening layer and methods thereof
US9431068B2 (en) 2012-10-31 2016-08-30 Mie Fujitsu Semiconductor Limited Dynamic random access memory (DRAM) with low variation transistor peripheral circuits
US8816754B1 (en) 2012-11-02 2014-08-26 Suvolta, Inc. Body bias circuits and methods
US9093997B1 (en) 2012-11-15 2015-07-28 Mie Fujitsu Semiconductor Limited Slew based process and bias monitors and related methods
US9070477B1 (en) 2012-12-12 2015-06-30 Mie Fujitsu Semiconductor Limited Bit interleaved low voltage static random access memory (SRAM) and related methods
US9112484B1 (en) 2012-12-20 2015-08-18 Mie Fujitsu Semiconductor Limited Integrated circuit process and bias monitors and related methods
US9268885B1 (en) 2013-02-28 2016-02-23 Mie Fujitsu Semiconductor Limited Integrated circuit device methods and models with predicted device metric variations
US9299801B1 (en) 2013-03-14 2016-03-29 Mie Fujitsu Semiconductor Limited Method for fabricating a transistor device with a tuned dopant profile
US9478571B1 (en) 2013-05-24 2016-10-25 Mie Fujitsu Semiconductor Limited Buried channel deeply depleted channel transistor
JP6230455B2 (ja) 2014-03-19 2017-11-15 株式会社東芝 半導体装置
US9710006B2 (en) 2014-07-25 2017-07-18 Mie Fujitsu Semiconductor Limited Power up body bias circuits and methods
US9319013B2 (en) 2014-08-19 2016-04-19 Mie Fujitsu Semiconductor Limited Operational amplifier input offset correction with transistor threshold voltage adjustment
CN105470288B (zh) * 2015-10-14 2018-10-19 西安电子科技大学宁波信息技术研究院 Delta沟道掺杂SiC垂直功率MOS器件制作方法
US9799645B2 (en) * 2015-11-20 2017-10-24 Raytheon Company Field effect transistor (FET) structure with integrated gate connected diodes
US9698214B1 (en) * 2016-03-31 2017-07-04 Taiwan Semiconductor Manufacturing Co., Ltd. Capacitor structure of integrated circuit chip and method of fabricating the same
CN111835302B (zh) * 2019-04-18 2025-04-04 苏州能讯高能半导体有限公司 一种射频偏置电路封装结构
JP6806270B1 (ja) * 2019-06-20 2021-01-06 三菱電機株式会社 炭化ケイ素単結晶、半導体素子
WO2021019888A1 (fr) * 2019-07-29 2021-02-04 富士電機株式会社 Dispositif à semi-conducteur au carbure de silicium et procédé de fabrication d'un dispositif à semi-conducteur au carbure de silicium
CN113161349B (zh) * 2020-01-22 2023-01-31 深圳市汇芯通信技术有限公司 一种集成芯片及其制作方法和集成电路
CN113161350B (zh) * 2020-01-22 2023-01-31 深圳市汇芯通信技术有限公司 一种集成芯片及其制作方法和集成电路
CN111540712B (zh) * 2020-04-26 2024-04-16 深圳市汇芯通信技术有限公司 集成器件制造方法及相关产品
US12166033B2 (en) * 2020-11-26 2024-12-10 Innolux Corporation Electronic device

Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6127681A (ja) * 1984-07-17 1986-02-07 Res Dev Corp Of Japan 超格子構造のチヤネル部をもつ電界効果トランジスタ
JPS6242566A (ja) * 1985-08-20 1987-02-24 Fujitsu Ltd 薄膜トランジスタ
JPS6251265A (ja) * 1985-08-30 1987-03-05 Sony Corp 半導体装置
JPH02111073A (ja) * 1988-10-20 1990-04-24 Fujitsu Ltd 絶縁ゲート電界効果トランジスタおよびその集積回路装置
JPH04207040A (ja) * 1990-11-30 1992-07-29 Toshiba Corp 半導体装置
JPH04290212A (ja) * 1991-03-18 1992-10-14 Murata Mfg Co Ltd 半導体装置
JPH05160344A (ja) * 1991-12-06 1993-06-25 Mitsubishi Materials Corp 膜インダクタンス及びその製造方法
JPH06275786A (ja) * 1993-03-23 1994-09-30 Sony Corp 相補形化合物半導体装置及びその作製方法
JPH08195287A (ja) * 1995-01-18 1996-07-30 Matsushita Electric Ind Co Ltd 蛍光ランプ点灯装置
JPH08222695A (ja) * 1995-02-13 1996-08-30 Hitachi Ltd インダクタ素子及びその製造方法
JPH09246471A (ja) * 1996-03-07 1997-09-19 Matsushita Electric Ind Co Ltd 高周波半導体装置および高周波通信機器
JPH1092947A (ja) * 1996-09-17 1998-04-10 Toshiba Corp 半導体装置及びその製造方法
JPH10289979A (ja) * 1997-04-15 1998-10-27 Nippon Steel Corp 高周波半導体デバイス

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4882609A (en) * 1984-11-19 1989-11-21 Max-Planck Gesellschaft Zur Forderung Der Wissenschafter E.V. Semiconductor devices with at least one monoatomic layer of doping atoms
US5488237A (en) 1992-02-14 1996-01-30 Sumitomo Electric Industries, Ltd. Semiconductor device with delta-doped layer in channel region
US5493136A (en) * 1993-02-22 1996-02-20 Sumitomo Electric Industries, Ltd. Field effect transistor and method of manufacturing the same
US5572040A (en) * 1993-07-12 1996-11-05 Peregrine Semiconductor Corporation High-frequency wireless communication system on a single ultrathin silicon on sapphire chip
DE69522075T2 (de) * 1994-11-02 2002-01-03 Trw Inc., Redondo Beach Verfahren zum Herstellen von multifunktionellen, monolithisch-integrierten Schaltungsanordnungen
JP3461274B2 (ja) * 1996-10-16 2003-10-27 株式会社東芝 半導体装置
US5929467A (en) * 1996-12-04 1999-07-27 Sony Corporation Field effect transistor with nitride compound
US6380569B1 (en) * 1999-08-10 2002-04-30 Rockwell Science Center, Llc High power unipolar FET switch

Patent Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6127681A (ja) * 1984-07-17 1986-02-07 Res Dev Corp Of Japan 超格子構造のチヤネル部をもつ電界効果トランジスタ
JPS6242566A (ja) * 1985-08-20 1987-02-24 Fujitsu Ltd 薄膜トランジスタ
JPS6251265A (ja) * 1985-08-30 1987-03-05 Sony Corp 半導体装置
JPH02111073A (ja) * 1988-10-20 1990-04-24 Fujitsu Ltd 絶縁ゲート電界効果トランジスタおよびその集積回路装置
JPH04207040A (ja) * 1990-11-30 1992-07-29 Toshiba Corp 半導体装置
JPH04290212A (ja) * 1991-03-18 1992-10-14 Murata Mfg Co Ltd 半導体装置
JPH05160344A (ja) * 1991-12-06 1993-06-25 Mitsubishi Materials Corp 膜インダクタンス及びその製造方法
JPH06275786A (ja) * 1993-03-23 1994-09-30 Sony Corp 相補形化合物半導体装置及びその作製方法
JPH08195287A (ja) * 1995-01-18 1996-07-30 Matsushita Electric Ind Co Ltd 蛍光ランプ点灯装置
JPH08222695A (ja) * 1995-02-13 1996-08-30 Hitachi Ltd インダクタ素子及びその製造方法
JPH09246471A (ja) * 1996-03-07 1997-09-19 Matsushita Electric Ind Co Ltd 高周波半導体装置および高周波通信機器
JPH1092947A (ja) * 1996-09-17 1998-04-10 Toshiba Corp 半導体装置及びその製造方法
JPH10289979A (ja) * 1997-04-15 1998-10-27 Nippon Steel Corp 高周波半導体デバイス

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP1231640A4 *

Also Published As

Publication number Publication date
US6674131B2 (en) 2004-01-06
EP1231640A4 (fr) 2008-10-08
EP1231640A1 (fr) 2002-08-14
US20030006415A1 (en) 2003-01-09

Similar Documents

Publication Publication Date Title
WO2002001641A1 (fr) Dispositif semi-conducteur
JP3527503B2 (ja) 半導体装置
JP4122880B2 (ja) 縦型接合型電界効果トランジスタ
JP4463482B2 (ja) Ｍｉｓｆｅｔ及びその製造方法
CN102449768B (zh) 形成包括外延层和相关结构的半导体器件的方法
JP7537483B2 (ja) 半導体装置
TWI329927B (en) Unit cell of a metal-semiconductor field-effect transistor and method of forming the same
US8658503B2 (en) Semiconductor device and method of fabricating the same
CN1254026C (zh) 通信系统用仪器
TWI390637B (zh) 具混合井區之碳化矽裝置及用以製造該等碳化矽裝置之方法
JP3502371B2 (ja) 半導体素子
JP2005507174A (ja) デルタドープされた炭化シリコン金属半導体電界効果トランジスタおよびその製造方法
WO2006098341A1 (fr) Transistor a effet de champ et son dispositif
JP4224423B2 (ja) 半導体装置およびその製造方法
US20160254393A1 (en) Silicon carbide semiconductor device and method of manufacturing silicon carbide semiconductor device
JP2002093920A (ja) 半導体デバイス
JP2006114795A (ja) 半導体装置
JP4937498B2 (ja) 半導体デバイス
JP2007048783A (ja) ショットキーダイオード及びその製造方法
JP2008098674A (ja) 半導体装置
JP4045893B2 (ja) 縦型接合型電界効果トランジスタ
CN116368624B (zh) 半导体装置及其制造方法
CN116646399A (zh) 一种沟槽栅半导体器件及其制备方法

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): US

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR

WWE Wipo information: entry into national phase

Ref document number: 10069654

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application
WWE Wipo information: entry into national phase

Ref document number: 2001943848

Country of ref document: EP

WWP Wipo information: published in national office

Ref document number: 2001943848

Country of ref document: EP