WO2002001569A1 - Memory control device and memory control method - Google Patents

Abstract

A memory control device is operated with a reduced power consumption by interrupting the clock after the mode of the memory is changed at a proper timing to a self-refresh mode. The memory control device comprises an arbitrating circuit (143) for managing an access to the data of the memory, a timer circuit (144), a timer setting circuit (145), and a command control circuit (142) for outputting a control signal for changing the mode of the memory to the self-refresh mode or canceling the refresh mode. The command control circuit (142) outputs a control signal according to the management of an access to data by the arbitrating circuit (143), the timer circuit (144), and the timer setting circuit (145).

Description

 Description Memory control device, memory control method

 The present invention relates to a memory control device and a memory control method.

In particular, the present invention relates to a device having a feature of reducing power consumption during a period in which there is no memory access request from a block using a DRAM to a DRAM. Background art

A conventional memory control device will be described with reference to FIG. In FIG. 2, reference numeral 21 denotes a DRAM used as a means for recording data. Reference numeral 25 denotes a clock generator for supplying a clock signal to the DRAM 21. Reference numeral 26 denotes a CPU which outputs a control signal for causing the DRAM 21 to shift to self-refresh, issues a clock stop instruction to the clock generator 25, and issues a control instruction to the entire system. The CPU 26 performs memory access to the DRAM 21. Reference numeral 24 denotes a memory control device that arbitrates memory access to the DRAM 21 from each block that accesses the DRAM 21 and controls the DRAM 21. The memory controller 24 outputs a control signal to the DRAM according to a control command from the CPU. Reference numeral 27 denotes a block for performing data access to the DRAM 21 via the memory control device 24. -The operation of the conventional memory control device having the above configuration will be described below. The DRAM 21 needs to periodically refresh the recorded data in order to keep the recorded data. As a method of refreshing, there are a method of refreshing from outside the DRAM 21 and a method of automatically refreshing inside the DRAM 21. The self refresh mode is a mode in which refresh is automatically performed inside the DRAM 21, and is characterized by lower power consumption than a method in which refresh is performed from outside the DRAM 21. Therefore, when the DRAM 21 is used, if the DRAM 21 is shifted to the self-refresh mode for as long as possible, the effect of reducing the power consumption is increased.

 Conventionally, the transition of the DRAM 21 to the self-refresh mode is performed by receiving a control command from the external CPU 26 or another device as a trigger and causing the memory controller 24 to issue a control signal for causing the DRAM 21 to shift to the self-refresh mode. This is done by outputting. After shifting the DRAM 21 to the self-refresh mode, the CPU 26 may issue a stop command to the clock generator 25 in order to stop the unnecessary signal for the DRAM 21. I have to.

By the way, in order for the self-refresh mode to be executed, it is indispensable that the DRAM 21 is not accessed, but the memory controller 24 receives a control command from the CPU 26 or an external trigger. When the DRAM is shifted to the self-refresh mode, the state of memory access to the DRAM 21 from the block 27 using the DRAM 21 cannot be directly known. For example, when the CPU 26 issues a control instruction and shifts the DRAM 21 to the self-refresh mode, the CPU 26 disables access to the block 27 that attempts to access the memory control device 24 and then issues a control instruction. Although this method allows memory access for blocks, it actually Even if no access is performed, the DRAM 21 cannot be shifted to the self-refresh mode.

 As described above, in the conventional memory control device, the DRAM cannot accurately shift to the self-refresh mode during the period in which there is no memory access to the DRAM 21.

 Also, since the clock control of the DRAM is performed by the CPU 26, when the DRAM 21 shifts to the self-refresh mode, the clock stop is delayed after the DRAM shifts to the self-refresh mode. It causes a time lag.

 As described above, in the conventional memory control device, it is not possible to shift to the self-refresh mode at an accurate timing according to the access status to the DRAM and to stop the clock at the exact timing. There has been a problem that power consumption has not been sufficiently reduced. Disclosure of the invention

 The present invention has been made to solve the above-mentioned problem, and the power consumption can be sufficiently reduced by shifting to a self-refresh mode at an appropriate timing and stopping a clock at an appropriate timing. It is an object of the present invention to provide a memory control device and a memory control method that can be performed. .

 To achieve the above object, a first aspect of the present invention (corresponding to claim 1) includes: a management unit for managing data access to a memory;

A command control circuit for outputting a control signal for shifting the memory to the self-refresh mode or canceling the self-refresh mode. The memory control device, wherein the command control circuit outputs the control signal based on management of data access by the management unit.

 According to a second aspect of the present invention (corresponding to claim 2), the management means has a timer circuit for performing counting,

 The present invention is characterized in that the command control means outputs the control signal when the data access to the memory is not performed for a predetermined period, and shifts the memory to a self-refresh mode. A third aspect of the present invention (corresponding to claim 3) is that the management means has a timer setting circuit for setting the period for performing the counting for the timer circuit. It is.

 In a fourth aspect of the present invention (corresponding to claim 4), the management means selectively accesses a specific one of data from a plurality of data accesses to the memory. This is the invention.

 A fifth aspect of the present invention (corresponding to claim 5) is the above-mentioned aspect of the present invention in which the selection is performed based on a priority assigned in advance to access to the plurality of data.

 A sixth invention (corresponding to claim 6) is a clock control circuit that outputs a clock signal to the memory.

 A memory control device characterized by at least comprising a command control circuit for receiving a control from the outside and causing a memory to transition to a self-refresh mode or outputting a control signal for releasing the self-refresh mode. is there.

In a seventh aspect of the present invention (corresponding to claim 7), the clock control circuit stops outputting a quick signal to the memory while the memory is in a self-refresh mode. The present invention described above. An eighth aspect of the present invention (corresponding to claim 8) is that the clock control circuit controls the output of a clock signal to the memory based on the external control. is there.

 A ninth aspect of the present invention (corresponding to claim 9) is that, when the memory receives a signal requesting data access to the memory during the self-refresh mode,

 The clock control circuit restarts output of the memory to the memory, and the command control circuit outputs the control signal for releasing the self-refresh mode of the memory. is there.

 A tenth aspect of the present invention (corresponding to claim 10) includes a management step of managing data access to a memory;

 A command control step of outputting a control signal for shifting the memory to the self-refresh mode or canceling the self-refresh mode.

 In the command control step, the control signal is output based on management of data access in the management step. '

 The eleventh invention (corresponding to claim 11) includes a clock control step of outputting a clock signal to a memory;

 A command control step of receiving a control from the outside and causing the memory to transition to the self-refresh mode or outputting a control signal for releasing the self-refresh mode. is there.

According to a twelfth invention (corresponding to claim 12), there is provided a memory control device according to the first invention, comprising: a management unit for managing data access to the memory; To transition to or self This is a program for causing a computer to function as all or part of a command control circuit that outputs a control signal for releasing the refresh mode.

 According to a thirteenth aspect of the present invention (corresponding to claim 13), the memory control device according to the sixth aspect of the present invention includes a clock control circuit that outputs a clock signal to a memory; It is a program for causing a computer to function as a whole or a part of a command control circuit that outputs a control signal for shifting the memory to a self-refresh mode or outputting a control signal for canceling the self-refresh mode.

 A fourteenth aspect of the present invention (corresponding to claim 14) is a memory control method according to the first aspect, wherein: a managing step of managing data access to the memory; This is a program for causing a computer to execute all or a part of a command control process for outputting a control signal for shifting or for releasing a self-refresh mode.

 A fifteenth aspect of the present invention (corresponding to claim 15) includes a clock control step of outputting a clock signal to a memory in the memory control method of the sixth aspect of the present invention

 A command control step of receiving a control from the outside and shifting the memory to the self-refresh mode, or outputting a control signal for canceling the self-refresh mode, and causing the computer to execute all or a part of the command control step. It is a program.

A sixteenth aspect of the present invention (corresponding to claim 16) is a memory control device according to the first aspect of the present invention, comprising: a management unit for managing data access to the memory; Command control to output a control signal to shift to the mode or cancel the self-refresh mode A medium that carries a program for causing a computer to function as all or part of a circuit, and is a medium characterized by being processable by a computer.

 The seventeenth invention (corresponding to claim 17) is a memory control device according to the sixth invention, wherein the clock control circuit outputs a clock signal to the memory; A medium carrying a program for causing a computer to function as a whole or a part of a command control circuit for outputting a control signal for shifting the memory to a self-refresh mode or for releasing a self-refresh mode. A medium that can be processed by a computer.

 An eighteenth aspect of the present invention (corresponding to claim 18) is a memory control method according to the first aspect of the present invention, wherein: a managing step of managing data access to the memory; A command that outputs a control signal for shifting or releasing the self-refresh mode. A medium carrying a program for causing a computer to execute all or part of a command control process, and can be processed by the computer. It is a medium characterized by this.

 A nineteenth aspect of the present invention (corresponding to claim 19) is a clock control step of outputting a clock signal to a memory according to the memory control method of the sixth aspect of the present invention.

 A program for causing a computer to execute all or part of a command control step of receiving a control from the outside and shifting the memory to a self-refresh mode or outputting a control signal for releasing the self-refresh mode The medium is characterized by being capable of being processed by a computer.

The memory control device of the present invention as described above, for example, An arbitration circuit for arbitrating a reaccess request; and a command control circuit for outputting a control signal to the DRAM, wherein when the memory access request signal from the block using the DRAM to the DRAM does not exist for a predetermined period, the DRAM is controlled. The mode is characterized in that power consumption is reduced by shifting to a self-refresh mode, and a clock control circuit for controlling a clock to the DRAM is provided in the memory control device, and the DRAM is self-refreshed. The power consumption is reduced by stopping the docking of the DRAM during the mode period.

 According to this, the memory (DRAM) is always self-refreshed when the memory access has not been performed for a predetermined period of time, regardless of whether the memory access is permitted to the external block or not. Mode.

 Also, it is possible to provide a memory control device that reduces power consumption during a period when there is no memory access to a memory (DRAM). BRIEF DESCRIPTION OF THE FIGURES

 FIG. 1 is a configuration diagram of a memory control device according to an embodiment of the present invention. FIG. 2 is a configuration diagram of a memory control device according to a conventional technique.

 FIG. 3 is a diagram for explaining another example of the control means of the present invention. Explanation of reference numerals

 1 1 DRAM

 1 2 B 1 o c k A

 1 3 B 1 o c k B

14 Memory controller 1 5 Clock generator

 1 6, 26 CPU

 21 DRAM

 24 Memory controller

 25 Clock generator

 141 Clock control circuit

 142 Command control circuit

 143 Arbitration circuit

 144 timer circuit

 145 Timer Setting Circuit BEST MODE FOR CARRYING OUT THE INVENTION

 (Embodiment)

 Hereinafter, a memory control device according to an embodiment of the present invention will be described with reference to FIG.

In FIG. 1, reference numeral 11 denotes a DRAM used as a means for recording data. Reference numeral 12 denotes BlocA which outputs a memory access request signal A for accessing the DRAM 11. Reference numeral 13 denotes B 1 ock B which outputs a memory access request signal B for accessing the DRAM 11. Reference numeral 14 denotes a memory control device that controls a memory access request signal from the Bloc kA12, Bloc kB13, and CPU 16 to the DRAM 1 and controls a clock signal from the clock generation device to the DRAM 11 c Reference numeral 15 denotes a clock generator for generating a clock signal. Reference numeral 16 denotes a GPU which outputs a memory access request signal C for accessing the DRA Ml 1 and issues a control instruction to the entire system. In the memory control device 14, reference numeral 141 denotes a clock control circuit that supplies or stops a clock signal output from the clock generation device 15 to the DRAI 1 in response to a clock stop request signal from the command control circuit 142. The instruction 142 controls the memory access from the block to which the memory access is granted by the instruction from the CPU to the DRAM 11 and the arbitration circuit, and the DRAM 11 responds to the self-refresh request signal from the timer circuit 144. A command control circuit that outputs a clock stop request signal to stop the quick signal to DRAMI1 after issuing a self-refresh command. 143 arbitrates Bloc kA12, Bloc kB13, and a memory access request signal from CPU 16 to DRAM 11 based on a predetermined priority, and has a block with a higher priority memory access request. Arbitration circuit that outputs a memory access permission signal to 144 sets the initial value T1 to the value set by the timer setting circuit 145, counts down at regular intervals TD, resets to the initial value when a timer reset signal is input, and requests a self-refresh when the value becomes 0. This is a timer circuit that outputs a signal. Reference numeral 145 denotes a timer setting circuit for setting an initial value of the timer circuit 144.

The operation of the memory control device having the above-described configuration according to the embodiment of the present invention will be described below, and an embodiment of the memory control method of the present invention will be described. The BlockA 12, the Bock B 13, and the CPU 16 output a memory access request signal to the memory controller 14 when accessing the DRAM 11. At this time, since the memory access to the DRAM 11 cannot be performed from a plurality of devices at the same time, the arbitration circuit 143 in the memory control device 14 selects the memory access request signals A, B, and C from among Predetermined A predetermined memory access request signal is selected based on the given priority. For example, if the priority of the memory access request signal to be accepted is determined in advance as in the following equation (1), and the memory access request signals A, B, and C are simultaneously input to the memory controller 14, the arbitration circuit 143 selects the memory access request signal A. When the memory access request signals B and C are simultaneously input to the memory control device 14, the arbitration circuit 143 selects the memory access request signal C.

 (Number 1)

 Memory access request signal A> Memory access request signal C> Memory access request signal B '

 ">" Indicates that the left side has a higher priority than the right side. (1) The arbitration circuit 143 outputs a memory access permission signal for notifying the block selected by the above arbitration operation of memory access permission. Power. For example, when the memory access request A is selected by arbitration of the arbitration circuit 143, the arbitration circuit 143 outputs a memory access permission signal A to B1OckA12.

 Similarly, when the arbitration circuit 143 selects the memory access request signal B, the arbitration circuit 143 outputs a memory access permission signal B to BlockBl3, and further, the arbitration circuit 143 selects the memory access request signal C. In this case, the arbitration circuit 143 outputs the memory access permission signal C to the CPU 16.

Next, the arbitration circuit 143 outputs the memory access permission signal A, B or C, and simultaneously outputs the timer reset signal generated by the logical sum of the memory access permission signals A, B and C to the timer circuit 144. . (Equation (2)). (Equation 2)

 Timer reset signal = memory access permission signal A I memory access permission signal B I memory access permission signal C

 "I" indicates logical sum (2)

 This timer reset signal indicates that the memory access has been permitted to one of BlocCkA12, B10ckB13, and CPU16.

 Subsequently, the CPU 16 gives the value of the initial value of the timer circuit 144 to the timer setting circuit 145, and the timer setting circuit 145 sets the value given from the CPU 16 as the initial value T1 in the timer circuit 144. . The timer circuit 144 is initialized to an initial value T1 by a timer reset signal, and is counted down at regular intervals TD. Assuming that the time indicated by the timer circuit 144 is TT, TT is expressed by the following equation (3). In equation (3), N is a natural number.

 (Equation 3)

 TT = T 1-TDXN (3)

 When ΤΤ in the timer circuit 144 becomes 0, it indicates that the time T1 has elapsed since the last memory access, and the timer circuit 144 outputs a self-refresh request signal to the command control circuit 42.

When the self-refresh request signal from the timer circuit 144 is input to the command control circuit 142, the command control circuit 142 issues a self-refresh command, which is one of the control signals, to the DRAM 11 _c. Since the clock signal is not required during the self-refresh mode, the command control circuit 142 sends a clock control signal to the clock control circuit 141 to stop the clock signal to the DRAM 11. Outputs a certain clock stop request signal. clock The control circuit 141 is a means for controlling whether or not the clock signal input from the clock generator 15 is output to the DRAM 11 or not, and when a clock stop request signal is input from the command control circuit 142, Stop outputting the clock signal to DA RM11.

 Next, while the DRAM 11 is in the self-refresh mode, the command control circuit 142 outputs a self-refresh mode enable signal to the arbitration circuit 143. In the arbitration circuit 143, when the memory access request signal is input to the DRAM 11 when the self-refresh mode enable signal is input, the arbitration circuit 143 performs the self-refresh mode of the DRAM 11 A self-refresh release signal is output to the command control circuit 142 in order to release the command.

 When the self-refresh release signal from the arbitration circuit 143 is input to the command control circuit 142, the command control circuit 142 restarts the quick signal supply to the DRAM 11 so that the command control circuit 142 To output a clock stop release signal, and then output a control signal for self-refresh release to DRAM 11.

 Subsequently, after the self-refresh mode of the DRAM 11 is released, the command control circuit 142 disables the self-refresh mode enable signal and stops transmitting the signal. When receiving the clock stop release signal from the command control circuit 142, the clock control circuit 141 restarts the supply of the clock signal from the clock generation circuit 15 to the DRAM 11.

 Next, an operation when the DRAM 11 is shifted to the self-refresh mode under the control of the CPU 16 will be described.

When shifting the DRAM 11 from the CPU 16 to the self-refresh mode, the CPU 16 and the command control circuit 142 receive one of the control instructions. Is output. When receiving the self-refresh command, the command control circuit 142 issues a self-refresh command, which is one of control signals, to the DRAM 11.

 Next, when releasing the self-refresh mode of the DRAM 11 from the CPU 16, the CPU 16 outputs a self-refresh release instruction which is one of control instructions to the command control circuit 142. When receiving the input of the self-refresh release command, the command control circuit 142 outputs a self-refresh release command, which is one of the control signals, to the DRAM 11.

 On the other hand, when using the CPU 16 to stop outputting the clock signal to the DRAM 11, the CPU 16 outputs a clock stop instruction, which is one of the control instructions, to the clock control circuit 141. Upon receiving the clock stop command, the clock control circuit 141 stops outputting the clock signal to the DRAM 11.

 Then, when releasing the suspension of the clock signal to the DRAM 11 using the CPU 16, the CPU 16 outputs to the clock control circuit 141 a clock suspension release instruction which is one of the control instructions. When receiving the clock stop release instruction, the clock control circuit 141 releases the stop of the clock signal to the DRAM 11 and outputs the clock signal from the clock generator 15 to the DRAM 11.

As described above, according to the present embodiment, by providing the arbitration circuit 143, the timer circuit 144, the command control circuit 142, the clock control circuit 141, and the timer setting circuit 145 in the memory control device 14, the memory control The device 14 shifts the DRAM 11 to the Senoref refresh mode at an appropriate timing when there is no memory access to the DRAM 11 for a certain period of time, and is also indispensable when the DRAM 11 is in the self-refresh mode. The necessary click signal can be stopped.

 In the embodiment, the memory according to the present invention is described as a DRAM. However, the present invention is not limited to this. Other examples include an SDRAM (Synchronous DRAM) and an SGRAM (Synchronous GSM). A memory such as a raphic RAM) may be used. That is, any type of memory that performs self-refresh may be used in the present invention.

 Further, in the embodiments, the timer circuit 144, the timer setting circuit 145, and the arbitration circuit 143 have been described as an example of the management unit of the present invention. You may. For example, each block is provided with a level signal that indicates the presence or absence of memory access, and the memory access is managed by using a level signal management unit that manages the level signal as the management unit of the present invention. You may do so. That is, as shown in FIG. 3, the level signal indicating whether or not each block has a memory access state is set to High when no memory access is performed and Low when performed. The level signal management means generates a trigger signal A by taking the logical product of the level signals from the respective blocks of B1lockA and B1lockB. The effect of the present invention can be obtained even if the level signal management means detects a rise of the trigger signal A, outputs a self-refresh request signal, detects a fall, and outputs a self-refresh release signal. .

In the present embodiment, the memory control device has been described as including the clock control circuit 141, the command control circuit 142, the arbitration circuit 143, the timer circuit 144, and the timer setting circuit 145. The present invention provides a configuration including only the clock control circuit 141 and the command control circuit 142, or a clock control circuit 141, an arbitration circuit 143, and a timer. It may be realized as a configuration including only one circuit 144 and the timer setting circuit 144. Of these configurations, the former is specialized in the function of controlling the output of the clock signal to the memory in the senor refresh mode in order to stop the clock at the correct timing. In the case of, in order to realize the transition to the self-refresh mode at the appropriate timing according to the access status to the memory, the refresh mode control operation is performed when the memory has multiple data accesses from outside. Specialized in function.

 Further, in the present embodiment, the selection of the arbitration circuit 144 for the memory access request signal from the block A 12, the block B 13, and the CPU 16 is based on a predetermined priority. However, the priority may be variable or the number of blocks that issue a memory access request may be one. .

 In the above description, the memory control device according to the embodiment of the present invention has been described. However, the present invention relates to all or a part of the memory control device of the present invention described above (or the device). , Elements, circuits, units, and the like) by a computer, and may be a program that operates in cooperation with the computer.

 Further, the present invention is a medium carrying a program for causing a computer to execute all or a part of the operations of all or some of the steps of the memory control method of the present invention described above. The read program may be a medium that executes the above-described operation in cooperation with the computer.

Further, the present invention is a medium carrying a program for causing a computer to execute all or a part of the functions of all or a part of the memory control device of the present invention, and is readable by a computer. The read program is a medium that executes the function in cooperation with the computer.

 Further, the present invention is a medium carrying a program for causing a computer to execute all or a part of the operations of all or some of the steps of the memory control method of the present invention described above. The read program is a medium that executes the above operation in cooperation with the computer.

 Note that some means (or devices, elements, circuits, units, and the like) of the present invention, and some steps (or steps, operations, functions, and the like) of the present invention are defined as a plurality of these means or steps. Means some means or steps, or means some functions or some operations within one third means or steps. -A computer-readable recording medium on which the program of the present invention is recorded is also included in the present invention.

 One use form of the program of the present invention may be a form in which the program is recorded on a computer-readable recording medium and operates in cooperation with the computer.

 One use form of the program of the present invention is a form that is transmitted through a transmission medium, read by a computer, and operates in cooperation with a computer.

 Further, the data structure of the present invention includes a database, a data format, a data table, a data list, a data type, and the like.

 The recording medium includes ROM and the like, and the transmission medium includes transmission media such as the Internet, light, radio waves, and sound waves.

Further, the above-described computer of the present invention is not limited to pure hardware such as a CPU, but also includes firmware, an OS, and peripheral devices. There may be.

 As described above, the configuration of the present invention may be realized by software or hardware. Industrial applicability

 As described above, according to the memory control device of the present invention, the memory is shifted to the self-refresh mode at an appropriate timing while the memory is not accessed, and the clock signal to the memory during the self-refresh mode is By stopping the operation, it is possible to provide a memory control device that reduces power consumption.

Claims

The scope of the claims 1. Management means for managing data access to the memory;  A command control circuit that outputs a control signal for shifting the memory to a self-refresh mode or canceling a self-refresh mode,  The memory control device, wherein the command control circuit outputs the control signal based on management of data access by the management unit.  2. The management unit has a timer circuit for counting, and the command control unit outputs the control signal when data access to the memory is not performed for a predetermined period. 2. The memory control device according to claim 1, wherein the memory is shifted to a self-refresh mode.  3. The memory control device according to claim 2, wherein the management unit includes a timer setting circuit for setting a period for performing the counting for the timer circuit.  4. The memory control device according to any one of claims 1 to 3, wherein the management unit selectively accesses a specific one of data from a plurality of data accesses to the memory.  5. The memory control device according to claim 4, wherein the selection is performed based on a priority assigned to the plurality of data accesses in advance. 6. A quick control circuit for outputting a quick signal to the memory, and a control signal for accepting control from the outside and shifting the memory to the self-refresh mode or canceling the self-refresh mode And a command control circuit for outputting a command. Memory control device.  7. The memory control device according to claim 6, wherein the clock control circuit stops outputting a clock signal to the memory while the memory is in a self-refresh mode.  8. The memory control device according to claim 7, wherein the clock control circuit controls output of a clock signal to the memory based on the external control.  9. If the memory receives a signal requesting data access to the memory during the self-refresh mode,  7. The method according to claim 6, wherein the control circuit restarts outputting a clock to the memory, and the command control circuit outputs the control signal for canceling a self-refresh mode of the memory. Memory control device as described.  10. At least comprising: a management step of managing data access to a memory; and a command control step of outputting a control signal for shifting the memory to a self-refresh mode or canceling a self-refresh mode.  In the command control step, the control signal is output based on management of data access in the management step.  1 1. A clock control process that outputs a clock signal to the memory, and a control signal that receives control from the outside and shifts the memory to the self-refresh mode or releases the self-refresh mode A memory control method characterized by at least comprising a command control step of: 1 2. Data memory for the memory of the memory controller according to claim 1. And a command control circuit for outputting a control signal for shifting the memory to the self-refresh mode or for releasing the self-refresh mode, and causing the computer to function as all or a part of the command control circuit. program.  13. The memory control device according to claim 6, further comprising: a clock control circuit that outputs a clock signal to the memory; and a control unit that receives control from the outside and shifts the memory to a self-refresh mode or a self-refresh mode. A program that causes a computer to function as all or part of a command control circuit that outputs a control signal for release.  14. The memory control method according to claim 1, wherein a management step of managing data access to the memory;  A program for causing a computer to execute all or a part of a command control process for outputting a control signal for shifting the memory to a self-refresh mode or for releasing a self-refresh mode.  15. The clock control step of outputting a clock signal to the memory according to the memory control method according to claim 6,  A program for causing a computer to execute all or part of a command control step of receiving a control from the outside and shifting the memory to a self-refresh mode or outputting a control signal for releasing the self-refresh mode . 16. The memory control device according to claim 1, further comprising: a management unit configured to manage data access to the memory; and a control signal configured to shift the memory to a self-refresh mode or to cancel the self-refresh mode. As a part or all of the command control circuit that outputs A medium carrying a program for causing a user to function, the medium being capable of being processed by a computer.  17. The memory control device according to claim 6, further comprising: a clock control circuit that outputs a clock signal to the memory; and a control unit that receives control from the outside to shift the memory to a self-refresh mode, or a self-refresh mode. A medium carrying a program for causing a computer to function as all or a part of a command control circuit that outputs a control signal for canceling, the medium being characterized by being processable by a computer.  18. The memory control method according to claim 1, wherein: a management step of managing data access to the memory;  A medium carrying a program for causing a computer to execute all or a part of a command control step for outputting a control signal for shifting the memory to a self-refresh mode or for releasing a self-refresh mode. Media that can be processed by computers.  19. The memory control method according to claim 6, wherein a clock control step of outputting a clock signal to the memory;  A program for causing a computer to execute all or part of a command control step of receiving a control from the outside and shifting the memory to a self-refresh mode or outputting a control signal for releasing the self-refresh mode A medium which carries thereon, and which can be processed by a computer.