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WO2002075793B1 - System and method of providing mask defect printability analysis - Google Patents

System and method of providing mask defect printability analysis

Info

Publication number
WO2002075793B1
WO2002075793B1 PCT/US2002/006491 US0206491W WO02075793B1 WO 2002075793 B1 WO2002075793 B1 WO 2002075793B1 US 0206491 W US0206491 W US 0206491W WO 02075793 B1 WO02075793 B1 WO 02075793B1
Authority
WO
WIPO (PCT)
Prior art keywords
mask
defect
critical dimension
physical
image
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2002/006491
Other languages
French (fr)
Other versions
WO2002075793A3 (en
WO2002075793A2 (en
Inventor
Lynn Cai
Linard Karklin
Linyong Pang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Numerical Technologies Inc
Original Assignee
Numerical Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/814,025 external-priority patent/US6925202B2/en
Priority claimed from US09/814,023 external-priority patent/US6873720B2/en
Application filed by Numerical Technologies Inc filed Critical Numerical Technologies Inc
Priority to KR1020037012260A priority Critical patent/KR100610441B1/en
Priority to JP2002574111A priority patent/JP4663214B2/en
Priority to AU2002245560A priority patent/AU2002245560A1/en
Publication of WO2002075793A2 publication Critical patent/WO2002075793A2/en
Publication of WO2002075793A3 publication Critical patent/WO2002075793A3/en
Anticipated expiration legal-status Critical
Publication of WO2002075793B1 publication Critical patent/WO2002075793B1/en
Ceased legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/68Preparation processes not covered by groups G03F1/20 - G03F1/50
    • G03F1/82Auxiliary processes, e.g. cleaning or inspecting
    • G03F1/84Inspecting
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01NINVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N21/00Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
    • G01N21/84Systems specially adapted for particular applications
    • G01N21/88Investigating the presence of flaws or contamination
    • G01N21/95Investigating the presence of flaws or contamination characterised by the material or shape of the object to be examined
    • G01N21/956Inspecting patterns on the surface of objects
    • G01N21/95607Inspecting patterns on the surface of objects using a comparative method
    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70433Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70491Information management, e.g. software; Active and passive control, e.g. details of controlling exposure processes or exposure tool monitoring processes
    • G03F7/705Modelling or simulating from physical phenomena up to complete wafer processes or whole workflow in wafer productions

Landscapes

  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Immunology (AREA)
  • Health & Medical Sciences (AREA)
  • Biochemistry (AREA)
  • General Health & Medical Sciences (AREA)
  • Chemical & Material Sciences (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Pathology (AREA)
  • Analytical Chemistry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Investigating Materials By The Use Of Optical Means Adapted For Particular Applications (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

A simulated wafer image of a physical mask and a defect-free reference image are used to generate a severity score for each defect, thereby giving a customer meaningful information to accurately assess the consequences of using a mask or repairing that mask. The defect severity score is calculated based on a number of factors relating to the changes in critical dimensions of the neighbor features to the defect. A common process window can also be used to provide objective information regarding defect printability. Certain other aspects of the mask relating to mask quality, such as line edge roughness and contact corner rounding, can also be quantified by using the simulated wafer image of the physical mask.

Claims

AMENDED CLAIMS[Received by the International Bureau on 26.March.2003 (26.03.03 ): original claims 1-58 replaced by amended claims 1-70 (16 pages) ]REPLACEMENT PAGESCLAIMS :We claim:
1. A method of providing printability analysis for a defect on a physical mask, the method comprising: generating a simulated wafer image of the physical mask; generating a simulated wafer image of a reference mask, the reference mask corresponding to a defect-free physical mask; identifying a first feature proximate to the defect on the simulated wafer image of the physical mask; identifying a second feature on the simulated wafer image of the reference mask, the second feature corresponding to the first feature; and computing critical dimension deviations including the first and second features to provide the printability analysis .
2. The method of Claim 1, wherein computing includes determining a first critical dimension of the first feature and a second critical- dimension of the second feature.
3. The method of Claim 2, wherein computing includes calculating a relative critical dimension deviation for the first and second features.
4. The method of Claim 3, wherein calculating the relative critical dimension deviation includes subtracting the second critical dimension from the first critical dimension, and dividing a resulting value by the second critical dimension.
5. The method of Claim 3, further including:
68 identifying a first plurality of features proximate to the defect on the simulated wafer image of the physical mask; identifying a second plurality of features on the simulated wafer image of the reference mask, the second plurality of features corresponding to the first plurality of features; and calculating a plurality of relative critical dimension deviations for the first and second plurality of features.
6. The method of Claim 5, further including determining the largest of the plurality of relative critical dimension deviations, thereby providing a maximum critical dimension deviation.
7. The method of Claim 1, further including: identifying a third defect-free feature on the simulated wafer image of the physical mask; identifying a fourth feature on the simulated wafer image of the reference mask, the fourth feature corresponding to the third feature; and computing critical dimension deviations including the third and fourth features.
8. The method of Claim 7, wherein computing the third and fourth features includes determining a first critical dimension of the third feature and a second critical dimension of the fourth feature.
9. The method of Claim 8, wherein computing includes calculating a critical dimension deviation for the first and second features .
10. The method of Claim 9, wherein calculating the critical dimension deviation includes subtracting the first
69 critical dimension from the second critical dimension, and dividing a resulting value by the second critical dimension.
11. The method of Claim 9, further including calculating the critical dimension deviation for N defect-free features on the simulated wafer image of the physical mask, wherein N is an integer equal to or greater than two.
12. The method of Claim 11, wherein the critical dimension deviation for each defect-free feature is added, and a resulting value is divided by N, thereby providing an average critical dimension deviation.
13. A method of providing printability analysis for a defect on a physical mask, the method comprising: generating a simulated wafer image of the physical mask; generating a simulated wafer image of a reference mask, the reference mask corresponding to a defect-free physical mask; computing an average critical dimension deviation for a defect-free area of the physical mask using the simulated wafer images of the physical and reference masks; computing a maximum critical dimension deviation for a defect area of the physical mask using the simulated wafer images of the physical and reference masks; and using the average critical dimension deviation and the maximum critical dimension deviation to provide the printability analysis.
14. The method of Claim 13, further including determining a defect severity score based on the step of using.
70
15. The method of Claim 13, further including determining a tolerance for critical dimension changes.
16. The method of Claim 15, wherein using includes using the tolerance for critical dimension changes to provide the printability analysis.
17. The method of Claim 15, wherein using includes determining the number of exposures analyzed.
18. A method of providing printability analysis for a defect on a physical mask, the method comprising: generating a simulated wafer image of the physical mask; identifying a first feature on the simulated wafer image affected by the defect; identifying a second feature on the simulated wafer image unaffected by the defect, wherein the first and second features have substantially the same critical dimension in the absence of the defect; computing a first critical dimension deviation for a defect-free area of the physical mask using the simulated wafer images of the physical and reference masks; computing a second critical dimension deviation for a defect . area of the physical mask using the simulated wafer images of the physical and reference masks; and using the first and second critical dimension deviations to provide the printability analysis.
19. The method of Claim 18, further including determining a tolerance for critical dimension changes.
20. The method of Claim 19, wherein using includes using the tolerance for critical dimension changes to provide the printability analysis.
71
21. The method of Claim 19, wherein using includes determining the number of exposures analyzed.
22. . A method of fabricating a physical mask, the method comprising: designing an integrated circuit; creating mask design data for a layer of the integrated circuit; manufacturing a physical mask conforming to the mask design data; inspecting the physical mask based on a simulated wafer image of the physical mask and a simulated wafer image of a reference mask, wherein the reference mask corresponds to a defect-free physical mask, wherein inspecting comprises: computing an average critical dimension deviation for a defect-free area of the physical mask using the simulated wafer images of the physical and reference masks ; computing a maximum critical dimension deviation for a defect area of the physical mask using the simulated wafer images of the physical and reference masks,- and using the average critical dimension deviation and the maximum critical dimension deviation to provide printability analysis; and determining whether the physical mask passes inspection based on the printability analysis.
23. The method of Claim 22, wherein inspecting includes: using a tolerance for critical dimension changes to provide printability analysis.
24. The method of Claim 23, wherein inspecting further includes determining a defect severity score based on using
72 the average critical dimension deviation, the maximum critical dimension deviation, and the tolerance for critical dimension changes .
25. The method of Claim 22, wherein using includes determining the number of exposures analyzed.
26. The method of Claim 25, wherein the printability analysis includes a defect severity score for at least one exposure .
27. The method of Claim 25, wherein the printability analysis includes a defect severity score for multiple exposures .
28. A method of generating a defect severity score for a defect on a mask, the method comprising: providing two-dimensional analysis on the defect and a first feature on the mask, the first feature being proximate to the defect; providing a first wafer image of the mask; and providing defect analysis on a second feature on the wafer image, the second feature corresponding to the first feature being simulated, wherein providing defect analysis includes computing various critical dimension deviations based on the first and second features.
29. The method of Claim 28, further including: identifying a third feature on a defect-free reference image of the mask, the third feature representing the first feature; providing a second wafer image of the reference image, the second wafer image including a fourth feature, the fourth
73 feature corresponding to the third feature being simulated; and providing defect analysis on the fourth feature, wherein providing defect analysis includes computing various critical dimension deviations based on the first, second, third, and fourth features.
30. The method of Claim 29, wherein providing defect analysis on the second and fourth features includes comparing critical dimensions on the second and fourth features.
31. The method of Claim 30, wherein providing defect analysis further includes determining changes of the critical dimensions at different exposures.
32. The method of Claim 31, wherein providing defect analysis further includes determining a maximum critical dimension change for each exposure.
33. The method of Claim 32, wherein providing defect analysis further includes calculating a relative maximum critical dimension change for each exposure.
34. The method of Claim 29, further including providing a calibration between the first and second wafer images.
35. A system for analyzing a defect on a physical mask, the system comprising: an inspection tool for generating a mask image from the physical mask and a reference image from a reference mask; a wafer image generator for simulating a stepper mask image from the mask image and a stepper reference image from the reference image; and a defect printability analysis generator for comparing the stepper mask image and the stepper reference image,_ wherein the defect printability analysis generator determines an average critical dimension deviation for a defect-free area on the physical mask using the stepper mask image and the stepper reference image, wherein the defect printability analysis generator determines a maximum critical dimension deviation for a defect area on the physical mask using the stepper mask image and the stepper reference image, and wherein the defect printability analysis generator uses the average critical dimension deviation and the maximum critical dimension deviation to provide printability analysis of the defect .
36. The system of Claim 35, further including a critical region identification generator for determining if the defect is located in a critical region of the physical mask, the critical region identification generator providing an output to the defect printability analysis generator.
37. The system of Claim 35, further including a bitmap editor for receiving data from the defect printability analysis generator and providing a suggested repair to the defect .
38. The system of Claim 37, further including a mask repair tool for responding to the suggested repair.
39. The system of Claim 38, wherein the system automatically analyzes the defect and the mask repair tool automatically responds to the suggested repair.
75
40. The system of Claim 35, wherein the system automatically analyzes the defect and the defect printability analysis generator automatically provides a severity score for the defect .
41. A system for generating a defect severity score for a defect on a physical mask, the system comprising: means for generating a first image of a feature on the physical mask proximate to the defect and a second image of the feature on the reference image; means for simulating a first wafer image of the first image and a second wafer image of the second image; and means for generating the defect severity score based on the first and second wafer images, wherein the means for generating determines an average critical dimension deviation for a defect-free area on the physical mask using the first and second wafer images, wherein the means for generating determines a maximum critical dimension deviation for a defect area on the physical mask using the first and second wafer images, and wherein the means for generating uses the average critical dimension deviation and the maximum critical dimension deviation to provide the defect severity score.
42. The system of Claim 41, further including means for identifying if the defect is within a critical region, wherein the means for identifying provides data to the means for generating the defect severity score .
43. The system of Claim 41, wherein the means for simulating includes means for responding to a plurality of lithographic conditions.
76
44. A physical mask comprising: at least one defect being modified based on a first average critical dimension deviation and a first maximum critical dimension deviation provided from analyzing a simulated wafer image of the physical mask and a simulated wafer image of a reference mask, the reference mask corresponding to a defect-free physical mask.
45. A physical mask comprising: at least one irregularity being modified based on a first average critical dimension deviation and a first maximum critical dimension deviation provided from analyzing a simulated wafer image of the physical mask and a simulated wafer image of a reference mask, the reference mask corresponding to a defect-free physical mask.
46. A physical mask comprising: at least one feature being modified based on a first average critical dimension deviation and a first maximum critical dimension deviation provided by comparing a simulated wafer image of the physical mask and a simulated wafer image of a reference mask, the reference mask corresponding to a defect-free physical mask.
47. An integrated circuit fabricated using a physical mask comprising: at least one feature being modified based on a first average critical dimension deviation and a first maximum critical dimension deviation provided by comparing a simulated wafer image of the physical mask and a simulated wafer image of a reference mask, the reference mask corresponding to a defect-free physical mask.
77
48. An integrated circuit fabricated using a physical mask made by the following steps: generating a simulated wafer image of the physical mask; generating a simulated wafer image of a reference mask, the reference mask corresponding to a defect-free physical mask; computing an average critical dimension deviation for a defect-free area of the physical mask using the simulated wafer images of the physical and reference masks; computing a maximum critical dimension deviation for a defect area of the physical mask using the simulated wafer images of the physical and reference masks; using the average critical dimension deviation and the maximum critical dimension deviation to determine whether to repair the physical mask; and fabricating the integrated circuit using the physical mask.
49. Computer software for analyzing a defect on a first mask, the software including: means for generating a simulated wafer image of the first mask; means for generating a simulated wafer image of a second mask, the second mask corresponding to a defect-free first mask; and means for computing an average critical dimension deviation for a defect-free area of the physical mask using the simulated wafer images of the physical and reference masks; means for computing a maximum critical dimension deviation for a defect area of the physical mask using the simulated wafer images of the physical and reference masks; and
78 means for using the average critical dimension deviation and the maximum critical dimension deviation to provide printability analysis regarding the defect.
50. The computer software of Claim 49, wherein the means for using includes: means for generating a defect severity score for the defect .
51. The computer software of Claim 49, further including: means for providing repair information on the defect based on the printability.
52. The computer software of Claim 50, further including: means for providing repair information on the defect based on the defect severity score.
53. A method of inspecting a physical mask, the physical mask including a defect, the method comprising the following steps : generating a simulated wafer image of the physical mask; generating a simulated wafer image of a reference mask, the reference mask corresponding to a defect-free physical mask; computing an average critical dimension deviation for a defect-free area of the physical mask using the simulated wafer images of the physical and reference masks; computing a maximum critical dimension deviation for a defect area of the physical mask using the simulated wafer images of the physical and reference masks; and
79 using the average critical dimension deviation and the maximum critical dimension deviation to provide printability analysis of the defect.
54. The method of Claim 53, wherein comparing includes generating a defect severity score.
55. The method of Claim 53, further including: communicating the information on the defect to a mask repair tool .
56. The method of Claim 54, further including: communicating the defect severity score to a mask repair tool .
57. The method of Claim 53, wherein the reference mask includes one of the following: a simulated image of a layout of the physical mask, a defect-free area of the physical mask having a substantially identical pattern to that including the defect, and a simulated image of the physical mask as the physical mask is processed in manufacturing.
58. The method of Claim 53, wherein generating the simulated image of the physical mask compensates for image distortions created during image capture.
59. A physical mask comprising: at least one defect being unmodified based on a first average critical dimension deviation and a first maximum critical dimension deviation provided from analyzing a simulated wafer image of the physical mask and a simulated wafer image of the reference mask, the reference mask corresponding to a defect-free physical mask.
60. The physical mask of Claim 59, further including at least one defect being modified based on a second average
80 critical dimension deviation and a second maximum critical dimension deviation provided from analyzing the simulated wafer images of the physical mask and the reference mask.
61. The physical mask of Claim 44, further including at least one defect being unmodified based on a second average critical dimension deviation and a second maximum critical dimension deviation provided from analyzing the simulated wafer images of the physical mask and the reference mask.
62. A physical mask comprising: at least one irregularity being unmodified based on a first average critical dimension deviation and a first maximum critical dimension deviation provided from analyzing a simulated wafer image of the physical mask and a simulated wafer image of a reference mask, the reference mask corresponding to a defect-free physical mask.
63. The physical mask of Claim 60, further including at least one irregularity being modified based on a second average critical dimension deviation and a second maximum critical dimension deviation provided from analyzing the simulated wafer images of the physical mask and the reference mask.
64. The physical mask of Claim 45, further including at least one irregularity being unmodified based on a second average critical dimension deviation and a second maximum critical dimension deviation provided from analyzing the simulated wafer images of the physical mask and the reference mask.
65. A physical mask comprising:
81 at least one feature being unmodified based on a first average critical dimension deviation and a first maximum critical dimension deviation provided by comparing a simulated wafer image of the physical mask and a simulated wafer image of a reference mask, the reference mask corresponding to a defect-free physical mask.
66 . The physical mask of Claim 65, further including at least one feature being modified based on a second average critical dimension deviation and a second maximum critical dimension deviation provided by comparing the simulated wafer images of the physical mask and the reference mask.
67. The physical mask of Claim 46, further including at least one feature being unmodified based on a second average critical dimension deviation and a second maximum critical dimension deviation provided by comparing the simulated wafer images of the physical mask and the reference mask.
68. An integrated circuit fabricated using a physical mask comprising: at least one feature being unmodified based on a first average critical dimension deviation and a first maximum critical dimension deviation provided by comparing a simulated wafer image of the physical mask and a simulated wafer image of a reference mask, the reference mask corresponding to a defect-free physical mask.
69. The integrated circuit of Claim 68, wherein the physical mask further includes at least one feature being modified based on a second average critical dimension deviation and a second maximum critical dimension deviation provided by comparing the simulated wafer images of the physical mask and the reference mask.
82
70. The integrated circuit of Claim 47, wherein the physical mask further includes at least one feature being unmodified based on a second average critical dimension deviation and a second maximum critical dimension deviation provided by comparing the simulated wafer images of the physical mask and the reference mask.
83
PCT/US2002/006491 2001-03-20 2002-02-28 System and method of providing mask defect printability analysis Ceased WO2002075793A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1020037012260A KR100610441B1 (en) 2001-03-20 2002-02-28 System and method for providing mask defect printability analysis
JP2002574111A JP4663214B2 (en) 2001-03-20 2002-02-28 System and method for providing printability analysis of mask defects
AU2002245560A AU2002245560A1 (en) 2001-03-20 2002-02-28 System and method of providing mask defect printability analysis

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US09/814,023 2001-03-20
US09/814,025 2001-03-20
US09/814,025 US6925202B2 (en) 2001-03-20 2001-03-20 System and method of providing mask quality control
US09/814,023 US6873720B2 (en) 2001-03-20 2001-03-20 System and method of providing mask defect printability analysis

Publications (3)

Publication Number Publication Date
WO2002075793A2 WO2002075793A2 (en) 2002-09-26
WO2002075793A3 WO2002075793A3 (en) 2003-05-01
WO2002075793B1 true WO2002075793B1 (en) 2004-05-21

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PCT/US2002/006491 Ceased WO2002075793A2 (en) 2001-03-20 2002-02-28 System and method of providing mask defect printability analysis

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JP (1) JP4663214B2 (en)
KR (1) KR100610441B1 (en)
CN (1) CN1290168C (en)
AU (1) AU2002245560A1 (en)
WO (1) WO2002075793A2 (en)

Families Citing this family (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9002497B2 (en) * 2003-07-03 2015-04-07 Kla-Tencor Technologies Corp. Methods and systems for inspection of wafers and reticles using designer intent data
DE10360536B4 (en) * 2003-09-30 2006-12-21 Infineon Technologies Ag Method for inspecting masks of a mask set for a multiple exposure
US8151220B2 (en) * 2003-12-04 2012-04-03 Kla-Tencor Technologies Corp. Methods for simulating reticle layout data, inspecting reticle layout data, and generating a process for inspecting reticle layout data
WO2005073807A1 (en) * 2004-01-29 2005-08-11 Kla-Tencor Technologies Corporation Computer-implemented methods for detecting defects in reticle design data
CN100413018C (en) * 2004-06-14 2008-08-20 中芯国际集成电路制造(上海)有限公司 Method and system for treating identity of semiconductor device
CN100428401C (en) * 2004-06-14 2008-10-22 中芯国际集成电路制造(上海)有限公司 Method and system for treating similarity of semiconductor device finished product ratio
JP4455469B2 (en) 2004-09-14 2010-04-21 エーエスエムエル マスクツールズ ビー.ブイ. Method for full chip manufacturing reliability check and correction
JP4904034B2 (en) * 2004-09-14 2012-03-28 ケーエルエー−テンカー コーポレイション Method, system and carrier medium for evaluating reticle layout data
US7729529B2 (en) 2004-12-07 2010-06-01 Kla-Tencor Technologies Corp. Computer-implemented methods for detecting and/or sorting defects in a design pattern of a reticle
JP2006337668A (en) * 2005-06-01 2006-12-14 Toshiba Corp Semiconductor device manufacturing method and layout pattern creation program
WO2007030704A2 (en) * 2005-09-09 2007-03-15 Brion Technologies, Inc. System and method for mask verification using an individual mask error model
JP4774917B2 (en) * 2005-10-27 2011-09-21 凸版印刷株式会社 Mask pattern inspection apparatus and inspection method
US20070177788A1 (en) * 2006-01-31 2007-08-02 David Liu System and method for detecting wafer failure in wet bench applications
US7596736B2 (en) * 2006-03-24 2009-09-29 International Business Machines Corporation Iterative process for identifying systematics in data
US7794903B2 (en) 2006-08-15 2010-09-14 Infineon Technologies Ag Metrology systems and methods for lithography processes
CN101512746B (en) * 2006-09-29 2010-08-11 佳能机械株式会社 Chip device picking method and chip device picking apparatus
US8038897B2 (en) * 2007-02-06 2011-10-18 Taiwan Semiconductor Manufacturing Company, Ltd. Method and system for wafer inspection
JP2009092954A (en) * 2007-10-09 2009-04-30 Toshiba Corp Pattern evaluation method
DE102007054994A1 (en) * 2007-11-17 2009-05-20 Carl Zeiss Sms Gmbh Method of repairing phase shift masks
NL1036189A1 (en) 2007-12-05 2009-06-08 Brion Tech Inc Methods and System for Lithography Process Window Simulation.
JP4942800B2 (en) 2009-08-18 2012-05-30 株式会社ニューフレアテクノロジー Inspection device
JP4918598B2 (en) * 2010-01-18 2012-04-18 株式会社ニューフレアテクノロジー Inspection apparatus and inspection method
US8196072B2 (en) * 2010-03-31 2012-06-05 Taiwan Semiconductor Manufacturing Company, Ltd. Method and apparatus of patterning semiconductor device
US8234603B2 (en) * 2010-07-14 2012-07-31 International Business Machines Corporation Method for fast estimation of lithographic binding patterns in an integrated circuit layout
CN102053093A (en) * 2010-11-08 2011-05-11 北京大学深圳研究生院 Method for detecting surface defects of chip cut from wafer surface
CN102789133B (en) * 2011-05-16 2014-09-03 中芯国际集成电路制造(上海)有限公司 After develop inspection method
CN102902154A (en) * 2011-07-29 2013-01-30 上海华虹Nec电子有限公司 Modeling method for optical proximity correction process model
CN109283800B (en) 2014-02-12 2021-01-01 Asml荷兰有限公司 Optimization method of process window
SG11201610106SA (en) * 2014-06-10 2016-12-29 Asml Netherlands Bv Computational wafer inspection
WO2017171890A1 (en) * 2016-04-02 2017-10-05 Intel Corporation Systems, methods, and apparatuses for reducing opc model error via a machine learning algorithm
US10451563B2 (en) 2017-02-21 2019-10-22 Kla-Tencor Corporation Inspection of photomasks by comparing two photomasks
DE102017203879B4 (en) * 2017-03-09 2023-06-07 Carl Zeiss Smt Gmbh Method for analyzing a defect site of a photolithographic mask
US10503078B2 (en) * 2017-09-01 2019-12-10 Kla-Tencor Corporation Criticality analysis augmented process window qualification sampling
WO2019070600A1 (en) * 2017-10-02 2019-04-11 Applied Materials Israel Ltd. Determining a critical dimension variation of a pattern
CN108932922B (en) * 2018-07-03 2021-05-14 京东方科技集团股份有限公司 Device and method for testing repair capability
US11079671B2 (en) * 2019-08-23 2021-08-03 Taiwan Semiconductor Manufacturing Company Ltd. Fabricating method of photomask, photomask structure thereof, and semiconductor manufacturing method using the same
KR20230037491A (en) * 2020-04-30 2023-03-16 포트로닉스, 인크. Systems, methods and program products for manufacturing photomasks
CN115561970B (en) * 2021-07-02 2025-08-19 中芯国际集成电路制造(上海)有限公司 Pattern detection method, apparatus, and storage medium
US12361535B2 (en) * 2021-10-25 2025-07-15 Applied Materials Israel Ltd. Mask inspection for semiconductor specimen fabrication

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4809341A (en) * 1986-07-18 1989-02-28 Fujitsu Limited Test method and apparatus for a reticle or mask pattern used in semiconductor device fabrication
US5029222A (en) * 1987-09-02 1991-07-02 Fujitsu Limited Photoelectron image projection apparatus
JPH04165353A (en) * 1990-10-30 1992-06-11 Oki Electric Ind Co Ltd Correction method of photo-mask
JPH0728226A (en) * 1993-04-30 1995-01-31 Internatl Business Mach Corp <Ibm> Equipment and method for measuring regional image
JP2776416B2 (en) * 1996-05-07 1998-07-16 日本電気株式会社 Reticle visual inspection device
US5795688A (en) * 1996-08-14 1998-08-18 Micron Technology, Inc. Process for detecting defects in photomasks through aerial image comparisons
JP3750270B2 (en) * 1997-04-21 2006-03-01 凸版印刷株式会社 Photomask defect analysis apparatus and defect analysis method
JP3750272B2 (en) * 1997-04-30 2006-03-01 凸版印刷株式会社 Photomask defect analysis apparatus, defect analysis method, and recording medium recording the defect analysis program
US6757645B2 (en) * 1997-09-17 2004-06-29 Numerical Technologies, Inc. Visual inspection and verification system
US5965306A (en) * 1997-10-15 1999-10-12 International Business Machines Corporation Method of determining the printability of photomask defects
US6614924B1 (en) * 1999-08-02 2003-09-02 Applied Materials, Inc. Adaptive mask technique for defect inspection
JP2001056306A (en) * 1999-08-19 2001-02-27 Jeol Ltd Sample surface inspection device

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KR100610441B1 (en) 2006-08-08
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