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WO2002071476A3 - Procede pour former des interconnexions conductrices dans des films isolants poreux et dispositif associe - Google Patents

Procede pour former des interconnexions conductrices dans des films isolants poreux et dispositif associe Download PDF

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Publication number
WO2002071476A3
WO2002071476A3 PCT/US2002/003945 US0203945W WO02071476A3 WO 2002071476 A3 WO2002071476 A3 WO 2002071476A3 US 0203945 W US0203945 W US 0203945W WO 02071476 A3 WO02071476 A3 WO 02071476A3
Authority
WO
WIPO (PCT)
Prior art keywords
opening
sidewall
insulating material
layer
comprised
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2002/003945
Other languages
English (en)
Other versions
WO2002071476A2 (fr
Inventor
John G Pellerin
Derick J Wristers
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of WO2002071476A2 publication Critical patent/WO2002071476A2/fr
Publication of WO2002071476A3 publication Critical patent/WO2002071476A3/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76835—Combinations of two or more different dielectric layers having a low dielectric constant
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

Le dispositif de circuit intégré décrit comporte une couche (32) isolante constituée d'une première matière isolante, dans laquelle est formé un orifice (36) défini par au moins une paroi latérale (36A), au moins un espaceur (40) de paroi latérale situé de façon adjacente à ladite paroi (36A) de l'orifice (36), l'espaceur (40) étant constitué d'une deuxième matière isolante ; et une interconnexion (42) conductrice formée dans l'orifice (36) de la couche (32) isolante. Dans une autre forme de réalisation, la première matière isolante présente une constante diélectrique inférieure à environ 3, et une densité inférieure à environ 1,2 g/cc ; et la deuxième matière isolante présente une constante diélectrique inférieure à environ 7, et une densité inférieure à environ 3 g/cc. Le procédé décrit comporte les étapes consistant à former un orifice (36) dans une première couche (32) d'une première matière isolante, cet orifice (36) étant défini par au moins une paroi latérale (36A) ; à déposer de façon conforme dans l'orifice (36), sur la paroi latérale (36A), une deuxième couche (38) constituée d'une deuxième matière isolante ; à mettre en oeuvre un procédé de gravure anisotrope sur la deuxième couche afin de définir un espaceur (40) de paroi latérale, constitué de la deuxième matière isolante et situé de façon adjacente à la paroi (36A) de l'orifice (36) ; et à former une interconnexion (42) conductrice dans l'orifice (36) de la couche (32) isolante, entre les éléments d'espaceur (40).
PCT/US2002/003945 2001-03-06 2002-02-01 Procede pour former des interconnexions conductrices dans des films isolants poreux et dispositif associe Ceased WO2002071476A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US80025001A 2001-03-06 2001-03-06
US09/800,250 2001-03-06

Publications (2)

Publication Number Publication Date
WO2002071476A2 WO2002071476A2 (fr) 2002-09-12
WO2002071476A3 true WO2002071476A3 (fr) 2003-03-13

Family

ID=25177889

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2002/003945 Ceased WO2002071476A2 (fr) 2001-03-06 2002-02-01 Procede pour former des interconnexions conductrices dans des films isolants poreux et dispositif associe

Country Status (1)

Country Link
WO (1) WO2002071476A2 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7928536B2 (en) 2006-03-29 2011-04-19 Fujitsu Limited Roughness reducing film at interface, materials for forming roughness reducing film at interface, wiring layer and semiconductor device using the same, and method for manufacturing semiconductor device

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102008045036B4 (de) * 2008-08-29 2011-06-22 GLOBALFOUNDRIES Dresden Module One Ltd. Liability Company & Co. KG, 01109 Verringern kritischer Abmessungen von Kontaktdurchführungen und Kontakten über der Bauteilebene von Halbleiterbauelementen

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5661344A (en) * 1994-08-05 1997-08-26 Texas Instruments Incorporated Porous dielectric material with a passivation layer for electronics applications
US5753967A (en) * 1995-09-14 1998-05-19 Advanced Micro Devices, Inc. Damascene process for reduced feature size
US5759906A (en) * 1997-04-11 1998-06-02 Industrial Technology Research Institute Planarization method for intermetal dielectrics between multilevel interconnections on integrated circuits
US5916823A (en) * 1998-10-13 1999-06-29 Worldwide Semiconductor Manufacturing Corporation Method for making dual damascene contact
US6140221A (en) * 1998-07-29 2000-10-31 Philips Electronics North America Corp. Method for forming vias through porous dielectric material and devices formed thereby

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5661344A (en) * 1994-08-05 1997-08-26 Texas Instruments Incorporated Porous dielectric material with a passivation layer for electronics applications
US5753967A (en) * 1995-09-14 1998-05-19 Advanced Micro Devices, Inc. Damascene process for reduced feature size
US5759906A (en) * 1997-04-11 1998-06-02 Industrial Technology Research Institute Planarization method for intermetal dielectrics between multilevel interconnections on integrated circuits
US6140221A (en) * 1998-07-29 2000-10-31 Philips Electronics North America Corp. Method for forming vias through porous dielectric material and devices formed thereby
US5916823A (en) * 1998-10-13 1999-06-29 Worldwide Semiconductor Manufacturing Corporation Method for making dual damascene contact

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7928536B2 (en) 2006-03-29 2011-04-19 Fujitsu Limited Roughness reducing film at interface, materials for forming roughness reducing film at interface, wiring layer and semiconductor device using the same, and method for manufacturing semiconductor device

Also Published As

Publication number Publication date
WO2002071476A2 (fr) 2002-09-12

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