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WO2002059966A8 - Planarizers for spin etch planarization of electronic components and methods of use thereof - Google Patents

Planarizers for spin etch planarization of electronic components and methods of use thereof

Info

Publication number
WO2002059966A8
WO2002059966A8 PCT/US2002/001861 US0201861W WO02059966A8 WO 2002059966 A8 WO2002059966 A8 WO 2002059966A8 US 0201861 W US0201861 W US 0201861W WO 02059966 A8 WO02059966 A8 WO 02059966A8
Authority
WO
WIPO (PCT)
Prior art keywords
layer
conductive
coupling
coupled
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2002/001861
Other languages
French (fr)
Other versions
WO2002059966A1 (en
Inventor
Shyama Mukherjee
Joseph Levert
Donald Debear
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Honeywell International Inc
Original Assignee
Honeywell International Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/768,439 external-priority patent/US6696358B2/en
Application filed by Honeywell International Inc filed Critical Honeywell International Inc
Priority to KR10-2003-7009631A priority Critical patent/KR20030086251A/en
Priority to EP02704222A priority patent/EP1354355A1/en
Priority to CA002432012A priority patent/CA2432012A1/en
Priority to JP2002560195A priority patent/JP2004523898A/en
Priority to AU2002237917A priority patent/AU2002237917A1/en
Publication of WO2002059966A1 publication Critical patent/WO2002059966A1/en
Anticipated expiration legal-status Critical
Publication of WO2002059966A8 publication Critical patent/WO2002059966A8/en
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
    • C23F3/00—Brightening metals by chemical means
    • C23F3/04—Heavy metals
    • C23F3/06—Heavy metals with acidic solutions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53233—Copper alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Weting (AREA)

Abstract

An electronic component contemplated comprises a substrate layer (110), a dielectric layer (120) coupled to the substrate layer (110), a barrier layer (130) coupled to the dielectric layer (120), a conductive layer (140) coupled to the barrier layer (130), and a protective layer (150) coupled to the conductive layer (140). A method of making the electronic component comprises the steps of providing a substrate (110) coupling a dielectric layer (120) to the substrate (110), coupling a barrier layer (130) to the dielectric layer (120), coupling a conductive layer (140) to the barrier layer (130), and coupling a protective layer (150) to the conductive layer (140). A method of planarizing a conductive surface of the electronic component comprises the steps of introducing or coupling a protective layer (150) onto a conductive layer (140), dispersing the protective layer (150) across the conductive layer (140), curing the protective layer (150), introducing an etching solution onto the conductive layer (140), and etching the conductive surface to substantial planarity.
PCT/US2002/001861 2001-01-23 2002-01-22 Planarizers for spin etch planarization of electronic components and methods of use thereof Ceased WO2002059966A1 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
KR10-2003-7009631A KR20030086251A (en) 2001-01-23 2002-01-22 Planarizers for spin etch planarization of electronic components and methods of use thereof
EP02704222A EP1354355A1 (en) 2001-01-23 2002-01-22 Planarizers for spin etch planarization of electronic components and methods of use thereof
CA002432012A CA2432012A1 (en) 2001-01-23 2002-01-22 Planarizers for spin etch planarization of electronic components and methods of use thereof
JP2002560195A JP2004523898A (en) 2001-01-23 2002-01-22 Planarizing material for spin-etch planarization of electronic device and method of using the same
AU2002237917A AU2002237917A1 (en) 2001-01-23 2002-01-22 Planarizers for spin etch planarization of electronic components and methods of use thereof

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US09/768,439 US6696358B2 (en) 2001-01-23 2001-01-23 Viscous protective overlayers for planarization of integrated circuits
US09/768,439 2001-01-23
US09/847,766 2001-05-01
US09/847,766 US6600229B2 (en) 2001-01-23 2001-05-01 Planarizers for spin etch planarization of electronic components

Publications (2)

Publication Number Publication Date
WO2002059966A1 WO2002059966A1 (en) 2002-08-01
WO2002059966A8 true WO2002059966A8 (en) 2003-10-16

Family

ID=28678458

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2002/001861 Ceased WO2002059966A1 (en) 2001-01-23 2002-01-22 Planarizers for spin etch planarization of electronic components and methods of use thereof

Country Status (5)

Country Link
EP (1) EP1354355A1 (en)
JP (1) JP2004523898A (en)
CN (1) CN1488170A (en)
AU (1) AU2002237917A1 (en)
WO (1) WO2002059966A1 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6939796B2 (en) * 2003-03-14 2005-09-06 Lam Research Corporation System, method and apparatus for improved global dual-damascene planarization
US6821899B2 (en) * 2003-03-14 2004-11-23 Lam Research Corporation System, method and apparatus for improved local dual-damascene planarization
DE102006008261A1 (en) * 2006-02-22 2007-08-30 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Etching solution for etching layer system, comprising phosphoric acid, nitric acid, de-ionized water and halogen component, which releases halogen ions that contain these components

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6146991A (en) * 1999-09-03 2000-11-14 Taiwan Semiconductor Manufacturing Company Barrier metal composite layer featuring a thin plasma vapor deposited titanium nitride capping layer

Also Published As

Publication number Publication date
EP1354355A1 (en) 2003-10-22
CN1488170A (en) 2004-04-07
AU2002237917A1 (en) 2002-08-06
WO2002059966A1 (en) 2002-08-01
JP2004523898A (en) 2004-08-05

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