WO2002056368A1 - High-frequency power amplifier and radio communication device - Google Patents

Abstract

A high-frequency power amplifier having multiple amplifying stages constituted of semiconductor amplifying elements that are MOS field-effect transistors having a lateral diffusion structure where the drain includes a drain low-concentration region. The lateral length of the drain low-concentration region of a drive-stage amplifying element is less than that of the drain low-concentration region of the final-stage amplifying element. Since the breakdown voltage of the final stage of the drive stage can be more lowered, the gain of the drive stage can be increased. Since only the lateral length of the drain low-concentration region is varied, the increase of the production cost is suppressed.

Description

 Description High-frequency power amplifier and wireless communication device

 The present invention relates to a multi-stage high-frequency power amplifying device (power amplifying device: high-frequency power amplifying module) in which a plurality of amplifiers (semiconductor amplifying elements) are cascaded in multiple stages, and a wireless communication device incorporating the high-frequency power amplifying device. In particular, the present invention relates to a manufacturing technique of a power amplifying apparatus having means for improving a gain of a driving stage while maintaining a conventional process technique and a manufacturing cost. Background art

 High-frequency power amplifiers used in wireless communication devices (wireless transceivers) such as mobile phones and mobile phones are composed of multiple amplifiers consisting of semiconductor amplifiers (transistors) cascaded in two or three stages. It has a multi-stage configuration. For example, in the case of a two-stage configuration, the first-stage amplifier stage constitutes a drive stage, and the two-stage amplifier stage constitutes an output stage.

 High-frequency power amplifiers require high efficiency, high gain, small size, and low cost. In addition, due to the peculiarity of portable use, the impedance of the antenna changes greatly under the use conditions, causing load mismatch and reflection, and a large voltage may be applied to the final stage amplifying element (semiconductor amplifying element). . It is necessary to consider the breakdown voltage that can withstand the amplification element.

Fig. 21 shows a block diagram showing the configuration of the high-frequency power amplifier, and a conceptual diagram for estimating the output voltage amplitude (max) of the final stage amplifier (output stage amplifier) and the driving stage amplifier. In Fig. 21, the high-frequency power amplifier is connected to drive stage 3 An example of a two-stage amplification configuration with the last stage 4 will be described. The high-frequency signal input to the input terminal 1 is amplified by the driving stage 3, then further amplified by the final stage 4, and output from the output terminal 2.

 In this high-frequency power amplifier, the output power of the final stage is Po2, the output voltage of the final stage is Vo2, the output power of the driving stage is P01, and the output voltage of the driving stage is Vo1. The reflected power is P o 2 \ and the reflected voltage is V 0 2 '. When the load mismatch is 10: 1, 67% (82% in voltage) of the output power Po2 is reflected, and the voltage is reached when the output power and the reflected power are in phase in the worst case. The output is superimposed as it is.

 For example, if the output power Po 2 is 4 W and the load impedance is 4 Ω, the output voltage Vo 2 will be 4 V, the reflected voltage yo 2 ′ will be 3.3 V, and the power supply voltage Vdd 5 V Then, a maximum amplitude of 12.3 V is applied to the last-stage element (semiconductor amplifier).

 On the other hand, assuming that the final stage gain PG is 10 dB, the drive stage output power Po 1 is ◦ .4 W and output voltage Vol 1.2 V (assuming load impedance 4 Ω). However, the voltage V o1, which corresponds to the peak power of the reflected power, is 1.0 V, and together with the power supply voltage V dd of 5 V, a maximum amplitude of 7.2 V is applied to the elements in the driving stage. Thus, the withstand voltage required for the elements in the driving stage can be significantly reduced.

By the way, it is generally known that B Vxf τ = —constant between the breakdown voltage characteristic BV and the amplification characteristic f T of the semiconductor element. Also, since the maximum available power gain (MAG) is proportional to the square of fT, halving the breakdown voltage and doubling: fT will improve MAG by 6 dB. In the above example, the withstand voltage of the driving stage can be set to 0.585 times (= 7.2 V / 12.3 V), which is compared to the case where the driving stage and the last stage use the same withstand voltage amplifier. 4.66 dB (= 20 lo (1 / 0.5.85)) gain can be improved. Take advantage of this By using an element with low withstand voltage and high amplification characteristics for the driving stage, it is possible to achieve high gain.

 FIG. 20 is a schematic cross-sectional view of a semiconductor device (semiconductor chip) having an amplifying element used in a conventional high-frequency power amplifying device. 1 shows a configuration diagram of an element (semiconductor amplification element).

 Fig. 20 shows an N-type bipolar junction transistor as an example. The collector region 56 of the driving stage and the collector region 57 of the final stage are separately formed on the P-substrate 55 using different masks. After the formation, the base region 58, the emitter region 59, the base, collector, and the extraction electrodes 60, 61, and 62 of the emitter region are formed by a common manufacturing process. The collector region 56 of the driving stage and the collector region 57 of the last stage are separately masked and formed in different processes so that the impurity concentrations Nc1 and Nc2 satisfy Nc1> Nc2. However, a drive stage and a final stage with different withstand voltages are realized on the same chip.

 However, in the above-described prior art, the collector impurity concentration of the bipolar junction transistor is changed in order to form amplification elements of the final stage and the driving stage having different breakdown voltages on the same semiconductor chip. This has the drawback of increasing manufacturing costs because it requires additional masks and manufacturing steps over the normal manufacturing steps.

 An object of the present invention is to increase the gain of a power amplifier without increasing manufacturing costs by forming amplification elements for the final stage and the driving stage having different breakdown voltages in the same manufacturing process without adding a new mask or manufacturing process. It is to realize the miniaturization accompanying it.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings. Disclosure of the invention

 The outline of typical inventions disclosed in the present application is briefly described as follows.

 (1) As an amplifying element of a high-frequency power amplifying device, a MOS type field effect of a drain offset structure having a laterally diffused structure and a drain low concentration region between the drain side end of the gate electrode and the drain high concentration region By using transistors and changing the mask pattern shape at the time of manufacturing, the length of the drain low-concentration region from the gate to the drain is designed to be longer in the final stage than in the driving stage. In addition, the semiconductor device is manufactured by the same process as that of the conventional MOS-type field effect transistor having a drain offset structure.

 According to this, a MOS-type field effect transistor having a drain offset structure is used for a multi-stage power amplifier, and the length of the drain low-concentration region of the driving stage is made shorter than that of the final stage to reduce the withstand voltage. Improving the gain can be realized only by changing the mask pattern shape.

 This has a large effect in that the performance can be improved without increasing the cost because no additional steps are required compared to the conventional manufacturing process. In addition, the mask does not require a new mask at all, and the mask needs to be improved so that the length of the drain low-concentration region of the driving stage is shorter than that of the final stage, and mask manufacturing costs can be reduced. is there.

 In addition, as described above, by improving the gain of the driving stage, the number of cascaded stages for obtaining the overall gain of the multi-stage amplifier can be reduced, and the matching circuit and its components between stages can also be reduced. The size and cost of the entire amplifier can be reduced, and the effect is significant.

(2) In the configuration of (1) above, without changing the drain offset length of the driving stage and the final stage, instead of the mask pattern shape at the time of manufacture, By changing the length, the length of the gate electrode is designed to be longer in the final stage than in the driving stage. With this configuration, the effect of the configuration (1) can be obtained similarly.

 (3) In a high-frequency power amplifier having a driving stage and a final stage, the power supply voltage of the driving stage is supplied through a voltage level conversion circuit that is lower than the power supply voltage of the entire high-frequency power amplifier and is stabilized. Voltage reduction and stabilization by the voltage level conversion circuit consist of voltage division by a resistor and a buffer amplifier, band gear / preference, diode electromotive voltage, and a buffer amplifier.

 As a result, overvoltage and unnecessary fluctuation of the power supply voltage can be suppressed, and the withstand voltage condition can be further reduced.

 In addition, since the voltage reduction and stabilization by the voltage level conversion circuit are composed of a voltage divider with a resistor, a buffer amplifier, a node gap reference, a diode electromotive voltage and a buffer amplifier, etc., it can be prototyped with the conventional LDMO SFET process. It does not add cost. Therefore, the effect is great in that the performance can be improved without increasing the cost. BRIEF DESCRIPTION OF THE FIGURES

 FIG. 1 is a schematic cross-sectional view of a semiconductor chip incorporated in a high-frequency power amplifier according to an embodiment (Embodiment 1) of the present invention.

 FIG. 2 is a flowchart showing a process of LDMO SFET formed on a semiconductor chip.

 FIG. 3 is a schematic cross-sectional view of a part of a semiconductor substrate on which oxide film element isolation has been performed in the manufacture of LDMO SFET.

FIG. 4 is a schematic cross-sectional view of a part of a semiconductor substrate on which a well (we1) has been formed in the manufacture of an LDMO SFET. FIG. 5 is a schematic cross-sectional view of a part of a semiconductor substrate on which a gate oxide film has been formed in the manufacture of an LD MOSFET.

 FIG. 6 is a schematic cross-sectional view of a part of a semiconductor substrate on which a gate electrode has been formed in the manufacture of LDMOSFET.

 FIG. 7 is a schematic cross-sectional view of a part of the semiconductor substrate on which the offset n-formation has been made in the manufacture of the LDM0SFET.

 FIG. 8 is a schematic cross-sectional view of a part of a semiconductor substrate on which n + has been formed in the manufacture of LDM0SFET.

 FIG. 9 is a schematic cross-sectional view of a part of a semiconductor substrate on which p + has been formed in the production of LDMOSFET.

 FIG. 10 is a schematic cross-sectional view of a part of a semiconductor substrate on which an extraction electrode has been formed in the production of LDMO SFET.

 FIG. 11 is a block diagram showing a part of the high-frequency power amplifier of the first embodiment.

 FIG. 12 is a perspective view showing the appearance of the high-frequency power amplifier module of the first embodiment.

 FIG. 13 is an equivalent circuit diagram of the high-frequency power amplifier module.

 FIG. 14 is a block diagram showing a configuration of a wireless communication device in which the high-frequency power amplification module of the first embodiment is incorporated.

 FIG. 15 is a schematic sectional view of a semiconductor element incorporated in a high-frequency power amplifier according to another embodiment (Embodiment 2) of the present invention.

 FIG. 16 is a block diagram showing a part of a high-frequency power amplifier according to another embodiment (Embodiment 3) of the present invention.

FIG. 1 is a circuit configuration diagram showing a first configuration example of a voltage level conversion circuit used in the third embodiment, and a configuration example of a band gap reference and an operational amplifier used therein. FIG. 18 is a circuit configuration diagram showing a second configuration example of the voltage level conversion circuit used in the third embodiment.

 FIG. 19 is a circuit configuration diagram showing a third configuration example of the voltage level conversion circuit used in the third embodiment.

 FIG. 20 is a schematic sectional view of a semiconductor device having an amplifying element used in a conventional high-frequency power amplifier.

 FIG. 21 is a conceptual diagram for estimating the output voltage amplitude of the final-stage amplifier and the driving-stage amplifier of a multistage high-frequency power amplifier, and specific numerical examples.

BEST MODE FOR CARRYING OUT THE INVENTION

 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for describing the embodiments of the present invention, components having the same function are denoted by the same reference numerals, and their repeated description will be omitted.

 (Embodiment 1)

 FIGS. 1 to 14 are diagrams relating to a high-frequency power amplifier according to an embodiment (Embodiment 1) of the present invention.

 FIG. 1 is a schematic cross-sectional view of a semiconductor chip incorporated in a high-frequency power amplifier, and FIG. 2 is a flowchart showing an LDMOS FET process formed on the semiconductor chip. 3 to 10 are schematic cross-sectional views of a part of the semiconductor substrate at each manufacturing stage in the manufacture of the LDMOS FET. FIG. 11 is a block diagram showing a part of the high-frequency power amplifier, and FIG. 12 is a diagram showing an appearance of the high-frequency power amplifier module. FIG. 13 is an equivalent circuit diagram of the high-frequency power amplifier module.

 FIG. 14 is a block diagram showing the configuration of a wireless communication device incorporating a high-frequency power amplification module. ·

As shown in FIG. 11, the high-frequency power amplifier of the first embodiment has a two-stage amplification configuration including a driving stage 3 and a final stage 4, and has an input terminal (P in). The high-frequency signal input to 1 is sequentially amplified in the driving stage 3 and the final stage 4, and the high-frequency signal is output from the output terminal (P out) 2. In the first embodiment, the withstand voltage BV1 of the semiconductor amplifying element forming the driving stage 3 becomes smaller than the withstand voltage BV2 of the semiconductor amplifying element forming the final stage 4, and the gain is increased by the reduced withstand voltage. be able to.

 Here, a description will be given of a semiconductor chip (semiconductor element) on which a semiconductor amplifying element constituting each of the driving stage 3 and the final stage 4 is formed.

 FIG. 1 is a schematic sectional view of a semiconductor chip on which amplifying elements (semiconductor amplifying elements) Q 1 and Q 2 constituting a driving stage 3 and a final stage 4 are formed. The driving elements and the final-stage amplifying elements Q 1 and Q 2 used in the two-stage high-frequency power amplifier (power amplifier) have a lateral diffusion structure. The drain (D) side end of the gate (G) electrode and the drain height It is a MOS-type field effect transistor (Metal Oxide Semiconductor Field Effect Transistor) with a drain offset structure having a low-concentration region between drain regions, and is generally called an L DMO SFET (Lateral Diffused-MOSFET). ing. Fig. 2 is a flowchart showing the manufacturing process.

 Steps (1) to (4) in FIG. 2, namely, (1) oxide film element separation, (2) Nwe 11 / P we 11 formation, (3) gate oxide film formation, (4) gate electrode formation, (4) offset n_ Formation (entire surface), ⑥ n + formation (selection) _NMO S, + p + formation (selection) — PMO S, 半導体 Semiconductor device (semiconductor chip) is manufactured through each process of forming extraction electrode. FIGS. 3 to 10 show cross-sectional views of the semiconductor substrate at the stage when the above steps are completed.

(1) In the oxide film element isolation step, the semiconductor substrate 5 is prepared, and an insulating film 12a made of an oxide film is selectively formed on the surface (main surface) for element isolation (see FIG. 3). The semiconductor substrate 5 is made of a first conductivity type or second conductivity type silicon substrate. Not shown, but same on surface A semiconductor substrate 5 provided with a conductive type epitaxial layer may be used. In the next step of forming Nwe11 / Pwe11, the Nwell diffusion layer 7 for PMOS and the Pwe11 diffusion layer 6 for LDMOSFET are made to be of the first conductivity type by ordinary impurity diffusion and annealing. It is formed on a semiconductor substrate 5 of the second conductivity type (see FIG. 4).

 Next, a gate oxide film 12 is formed on the entire main surface of the semiconductor substrate 5 ((3) Gate oxide film forming step: see FIG. 5), and a gate oxide film 12 is formed on the gate oxide film 12 in the region where the FET is to be formed. A gate electrode 8 is selectively formed (gate electrode forming step: see FIG. 6).

 Next, an impurity is selectively implanted into the main surface of the semiconductor substrate 5 to form an n-type drain low-concentration region (n-layer) 9 (⑤offset n_ formation (entire surface) Process: FIG. 7 reference). In this case, since the gate electrode 8 and the insulating film 12a serve as a mask, the n-type drain low-concentration region (n-type) is formed on the surface layer of the semiconductor layer exposed from the gate electrode 8 and the insulating film 12a. —Layer) 9 will be formed.

 Next, an n-type drain Z source high concentration region 10 serving as a drain region or a source region is selectively formed using a mask (not shown) (⑥ n + formation (selection) — NM 0 S step: see FIG. 8). ). Similarly, a p-type drain / source high-concentration region 11 serving as a drain region or a source region for PMOS is selectively formed using a mask (not shown) (⑦p + formation (selection) —PMOS process: first step). 9).

 Next, an insulating film 12 c is selectively formed on the main surface of the semiconductor substrate 5, and a gate lead electrode 13, a source lead electrode 14, and a drain lead electrode 15 are formed. Forming process: see FIG. 10).

As a result, as shown in FIGS. 1 and 10, the N-channel M〇S (NMO S) having the LDM〇S structure and the P-ch It is possible to manufacture semiconductor devices with channel type MOS (PM.0S).

 Although FIGS. 2 and 3 to 10 show only the formation state of the semiconductor elements, in practice, a plurality of semiconductor element portions are formed vertically and horizontally on a semiconductor substrate (wafer) having a large area and then divided vertically and horizontally. Thus, a large number of semiconductor elements are manufactured. If necessary, other active elements such as transistors and passive elements such as resistors may be formed in the semiconductor element.

 In the manufacture of the semiconductor element, the offset n—forming (entire surface) step includes, as shown in FIG. 1, the length L r 1 of the offset n region of the drive stage amplifying element Q 1. Is formed shorter than the length L r 2 of the offset n-region of the final-stage amplification element Q 2.

 That is, the mask pattern of the selectively formed n-type drain Z source high-concentration region 10 is adjusted, and the drain-side end of the gate electrode 8 with respect to the driving-stage amplifier element Q1 and the final-stage amplifier element Q2 is adjusted. Length Lr1 and offset length Lr2 of n-type drain low-concentration region (n-layer) 9 between n-type drain / source high-concentration region 10 and Lr1 and Lr2 So that

 As a result, the breakdown voltages BVI and BV2 of the drive stage amplifier element Q1 and the final stage amplifier element Q2 satisfy BV1 <BV2. Therefore, the gain of the driving stage amplifying element Q1 can be increased.

 In this way, without additional steps, etc., the amplifying element can be manufactured simply by changing the pattern dimensions of the n-type drain low-concentration region (n-layer) 9 and n-type drain / source high-concentration region 10 in the mask pattern. Since the withstand voltage can be changed, the gain can be improved by suppressing the withstand voltage without increasing the cost.

FIG. 12 is a perspective view showing the appearance of a high-frequency power amplifier (high-frequency power amplifier module) 95 incorporating the above-described semiconductor element. The high-frequency power amplifier module 95 includes a module substrate 96 composed of a plate-like wiring substrate, A package 98 having a flat rectangular structure is formed by the cap 97 mounted on the module substrate 96 in a superimposed manner. Package 9 8 is made of metal that plays the role of electromagnetic shielding.

Ό o

 From the package 98, electrically independent external electrode terminals are exposed. That is, in this example, external electrode terminals for surface mounting are provided from the side surface to the lower surface of the module substrate 96. The external electrode terminals are formed by wiring formed on the surface of the module substrate 96 and PbSn solder formed on the surface of the wiring.

As shown in Fig. 12, the external electrode terminals are an input terminal Pin, a second voltage terminal GND, and a bias supply terminal V ape from left to right on one edge of the package 98, and At the other edge, from left to right, the output terminal is P out, the GND _{5 is} the first voltage terminal V dd.

 FIG. 13 is an equivalent circuit diagram of the high-frequency power amplification module 95. In this equivalent circuit, capacitors (C1 to C10), bypass capacitors (CB) and resistors (R1 to R4) are incorporated in each part for the purpose of matching or potential adjustment. The white frame indicates the microstrip line.

 FIG. 14 is a block diagram showing a system configuration of a wireless communication device in which the high-frequency power amplification module of the first embodiment is incorporated. Specifically, it shows the system configuration of a mobile phone (mobile communication terminal).

The mobile phone includes a transmitter / receiver 82 having a receiver 83 and a transmitter 84, a reception signal processing unit 85, a demodulator 86, and a transmitter 84 connected to the receiver 83 in order. A baseband unit 89 having a transmission signal processing unit 87 and a modulator 88 connected sequentially to the baseband unit 89, an RF block unit 70 connected to the baseband unit 89, and a connection to the RF block unit 70 Antenna 8 0 and a control unit 90 connected to the baseband unit 89 and the RF block unit 70 and having a control circuit 91 and a display key 92.

 The RF block 70 is provided with an antenna switch 71. The antenna switch 71 includes a high-frequency amplifier 74 of a receiving section 75 composed of an IF amplifier 72, a reception mixer 73, and a high-frequency amplifier 74, a transmission mixer 76, a transmission power amplifier (a high-frequency power amplifier). Module) 95 is connected to the high frequency power amplification module 95 of the transmission section 78 and the antenna 80.

 The reception mixer 73 and the transmission mixer 76 are connected to a frequency synthesizer 79.

 In the transmission system, the voice (acoustic signal) spoken toward the transmitter 84 is converted into an electric signal by the transmitter 84 and converted into a transmission signal by the transmission signal processor 87, and Modulator 8 8 Converts analog to digital. Thereafter, the transmission signal is converted to a target frequency by the frequency synthesizer 79 in the transmission mixer 76 of the transmission section 78, further amplified by the high-frequency power amplification module 95 of the first embodiment, and transmitted to the antenna switch 71. It is transmitted as a radio wave from antenna 80 by switching.

 In the receiving system, the received signal captured by the antenna 80 is amplified by the high-frequency amplifier 74 of the receiving unit 75 by switching the antenna switch 71, and is also amplified by the frequency synthesizer 79 by the receiving mixer 73. Converted to frequency. Thereafter, the received signal is amplified by an IF amplifier 72, converted from a digital signal into an analog signal by a demodulator 86 of a baseband unit 89, processed by a received signal processing unit 85, and processed by a receiver 8. At 3 it is converted to an acoustic signal.

In such a wireless communication device, the withstand voltage of the first-stage amplifying element of the high-frequency power amplifier 95 is made smaller than the withstand voltage of the last-stage amplifying element. Since the gain in the first amplification stage can be increased, high output can be achieved.

 According to the first embodiment, the following effects can be obtained.

 (1) According to the first embodiment, a MOS type field effect transistor having a drain offset structure is used for a power amplifier having a multi-stage configuration, and the length of the drain low-concentration region of the driving stage is made shorter than that of the final stage to withstand voltage. Can be reduced and the gain can be improved simply by changing the mask pattern shape. This has a large effect in that the performance can be improved without increasing the cost because no additional steps are required compared to the conventional manufacturing process. In addition, the mask does not require a new mask at all, and needs to be improved to the extent that the length of the low-concentration drain region in the driving stage is shorter than that in the final stage, so that mask manufacturing costs can be reduced.

 Also, by improving the gain of the drive stage, the number of cascaded stages for obtaining the overall gain of the multistage amplifier can be reduced, and the interstage matching circuit and its components can also be reduced. And cost reductions are possible.

 (Embodiment 2)

FIG. 15 is a schematic sectional view of a semiconductor element incorporated in a high-frequency power amplifier according to another embodiment (Embodiment 2) of the present invention. In the second embodiment, instead of changing the offset length of the n-type drain low-concentration region (n-layer) 9 in the LDM 0 SFET of the first embodiment, the gate of the drive stage amplifier element Q 1 is changed. The length Lgl is shorter than the gate length Lg2 of the final-stage amplifier Q2. When L gl and L g 2 are satisfied, the withstand voltage BV 1 and BV 2 of the driving stage amplifying element Q 1 and the final stage amplifying element Q 2 are equal to L V, similarly to L r in the first embodiment. 1 and BV 2, which has the same effect as in the first embodiment. That is, according to the second embodiment, the MS type field effect transistor having the drain offset structure is used for the multi-stage power amplifier, and the length of the gate electrode of the driving stage is shorter than that of the last stage. It is possible to reduce the breakdown voltage and improve the gain by simply changing the mask pattern shape.

 This has a large effect in that the performance can be improved without increasing the cost because no additional steps are required compared to the conventional manufacturing process. In addition, the mask does not require a new mask at all, and requires improvement such that the gate length of the driving stage is shorter than the gate length of the final stage, and mask manufacturing costs can be reduced. .

 (Embodiment 3)

 FIG. 16 is a block diagram showing a part of a high-frequency power amplifier according to another embodiment (Embodiment 3) of the present invention.

 The high-frequency power amplifier module according to the third embodiment has a two-stage amplification configuration including a driving stage 3 ′ and a final stage 4, as in the first embodiment, and the final stage 4 receives the power supply voltage V dd from the power supply terminal 16. The power supply voltage V dd is supplied to the drive stages 3 and 3 via the voltage level conversion circuit 17 while being supplied directly. The electromotive force of batteries used in mobile devices such as mobile phones fluctuates greatly depending on the usage conditions. For example, in a lithium-ion battery, the average voltage varies from 2.7 V to 5 V with respect to 3.6 V. Therefore, the withstand voltage of the power amplifier (high-frequency power amplifier) is also designed considering the fluctuation. There is a need.

A higher power supply voltage is advantageous in the final stage to extract output power, but a drive stage with a lower output power than the final stage requires a smaller output voltage amplitude than the power supply voltage, so the power supply voltage can be lower than the final stage. . By using a voltage level conversion circuit 17 to divide and lower or stabilize the power supply voltage, the withstand voltage of the element is reduced by the variation margin of the battery electromotive force, which was considered in the past. Can be set. As the withstand voltage is reduced, the gain of the drive stage is improved, which leads to higher gain of the whole power amplifier.

 FIG. 1 is a circuit configuration diagram showing a first configuration example of a voltage level conversion circuit used in Embodiment 3 and a configuration example of a pan gear preference and an operational amplifier used there.

 The voltage level conversion circuit shown in FIG. 17 (a) will be described. The band gap reference 18 generates a potential independent of temperature by the size ratio of the diodes 24 and 25 and the resistor 26 as shown in an example shown in FIG. The potential of the power supply voltage is not dependent on the transistors 28 and 29 and the operational amplifier 30 that constitute the circuit. The output terminal 3 is composed of the transistor 31, the diode 32, and the resistor 33 that constitute the current mirror circuit. An output is generated at 4.

 As shown in Fig. 17 (c), the operational amplifier consists of differential pairs 38, 39 receiving their inputs from the inverting input terminal 36 and the non-inverting input terminal 35, their current sources 40, and the active load. It consists of 41, 42, output stages 45, 46, and phase compensation capacitor 47, and obtains output from the output terminal 37.

 When the output of the band gap reference 18 is input to the non-inverting input terminal of the operational amplifier 19 and the voltage dividing points of the resistors R 1 and R 2 are input to the inverting input terminal, the output potential V 0 — 0 p of the operational amplifier becomes With respect to the output potential V bgap of Reference 18, V o — op = (R 1 + R 2) x (V bgap / R 2), which is independent of the power supply voltage. This V o — op is output to the output terminal 23 via the voltage follower 22.

FIG. 18 is a circuit configuration diagram showing a second configuration example of the voltage level conversion circuit used in the third embodiment. As shown in Fig. 18 (a), a plurality of diode-connected MOS field-effect transistors 49, 50 and a resistor 48 are connected to the cathode terminal of the diode and the power terminal to the ground terminal. 1 come to 6 side In this way, the potential at the connection point of the diode and the resistor is output via the voltage follower 51.

 The circuit shown in Fig. 18 (b) is a circuit in which the constant current source 44 is used instead of the resistor 48 in the circuit shown in Fig. 18 (a). A similar effect can be obtained with this circuit configuration.

 FIG. 19 is a circuit configuration diagram showing a third configuration example of the voltage level conversion circuit used in the third embodiment. As shown in Fig. 19, the resistors 52 and 53 are connected in series between the ground and the power supply terminal 16 and the potential at the connection point between the resistors is output to the output terminal 30 via the voltage follower 54. It is assumed that. The above-mentioned voltage level conversion circuit reduces and stabilizes the voltage by using a conventional LDMOSFET process, because the voltage is reduced and stabilized by dividing the voltage with a resistor and an amplifier, and a node gap reference and a diode electromotive force and an amplifier. Since it can be manufactured, it requires only minor changes to the mask mask and no additional steps are required. As a result, the performance of the high-frequency power amplification module can be improved without increasing the cost.

 As described above, by improving the gain of the driving stage, the number of cascaded stages for obtaining the overall gain of the multistage amplifier (high-frequency power amplifier module) can be reduced, and the interstage matching circuit and its components are also reduced. This makes it possible to reduce the size and cost of the entire power amplifier.

 Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the above embodiment, and it can be said that various modifications can be made without departing from the gist of the invention. Not even.

For example, Embodiment 3 supplies a power supply voltage to the drive stage via a voltage level conversion circuit, Embodiment 1 in which the drain offset length is shortened in the drive stage, and Embodiment 2 in which the gate length is shortened in the drive stage. A combination of the above may be used. In this case, the power supply voltage of the driving stage is supplied through a voltage level conversion circuit that is lower and stabilized than the power supply voltage of the entire high-frequency power amplifier, thereby suppressing overvoltage and unnecessary fluctuation of the power supply voltage. The withstand voltage condition can be further reduced. Accordingly, the length of the low-concentration drain region and the length of the gate electrode can be further reduced, and the gain can be further improved.

 Further, in each of the above embodiments, the example of the two-stage high-frequency power amplification module including the first-stage semiconductor amplification element and the last-stage semiconductor amplification element has been described. The present invention is also applicable to a configuration in which one or more middle-stage semiconductor amplifying elements are cascaded.

 In the above description, the case where the invention made by the inventor is mainly applied to a mobile phone, which is the field of application as the background, has been described. However, the present invention is not limited to this case. Applicable to amplification devices.

 The present invention can be applied at least to a high-frequency power amplifying device incorporated in a wireless communication device. Industrial applicability

 As described above, the high-frequency power amplifying device according to the present invention can be used as a power amplifier of various wireless communication devices such as a mobile phone such as a mobile communication terminal. Further, it is possible to provide a wireless communication device capable of achieving stable communication. Further, improvement in the manufacturing yield of the high-frequency power amplifier module and the wireless communication device can reduce the manufacturing cost of the high-frequency power amplifier and the wireless communication device.

Claims

The scope of the claims  1. Input terminal and  An output terminal,  A plurality of amplification stages connected in cascade between the input terminal and the output terminal,  A semiconductor amplifier included in the first amplifier coupled to the output terminal and the second amplifier coupled between the input terminal and the first amplifier in the amplification stage includes a gate amplifier. A drain offset structure having a low drain concentration region between the drain side end of the gate electrode and the high drain concentration region,  The length of the drain low-concentration region along the direction from the gate to the drain of the field-effect transistor included in the first amplifier is equal to the drain low-concentration region of the field-effect transistor included in the second amplifier. A high-frequency power amplifier characterized by being longer than the length of the region. 2.The first amplifier is directly supplied with a power supply voltage from a power supply voltage terminal, and the second amplifier is supplied with a voltage from a voltage level conversion circuit that converts the power supply voltage to a voltage lower than the power supply voltage. 2. The high-frequency power amplifier according to claim 1, wherein:  3. The low-concentration drain region of each of the field-effect transistors included in the first amplifier and the second amplifier is formed by the same process. 2. The high-frequency power amplifier according to claim 1, wherein  4. The voltage level conversion circuit is 3. The high-frequency power amplifier according to claim 2, wherein the circuit outputs a desired voltage generated based on a band gap reference that generates a stable voltage with respect to the power supply voltage or the temperature. 5. The above voltage level conversion circuit  A plurality of field-effect transistors in which the gate and the drain of the semiconductor amplifying element are diode-connected are connected in series with respect to ground, and the plurality of field-effect transistors connected in series are connected to the opposite end to the ground. 3. The high-frequency device according to claim 2, wherein a resistor is connected between the power supply voltages, and the circuit is configured to output a desired voltage generated based on contact points of the plurality of the field effect transistors and the resistor. Power amplification device.  6. The above voltage level conversion circuit  A plurality of field-effect transistors in which the gate and the drain of the semiconductor amplifying element are diode-connected are connected in series with reference to ground, and a plurality of the series-connected field-effect transistors are connected to the opposite end to the ground. A voltage level conversion circuit, wherein a constant current source is connected between power supply voltages, and the voltage level conversion circuit outputs a desired voltage generated based on a contact point between the plurality of field effect transistors and the constant current source. 3. The high-frequency power amplifier according to claim 2.  7. The above voltage level conversion circuit  3. The high-frequency circuit according to claim 2, wherein the circuit outputs a desired voltage generated based on a voltage at a connection point between two resistors connected in series between the power supply voltage terminal and ground. Power amplification device. 8. Input terminal and  An output terminal,  A plurality of amplification stages connected in cascade between the input terminal and the output terminal, A semiconductor amplifier element included in the first amplifier coupled to the output terminal and the second amplifier coupled between the input terminal and the first amplifier in the amplification stage has a gate electrode Drain side edge and drain A drain offset structure having a low-concentration drain region between  A high frequency power amplifier, wherein the gate length of the field effect transistor included in the first amplifier is longer than the gate length of the field effect transistor included in the second amplifier.  9.A power supply voltage is directly supplied to the first amplifier from a power supply voltage terminal, and a voltage is supplied to the second amplifier from a voltage level conversion circuit that converts the voltage to a voltage lower than the power supply voltage. 9. The high-frequency power amplifier according to claim 8, wherein:  10. The gate length of each of the field-effect transistors included in the first amplifier and the second amplifier is formed by the same process. High frequency power amplifier described 1 1. The above voltage level conversion circuit  10. The high-frequency power amplifier according to claim 9, wherein the circuit outputs a desired voltage generated based on a bandgap reference that generates a stable voltage with respect to the power supply voltage or the temperature. .  1 2. The above voltage level conversion circuit  A plurality of field-effect transistors in which the gate and the drain of the semiconductor amplifying element are diode-connected are connected in series with respect to ground, and the other end of the plurality of field-effect transistors connected in series and opposite to the ground. 10. A high-frequency circuit according to claim 9, wherein a resistor is connected between power supply voltages, and the circuit outputs a desired voltage generated with reference to a plurality of contact points between the field-effect transistor and the resistor. Power amplification device.  1 3. The above voltage level conversion circuit The gate and drain of the above-mentioned semiconductor amplifying device were diode-connected. A plurality of field effect transistors are connected in series with respect to ground, and a constant current source is connected between the power supply voltage and the other end of the plurality of field effect transistors connected in series, which is opposite to the ground, 10. The high-frequency power amplifier according to claim 9, wherein the high-frequency power amplifier is a voltage level conversion circuit that outputs a desired voltage generated with reference to a contact point between the plurality of the field effect transistors and a constant current source.  1 4. The above voltage level conversion circuit  10. The high-frequency circuit according to claim 9, wherein the circuit outputs a desired voltage generated based on a voltage at a connection point of two resistors connected in series between the power supply voltage terminal and ground. Power amplification device.  15. A wireless communication device having a high-frequency power amplifier in a transmission unit, wherein the high-frequency power amplifier is the high-frequency power amplifier according to claim 1.  16. A wireless communication device having a high-frequency power amplifier in a transmission unit, wherein the high-frequency power amplifier is the high-frequency power amplifier according to claim 8.