WO2001033705A1

WO2001033705A1 - Control circuit for a switching regulator

Info

Publication number: WO2001033705A1
Application number: PCT/AU2000/001338
Authority: WO
Inventors: Lawrence Joseph Borle
Original assignee: Origin Energy Retail Ltd
Current assignee: Origin Energy Retail Ltd
Priority date: 1999-11-02
Filing date: 2000-11-01
Publication date: 2001-05-10
Anticipated expiration: 2002-05-02
Also published as: AUPQ381199A0; AU1119101A

Abstract

A control circuit for a switching regulator having an inductor, said control circuit having a first controller J to switch between a positive voltage and an alternating voltage across said inductor, and a second controller K to switch between a negative voltage and said alternating voltage across said inductor. The first controller J and second controller K normally alternate to operate said switching regulator in half-bridge switching mode to produce a current waveform in said inductor, with the timing of switching instants calculated to achieve an average current error signal close to or near zero, based on timing of previous switching instances. When it is calculated that a desired zero crossing time of the current error signal will be overshot, the control circuit starts the inactive controller of the first and second controllers J and K to cause the inactive controller to operate when the desired zero crossing time has been overshot, to bring said current error signal rapidly to zero crossing. Both the first and second controllers J and K will operate the switching regulator in plural half bridge switching mode until it is determined that a desired zero crossing time of the current error signal is reached early, whereafter half bridge switching mode operation of the switching regulator is resumed.

Description

Control Circuit For A Switching Regulator

FIELD OF THE INVENTION

This invention relates to switching regulators for inter alia deriving an AC or DC power supply, and in particular to a control circuit therefor.

BACKGROUND ART

Hysteresis current control has been used in many applications and has been found to be a very effective method of current regulation. It is simple to understand easy to implement, and is stable regardless of load conditions Hysteresis current control can accurately follow a reference signal with a steady state and dynamic response limited only by the inductor in the power circuit Power circuit parameter variations or second order non-linearities are easily accommodated.

The main disadvantage of hysteresis current control is that the switching frequency varies significantly with line and load variations. This can have a negative impact on efforts to minimize the ripple current, and requires that the outer control design must accommodate both a minimum and a maximum switching frequency Additional difficulties also arise since the hysteresis bands are generally set in analog circuitry which can cause steady-state fidelity errors Also, intentional delays in the implementation of switching decisions - generally due to anti "shoot-through" logic - result in steady-state errors.

While the above disadvantages may be significant in only a portion of applications, their elimination in a current regulator which is also easily implemented and cost effective would be advantageous. There have been many efforts to restrict the switching frequency of hysteresis controllers, as described in Q Yao and D. G. Holmes, "A simple, novel method for vanable-hysteresis- band current control of a three phase inverter with constant switching frequency", Proc. IEEE Industry Applications Society Annual Meeting, 1993, pp 1122-1129, L. J. Borle and C. V. Nayar, "Zero Average Current Error Controlled Power Flow for AC-DC Power Converters", IEEE Trans. Power Electronics, Nov. 1995, pp 725-732; E. Persson, N. Mohan, and B. B. Banerjee, "Adaptive Tolerance-Band Current Control of Standby Power Supply Provides Load-Current Harmonic Neutralization", IEEE Power Electronics Specialist's Conference (PESC'92), Toledo, Spain, pp 320-326, June, 1992; T. Szepesi, "Hysteretic current-mode control of transformer-coupled dc/dc converters", Power Electronics Show and Conference 1986, pp 60-67; R. Redl and N. O. Sokal, "Frequency stabilization and synchronization of free-running current-mode controlled converters", IEEE 1986 Power Electronics Specialists Conference (PESC'86), pp 519-530; C. P. Henze and N. Mohan, "A digitally controlled ac to dc power conditioner that draws sinusoidal input current", IEEE 1986 Power Electronics Specialists Conference (PESC'86), pp 531 -540; and T. Szepesi, "Stabilizing the frequency of hysteretic current mode dc/dc converters", IEEE 1986 Power Electronics Specialists Conference (PESC'86), pp 550-559..

Recently, an alternative digital current control technique was proposed which overcomes the above limitations. This technique is described variously in L. J. Borle, "A Three-phase grid-connected inverter with improved ramptime current control in programmable logic", IEEE 1998 International Conference on Power Electronics Drives and Energy Systems for Industrial Growth, PEDES'98, pp 452-457; L. J. Borle, "Method and Control Circuit for a Switching Regulator", United States Patent US5801517 granted 1 -September-1998; L J. Borle, M. S. Dymond and C. V. Nayar, "Development and testing of a 20-kW grid interactive photovoltaic power conditioning system in Western Australia", IEEE Trans. Ind. App., Vol. 33, No. 2, March/April 1997, pp 502-508; L J. Borle and C. V. Nayar, "Ramptime Current Control", IEEE Applied Power Electronics Conference, 1996, APEC'96, pp 828-834; and L. J. Borle, "Four Quadrant Power Flow in a Ramptime Current Controlled Converter", IEEE Applied Power Electronics Conference, 1996, APEC'96, pp 898-904.

Ramptime current control uses the relative timings of recent switching events and the zero crossings of the current error signal to determine when the next switching transition should occur Like hysteresis current control, switching instants are continuously generated so as to push the current error signal back towards zero Unlike hysteresis current control, in the most preferred form of ramptime current control, switching instants are chosen with the intention that the next zero crossing of the current error signal will occur a half switching period after the last zero crossing This is how the switching frequency is fixed

It has been found that in a full bridge switching regulator, the ramptime technique as described in the foregoing publications is unable to maintain a minimum desirable ripple current in the inductor

It has also been found that in a half bridge switching regulator, the ramptime technique as described in the foregoing publications is unable to maintain a transient response which would be considered to be ideal.

It is an object of this invention to provide a control circuit for a switching regulator which provides improved control over the ripple current in the inductor and improved transient response of the switching regulator.

This is achieved in a switching regulator such as a full bridge voltage source inverter, by choosing between three (or more) available voltages that can be placed across the inductance in a manner that uses the minimum voltage for normal operation, but chooses the maximum available voltage to help track a rapidly changing current reference. In one embodiment of the invention, this is achieved by using two ramptime type regulators together to choose the appropriate voltages for the appropriate proportion of time in a switching period so as to minimize the ripple current while maintaining full controllability and ability to follow a rapidly changing reference current

Throughout the specification, unless the context requires otherwise, the word "comprise" or variations such as "comprises" or "comprising", will be understood to imply the inclusion of a stated integer or group of integers but not the exclusion of any other integer or group of integers DISCLOSURE OF THE INVENTION

In accordance with one aspect of the present invention there is provided a control circuit for a switching regulator having an inductor, said control circuit having a first controller to switch between a positive voltage and an alternating voltage across said inductor, and a second controller to switch between a negative voltage and said alternating voltage across said inductor, where said first controller and said second controller normally alternate to operate said switching regulator in half-bridge switching mode to produce a current waveform in said inductor, where the timing of switching instants is calculated to achieve an average current error signal close to or near zero, based on timing of previous switching instances relative to zero crossing times of the current error signal during a previous excursion at least during half bridge switching mode, wherein when it is calculated that a desired zero crossing time of said current error signal will be overshot, said control circuit starts the inactive controller of said first and said second controllers to cause said inactive controller to operate when said desired zero crossing time has been overshot, to bring said current error signal rapidly to zero crossing.

Preferably when said inactive controller commences operation, both said first and said second controllers operate said switching regulator in plural half bridge switching mode until it is determined that a desired zero crossing time of said current error signal is reached early, whereafter half bridge switching mode operation of said switching regulator is resumed.

Both said first controller and said second controller could, in a preferred embodiment, be incorporated into a single controller with data swapping to enable smooth operation, or include a single processing means to perform calculations and determinations

Preferably said inactive controller operates from the previous zero crossing of the current error signal in a time from 0 5 target switching periods and not exceeding ten target switching periods when first activated in said plural half bridge switching mode Preferably said time lies from 0.52 to 2 times the target switching period.

Preferably said time lies from 0.54 to 1 times the target switching period.

Preferably said time lies from 0.56 to 0.75 times the target switching period.

Preferably said time lies from 0.6 to 0.64 times the target switching period.

Preferably said time is approximately 0.62 times the target switching period.

Preferably said switching regulator is a voltage source inverter.

Preferably said control circuit includes further controllers to switch between different positive and/or negative voltages across said inductor, operating with said first and second controllers. Such an arrangement would provide for varying current slopes across said inductor to further assist in achieving an average current error signal close to zero while maximising transient response and minimising ripple current in said inductor when a desired zero crossing time is not achieved in half bridge switching mode.

Thus in an embodiment with two controllers, it will be understood that when the behaviour of the current error polarity signal shows that one controller is insufficient, the other controller is turned on, and the switching regulator will operate in dual half bridge switching to drive the current error signal towards zero as required. Then when the behaviour of the current error polarity signal shows that both controllers together are no longer required, the appropriate one is turned off. In this way, the minimum current slopes are used normally to minimize the ripple current and the maximum current slope is provided when needed. The controller which is turned off after dual half bridge mode ceases is determined by which side of zero the current error signal has been on when it returns to zero early.

Preferably said current error signal is derived through said control circuit having a first input for receiving a current measurement signal proportional to the magnitude and direction of current in an inductor in said switching regulator, said control circuit having a reference current generating means for deriving a reference current signal representing the magnitude and direction of the desired current or current waveform in said inductor, where processing means determines the difference between said current measurement signal and said reference current signal to generate said current error signal representative of the difference or representative of the polarity of the difference.

In such an arrangement for either said first or second controller operating alone, said control circuit determines a next switching instant time relative to zero- crossing of said current error signal, based on a previous time of a previous said switching instant relative to zero-crossing of said current error signal

The determination of timing for a next switching instant from any zero crossing of the current error signal, may be based on switching instant timing relative to any previous excursion of the current error signal, but preferably for most accurate control is based on the switching instant timing relative to the immediate previous excursion of the current error signal. Basing the switching instant timing relative to any excursion of the current error signal more than three switching periods of the current error signal previous to the instant under determination would be expected to produce a noticeable lag in reaction of the control circuit to changing circuit parameters

Preferably, in either said first or second controller operating alone, in said control circuit the next switching instant timing is based on a previous switching instant timing during a current error signal excursion in a half period ending one current error signal zero crossing before the most recent current error signal zero crossing In this manner, the timing of switching instances is derived from the timing of the immediate previous switching instance from zero crossing of the current error signal, for the same polarity of current error signal (or in other words for the same side of zero)

Preferably, in either said first or second controller operating alone, said control circuit operates to switch a negative voltage across said inductor approximately when T = τ„Xf τ.. and operates to switch a positive voltage across said 2

inductor approximately when T_h , where

- T_ar is the calculated time when switching is to occur after the current error signal has crossed zero rising, - T_arp is the measured time the current error signal was above zero before a said previous switching instant (above zero and rising),

- T_a is the measured time the current error signal was above zero in a previous excursion,

- T_sw / 2 is the desired time between successive current error signal zero crossings (T_sw is the desired switching period),

- T f is the calculated time when switching is to occur after the current error signal has crossed zero falling,

- T_bfp is the measured time the current error signal was below zero before a said previous switching instant (below zero and falling), and - T_b is the measured time the current error signal was below zero in a previous excursion

Preferably, the first controller when operating in conjunction with the second controller in said control circuit operates to switch a positive voltage across said inductor with timing based on a previous switching instant timing relative to the current error signal crossing

Preferably the first controller when operating in conjunction with the second controller in said control circuit determines a next switching instant time relative to falling zero-crossing of said current error signal, based on a previous time of a previous said switching instant relative to falling zero-crossing of said current error signal

The determination of timing for a next switching instant from any falling zero crossing of the current error signal, may be based on switching instant timing relative to any previous excursion of the current error signal, but preferably for most accurate control is based on the switching instant timing relative to the immediate previous same-side excursion of the current error signal. Basing the switching instant timing relative to any excursion of the current error signal more than three switching periods of the current error signal previous to the instant under determination would be expected to produce a noticeable lag in reaction of the control circuit to changing circuit parameters.

Preferably, the first controller when operating in conjunction with the second controller in said control circuit the next switching instant timing is based on a previous switching instant timing during a negative current error signal excursion in a half period ending one current error signal zero crossing before the most recent current error signal zero crossing. In this manner, the timing of switching instances is derived from the timing of the immediate previous switching instance from falling zero crossing of the current error signal, for the same polarity of current error signal (or in other words for the same side of zero).

Preferably, the first controller when operating in conjunction with the second controller in said control circuit operates to switch a positive voltage across said

inductor approximately when T_h/ = , and operates to switch an

alternating or a negative voltage across said inductor approximately an amount of time not exceeding one quarter of the target switching period after the rising zero crossing of the current error signal, where:

- T_bf is the calculated time when switching is to occur after the current error signal has crossed zero falling, - T_bfp is the measured time the current error signal was below zero before a said previous switching instant (below zero and falling), and

- T is the measured time the current error signal was below zero in a previous excursion. Preferably said amount of time lies between 1 % and 15% of the target switching period

Preferably said amount of time lies between 2% and 10% of the target switching period

Preferably said amount of time lies from 3% to 4% of the target switching period

Preferably the second controller when operating in conjunction with the first controller in said control circuit operates to switch a negative voltage across said inductor with timing based on a previous switching instant timing relative to the current error signal zero crossing.

Preferably, the second controller when operating in conjunction with the first controller in said control circuit determines a next switching instant time relative to rising zero-crossing of said current error signal, based on a previous time of a previous said switching instant relative to rising zero-crossing of said current error signal

The determination of timing for a next switching instant from any rising zero crossing of the current error signal, may be based on switching instant timing relative to any previous excursion of the current error signal, but preferably for most accurate control is based on the switching instant timing relative to the immediate previous same-side excursion of the current error signal. Basing the switching instant timing relative to any excursion of the current error signal more than three switching periods of the current error signal previous to the instant under determination would be expected to produce a noticeable lag in reaction of the control circuit to changing circuit parameters.

Preferably, the second controller when operating in conjunction with the first controller in said control circuit the next switching instant timing is based on a previous switching instant timing during a positive current error signal excursion in a half period ending one current error signal zero crossing before the most recent current error signal zero crossing In this manner, the timing of switching instances is derived from the timing of the immediate previous switching instance from rising zero crossing of the current error signal, for the same polarity of current error signal (or in other words for the same side of zero).

Preferably, the second controller when operating in conjunction with the first controller in said control circuit operates to switch a negative voltage across said

inductor approximately when T_ar = , and operates to switch an

alternating voltage or a positive voltage across said inductor approximately an amount of time not exceeding one quarter of the target switching period after the falling zero crossing of the current error signal, where: - T_ar is the calculated time when switching is to occur after the current error signal has crossed zero rising,

- T_arp is the measured time the current error signal was above zero before a said previous switching instant (above zero and rising),

- T_sw / 2 is the desired time between successive current error signal zero crossings (T_sw is the desired switching period)

Preferably said amount of time not exceeding one quarter of the target switching period lies between 1% and 15% of the target switching period.

Preferably said amount of time not exceeding one quarter of the target switching period lies between 2% and 10% of the target switching period.

Preferably said amount of time not exceeding one quarter of the target switching period lies from 3% to 4% of the target switching period.

BRIEF DESCRIPTION OF THE DRAWINGS

An embodiment of the invention and several examples of its application will now be described in the following description, made with reference to the drawings, in which: Figure 1 is a schematic for a single phase full-bridge "voltage source inverter";

Figure 2 is a schematic for a voltage source inverter control circuit with inner current control loop; Figure 3 is a schematic for a dual ramptime inner current control loop;

Figure 4 is part of a flow chart for implementing a power supply according to the embodiment

Figure 5 is part of a flow chart for implementing a power supply according to the embodiment Figure 6 is part of a flow chart for implementing a power supply according to the embodiment

Figure 7 is part of a flow chart for implementing a power supply according to the embodiment

Figure 8 is a graph of waveforms illustrating dual ramptime operation; Figure 9 is a graph showing Kfn values;

Figure 10 is a graph of waveforms illustrating reactive current and voltage waveforms for a four quadrant voltage source inverter;

Figure 11 is a graph of waveforms illustrating current and voltage waveforms for a four quadrant voltage source inverter; Figure 12 is a graph of waveforms showing waveforms at voltage zero crossing for a four quadrant voltage source inverter;

Figure 13 is a graph of waveforms showing current harmonic spectrum for a four quadrant voltage source inverter;

Figure 14 is a graph of waveforms showing low order harmonics for a four quadrant voltage source inverter;

Figure 15 is a graph of waveforms showing current and voltage waveforms for diode rectifier active filtering;

Figure 16 is a graph of waveforms showing line current and voltage waveforms for diode rectifier active filtering; Figure 17 is a graph of waveforms showing current harmonic spectrum for diode rectifier active filtering;

Figure 18 is a graph of waveforms showing low order harmonics for diode rectifier active filtering; Figure 19 is a graph of waveforms showing line current and voltage waveforms showing the 13th harmonic reference;

Figure 20 is a graph of waveforms showing current and voltage waveforms with dual regulator operation; Figure 21 is a graph of waveforms showing current harmonic spectrum showing the 13th harmonic reference waveform;

Figure 22 is a graph of waveforms showing low order current harmonic spectrum showing the 13th harmonic reference;

Figure 23 is a graph of waveforms showing line currents and voltages in 12 pulse CSI active filtering;

Figure 24 is a graph of waveforms showing CC-VSI currents and voltages in 12 pulse CSI active filtering;

Figure 25 is a graph of waveforms showing current harmonics spectrum in 12 pulse CSI active filtering; and Figure 26 is a graph of waveforms showing low order harmonics in 12 pulse CSI active filtering.

BEST MODE(S) FOR CARRYING OUT THE INVENTION

The control circuit of the embodiment is hereafter referred to as dual ramptime current control, and comprises two ramptime current regulators operating together to provide optimum control of a single phase ac-dc bidirectional power converter.

In this description of the embodiment, the dual ramptime current control is applied to the full bridge voltage source inverter shown in Figure 1 . This technique can equally well be applied to any switching regulator.

One way to control the inverter in figure 1 is by using "full-bridge" or "bipolar" switching, however this technique results in a large ac current ripple. Dual polarized ramptime current control is a technique to provide full controllability and rapid transient response, while minimizing the ripple current through the use of "half-bridge", or "uni-polar", switching. By the expression "polarized", it is meant that the timing of switching instances is derived from the timing of the immediate previous switching instance from zero crossing of the current error signal, for the same polarity of current error signal (or in other words for the same side of zero). These concepts will be explained below along with a description of dual ramptime current control. The performance of the converters in following different reference waveforms is also discussed.

The current controlled voltage source inverter can be controlled with any outer power control loop which produces a current reference waveform. An inner current control loop with the dual ramptime current control is used to force the converter to follow the current reference waveform mentioned above. An example of the inner current control loop with an outer control loop providing the current reference is shown in figure 2. The output signals s_n control the four switches in the voltage source inverter as pulse-width-modulated signals.

Table of Voltages and Allowable Choices of Switch Position

In the voltage source inverter, each active switch and anti-parallel diode make a pair which are considered as one switch. Referring to the voltage source inverter in figure 1 , at any instant in time the allowable choices of switch position are shown in the above table. V_L is the voltage across the ripple inductor L_r.

From a control point of view, state 1 and state 4 are identical, since they both produce the same voltage across the inductor. These switch states are collectively referred to as switch state 0, or the zero state. Hence, there are three effective switch positions, and this voltage source inverter can be operated as a tπ-level inverter In such a tπ-level inverter, the zero state corresponds to the alternating voltage referred to heretofore

The simplest way to control the voltage source inverter is to use "full-bridge" switching which means that all four switches are switched between only two positions, state 2 and 3 State 0 is not used This results in the fastest transient response since the largest available voltage is always chosen, but the price is a large ripple current in the inductor

The next simplest way to control the VSI is to use "half-bridge" switching, where only one half bridge is switched while the other one is held constant for half a line period States 2 and 0 are used when the effective pwm voltage is meant to be positive, called "positive half-bridge switching" here States 3 and 0 are used when the effective pwm voltage is meant to be negative, called "negative half- bridge switching" here

Half-bridge switching produces much lower ripple current than full-bridge switching since the average voltage across the inductor is much lower However, when the ac voltage is near zero, it is not sufficient to overcome the diode voltage drops and drive the current Furthermore, the time to transfer from positive half-bridge switching to negative half-bridge switching is often chosen as the zero crossing of the ac voltage as this is simple to implement However, this is only the appropriate time to transfer if the slope of the current reference waveform is zero If not, which includes real power flow, choosing to transfer at the zero crossing of the ac voltage will result in some current distortion as the current becomes momentarily uncontrollable, and the transient response is further compromised.

In the embodiment, the control circuit for the current controlled voltage source inverter is able to choose half-bridge switching during normal operation to ensure that the ripple current is minimized, and then when rapid changes in the current reference signal require the maximum voltage across the inductor, or when it is uncertain if state 0 will produce the desired current slope, state 2 or 3 would be used judiciously Thus, dual ramptime current control according to the embodiment is intended to provide normal half-bridge switching, with dual half- bridge switching added when necessary, as described above

As shown in figure 3, in dual ramptime current control, two ramptime regulators are used to control the four switches to control the ac current The first controller in the form of J regulator provides an output to choose between state 0 and state 2, while the second controller in the form of K regulator chooses between state 0 and state 3 Most of the time, and as a preference, only one of the two regulators will be operating, providing half-bridge switching as described earlier However, when the behaviour of the current error polarity signal shows that one regulator is insufficient, the other regulator is turned on, and the third switching state used to drive the current error signal towards zero as required Then when the behaviour of the current error polarity signal shows that both regulators are no longer required, the appropriate one is turned off In this way, the minimum slopes are used normally to minimize the ripple current and the maximum current slope is provided when needed

The operation of the two regulators both individually and together is shown in the flowcharts in figures 3 to 7, which will now be described.

Referring to figure 4, when switching is initiated, the polarity of the current error signal determines which regulator will be turned on; the J regulator if the error signal "es" is below zero, or the K regulator if not. The switch position of the active regulator will then be set to "1 " which means that inverter will be placed into switch state 2 or state 3 respectively. The registered values of away and excursion times in the active regulator are then set to appropriate values so that the next two switching instants will occur shortly after each of the next two zero crossings of the current error signal. Then the procedure waits for the next zero crossing of the current error signal.

Referring to figure 5, J regulator solitary operation can begin at the falling edge of the current error signal when entering from dual operation, or at the rising edge of the current error signal when entering from an initialization At the falling edge of the current error signal, the value of the previous above zero error signal excursion time is captured for later use in determining switching instants, and counting of the new excursion time is started. Also, the normal process of determining the next switching instant using ramptime control is started. When that appropriate time for that switching instant is reached, swj is set to "1 " which will cause the inverter to go into switch state 2. At that instant, the value of the "below zero and falling" time is captured for later use in determining switching instants. Then the process waits for the rising zero crossing of the current error signal.

At the rising edge, the value of the previous below zero error signal excursion time is captured for later use in determining switching instants. Also immediately (and this is also the entry point from initialization) counting of the new excursion time is started, and the normal process of determining the next switching instant using ramptime control is started. When that appropriate time for that switching instant is reached, swj is set to "0" which will cause the inverter to go into switch state 0. At that instant, the value of the "above zero and rising" time is captured for later use in determining switching instants. Then the process waits for the falling zero crossing of the current error signal while monitoring the present excursion time. If that time exceeds a preset limit, the K regulator is turned on, and dual ramptime operation is started, entering at the "K ON" point in figure 7.

Referring to figure 6, K regulator solitary operation can begin at the rising edge of the current error signal when entering from dual operation, or at the falling edge of the current error signal when entering from an initialization.

At the rising edge of the current error signal, the value of the previous below zero error signal excursion time is captured for later use in determining switching instants, and counting of the new excursion time is started. Also, the normal process of determining the next switching instant using ramptime control is started. When the appropriate time for that switching instant is reached, swk is set to "1 " which will cause the inverter to go into switch state 3. At that instant, the value of the "above zero and rising" time is captured for later use in determining switching instants Then the process waits for the falling zero crossing of the current error signal

At the falling edge, the value of the previous above zero error signal excursion time is captured for later use in determining switching instants Also immediately (and this is also the entry point from initialization) counting of the new excursion time is started, and the normal process of determining the next switching instant using ramptime control is started When the appropriate time for that switching instant is reached, swk is set to "0" which will cause the inverter to go into switch state 0 At that instant, the value of the "below zero and falling" time is captured for later use in determining switching instants Then the process waits for the rising zero crossing of the current error signal while monitoring the present excursion time If that time exceeds a preset limit, the J regulator is turned on, and dual ramptime operation is started, entering at the "J ON" point in figure 7

Referring to figure 7 dual ramptime operation can begin at "K ON" when entering from solitary J regulator operation, or at "J ON" when entering from solitary K regulator operation.

At the falling edge of the current error signal, the value of the previous above zero error signal excursion time is captured for later use in determining switching instants, and counting of the new excursion time is started. Also, the normal process of determining the next J regulator switching instant using ramptime control is started. A short time (relative to the target switching period) after the falling edge of the current error signal, swk is set to "0" which will cause the inverter to go into switch state 0. If the error signal then crosses zero rising before the J regulator switching instant occurs, the J regulator is turned off and the process goes to "K only" operation. If the error signal has not crossed zero rising when the appropriate time for the ramptime determined J switching instant is reached, swj is set to "1 " which will cause the inverter to go into switch state 2. At that instant, the value of the "below zero and falling" time for the J regulator is captured for later use in determining switching instants. Then the process waits for the rising zero crossing of the current error signal At the rising edge, the value of the previous below zero error signal excursion time is captured for later use in determining switching instants. Also immediately counting of the new excursion time is started, and the normal process of determining the next K regulator switching instant using ramptime control is started. A short time (relative to the target switching period) after the rising edge of the current error signal, swj is set to "0" which will cause the inverter to go into switch state 0. If the error signal then crosses zero falling before the K regulator switching instant occurs, the K regulator is turned off and the process goes to "J only" operation. If the error signal has not crossed zero falling when the appropriate time for the ramptime determined K switching instant is reached, swk is set to "1 " which will cause the inverter to go into switch state 3. At that instant, the value of the "above zero and rising" time for the K regulator is captured for later use in determining switching instants. Then the process waits for the falling zero crossing of the current error signal.

A detailed explanation of the operation of dual ramptime is provided with the aid of figure 8. The current error signal is shown centered around zero, and the voltage across the inductor is shown reduced by a factor of 0.1 and offset by - 0.5. Prior to roughly the 9.5 millisecond point, the J regulator operates alone switching between state 0 and state 2. When one regulator is operating in a controllable region, it is generally successful in maintaining a relatively constant switching period. As the slope of the current error signal in state 0 decreases and the duty cycle approaches a minimum, the switching period will begin to extend. If while in state 0, the current error signal has not reached the zero crossing within a specified period of time, the second regulator will be turned on to immediately switch to bring the current error signal past the zero crossing. This occurs at roughly the 9.5 millisecond point in figure 8, where the K regulator is turned on and immediately switches to state 3. Thereafter, both regulators are operating, although in a modified manner.

Whenever both regulators are on, each is set to switch to state 0 a very short time after the respective zero crossing of the current error signal. The switching transition from state 0 to the full voltage state is determined using the normal ramptime function. In figure 8, during the dual regulator operation, the lower switching instant for the J regulator (from state 0 to state 2) occurs naturally, and the upper switching instant (from state 2 to state 0) is forced to occur quickly after the zero crossing of the current error signal. Likewise, the upper switching instant for the K regulator (from state 0 to state 3) occurs naturally, and the lower switching instant (from state 3 to state 0) is forced to occur quickly after the zero crossing of the current error signal.

During dual regulator operation, the two regulators do not disturb each other since each is operating primarily in state 0. The J regulator is in the middle of it's state 0 when the K regulator enters state 3 for a brief period of time. The J regulator is oblivious to the temporary change of state, and sees the current error signal zero crossing at roughly the correct time as expected. Likewise, the K regulator is in the middle of its state 0 when the J regulator enters state 2 for a brief period of time, and the K regulator is oblivious to this temporary change of state. Logic is put in place to ensure that at least one of the regulators is always in state 0, although this is generally unnecessary.

After the current error signal slope in state 0 becomes large enough that single regulator controllability is likely, dual regulator operation is ended in a simple manner. If the current error signal crosses zero before the appropriate regulator has switched, that regulator operation is no longer necessary, so it is turned off. Thereafter, normal operation with one remaining regulator continues. A normal sequence would see dual regulator operation result in a transfer of control from one regulator to the other as the zero state current error signal slope moved through zero. However, a relatively quickly changing current reference waveform could temporarily cause dual regulator operation in the middle of normal single regulator operation, so the behaviour of the current error signal alone is used to determine when each regulator operates.

It is apparent in figure 8 that zero average current error is only achieved during dual regulator operation when the zero state current error signal slope is zero. The effect of the finite average current error is not significant though, as will be shown in the simulations which follow.

The "state selection logic" block in figure 3 routes the current regulator outputs to the appropriate switches to produce the appropriate states. To produce state 0, thermal considerations in the voltage source inverter design would generally dictate that state 1 and state 4 be chosen an equal amount of time, resulting in equal rms currents in each switch. This can be achieved by alternating between the two states each time state 0 is desired.

The power circuit is designed at a certain current rating and minimum and maximum ac and dc voltages. The main passive component value which needs to be determined is the ripple inductance. The choice of inductance, the magnitude of the dc link voltage, and the switching frequency contribute to determine the ripple current. The relationship between the three can be expressed in terms of a parameter K_f defined here:

where I, is the ripple current in the inductor f_sw is the switching frequency in Hz, and X_r is the impedance of the ripple inductor

Kfi, is a fixed "per unit" value for a specific converter topology, dc voltage, control method, and to a minor extent, the current reference waveform. The minor effect of the current reference waveform can be ignored, so K need only be determined for specific dc voltages. Figure 9 shows approximate values of K_fll versus V_dc for the specified control techniques for the current controlled voltage source inverter in Figure 1 operating with a fundamental real inverting sinusoidal current reference. These K_fll values were determined through test cases simulated using ATP-EMTP ("Alternative Transients Program Rule Book", K U Leuven, EMTP Center (LEC), Belgium). It is apparent that the dual ramptime control has only marginally greater K_fil values than half-bridge switching, despite having the full controllability and transient response of full-bridge switching.

In converter design, often the first parameter to be determined is the acceptable current ripple at the switching frequency. Low order current harmonics can be eliminated with an appropriate current reference generator and current regulator. Therefore, the switching frequency ripple current will be the most significant contributor and most of the allowable current THD can be budgeted for the switching ripple current.

The next parameter to be determined is the switching frequency. Given a target ripple current, the choice of switching frequency is a trade-off between inductor size (and cost), and switching losses. This is essentially a choice between initial cost and operating costs, and will be specific to each project. A strong consideration in the choice of switching frequency is often the audible noise from the inverter. For those applications where noise is an issue, the minimum switching frequency should be approximately 18 kHz.

With the ripple current and switching frequency chosen, the ripple inductance can now be determined. A value for K_fι, is chosen from the graph in figure 9 based on the highest dc voltage at which the ripple current specification must be met. The inductor impedance is then determined from the above formula, rearranged below:

x . - ^κ " i r J f sw

The procedure above was followed with four example applications of dual ramptime current regulation according to the embodiment, presented with increasingly onerous current reference waveforms. Circuit parameters are chosen, and the performance of the regulator in following the reference waveforms is shown as simulated using ATP. In these simulations, all diode to switch transitions are delayed by 2 microseconds, as would occur in a standard voltage source inverter due to anti-shoot through logic.

The first application is a four quadrant inverter/rectifier. A ripple current of 4% was chosen with the intention to end up with a total current THD below 5%, and a switching frequency of 10 kHz was chosen so as produce acceptable switching losses. A fixed dc voltage was required, with a clearance of 0.08 pu for ac voltage fluctuations, 0.07 pu for reactive power capability and 0.07 pu for duty cycle requirements, for a total of 0.22 pu over the nominal ac voltage. Km was read from the graph in figure 9 and the inductor impedance was then calculated using the formula above. With ω equal to 100π (f = 50 Hz), the ripple inductance L_r was then determined. The chosen and determined parameter values are:

Xr = 0.070 pu L_r = 223 uH

Figure 10 shows the inductor current riding on top of the reactive current reference waveform, with the current error signal along the zero axis, and the line voltage. The lower waveform is the voltage across the ripple inductance, offset by -2 pu and multiplied by 0.2.

Figure 11 shows the inductor current riding on top of the real current reference waveform, with the current error signal along the zero axis, and the line voltage inverted. The lower waveform is the voltage across the ripple inductance, offset by -2 pu and multiplied by 0.2. In both figures 10 and 11 , the periods where both ramptime regulators are active are apparent near the zero crossing of the line voltage.

Figure 12 shows an expanded section of figure 11 between 9 and 11 milliseconds, but with the current error signal multiplied by 5 and offset by -1. The period when both ramptime regulators operate is apparent. During dual operation, the average current error within a switching period will be offset from zero by up to half the zero state current error signal slope multiplied by the zero state duty cycle multiplied by the switching period. From the start of dual regulator control to the end, the current error signal has an average value in any one switching period moving from slightly negative to slightly positive. This is due to the state 0 current error signal slope moving from negative to positive, and has a negligible effect on the current harmonics.

Figure 13 shows the current harmonic spectrum of the inductor current up to above twice the switching frequency. The narrow switching frequency band is apparent. The spectrum in figure 14 shows the low order harmonics, verifying that no significant low order harmonics are generated due to the dual current regulator operation. The inductor current has a THD of 4.0% as intended.

The second application is in an ac power distribution circuit where there are many diode rectifier loads (feeding loads such as switch-mode power supplies for computers and/or communications equipment, or adjustable speed drives), a pulsed current is drawn with a very high content of low order harmonics. The load capacity of the circuit, which is limited by the rms current rating, could be increased if the harmonic currents were eliminated. A dual ramptime controlled active filter is simulated in this application to remove the harmonic currents.

A current controlled voltage source inverter intended for use in this more demanding system, requires a faster current slew rate. This must be accomplished by using a smaller inductance and/or a greater dc link voltage. This means that a higher ripple current must be tolerated, although a higher switching frequency will help to mitigate the problem. Also, audible noise is a consideration, so a switching frequency above the average human hearing range is chosen. This current controlled voltage source inverter will have greater switching losses and require better heat-sinking than the previous current controlled voltage source inverter. The chosen and determined parameter values are:

i_r* = 0.050 pu f_sw* = 18 kHz

V_dc = 2.00 pu Km = 39

X_r = 0.043 pu L_r = 138 uH ln this application, the current reference waveform is the load current minus the desired sinusoidal line current. This waveform consists solely of the harmonic currents drawn by the load, and is intended to result in the line current being predominantly fundamental.

Figure 15 shows the inductor current riding on top of the reference waveform, the line voltage, the current error signal offset by -3 pu and multiplied by 5, and the voltage across the ripple inductance, offset by -5 pu and multiplied by 0.2. Dual regulator operation is required at the end of each of the load current pulses due to the higher reference current slope.

Figure 16 shows the line voltage, the load current, and the line current that would be drawn from an AC line with no impedance. This demonstrates the ability of the current regulation alone, without line impedance generated harmonics coloring the results.

The line current harmonic spectrum up to above twice the switching frequency is shown in figure 17. Again, a narrow switching frequency band is apparent. The line current in figure 16 has a THD of 4.8%, composed mostly of the switching frequency harmonic bands. This is close to the intended design ripple current content. The spectrum in figure 18 shows no low order harmonics, verifying that there are no significant steady-state or transient errors in the current regulation.

The third application is in a current controlled voltage source inverter intended for use in a more demanding system like a UPS where it may have to take over the load current from the grid in a fraction of a millisecond. This is similar to the last case, but a faster current slew rate is required, so a higher ripple current must be tolerated. Again, audible noise is a consideration. The chosen and determined parameter values are: lr* = 0.060 pu f * = 18 kHz

Xr = 0.036 pu Lr = 1 15 uH

In this application, the current reference waveform will take many forms, and could vary continuously. The aspect under study is the current regulation with an onerous reference, and the ability to shift rapidly at any point in the line cycle is important. While a reference current waveform consisting solely of the 13th harmonic is normally unlikely, using this reference waveform shows the accuracy with which the current controlled voltage source inverter could follow a desired reference at any point in the line cycle, and demonstrates the effectiveness of the current regulation.

Figure 19 shows the inductor current riding on top of the 13th harmonic current reference waveform, with the current error signal along the zero axis, and the line voltage shown. The lower waveform is the voltage across the ripple inductance, offset by -2 pu and multiplied by 0.2.

Periods when dual regulator operation is required are more frequent, allowing the current reference to be followed accurately. Points in time where the current slope is not quite able to match the reference waveform slope are near the 4.5 and 14.5 millisecond times where the current error signal remains on one side of zero and the voltage across the inductor is held constant. This could be improved by increasing the dc voltage, but the price would be increased ripple current. The inductor current has a THD of 5.9% (using 650 Hz as the fundamental), which is close to the target.

Figure 20 shows an expanded section of figure 19 between 8 and 12 milliseconds, but with the current error signal multiplied by 5. Again the current error signal is generally well centered around zero. The small average current error which can occur during dual regulator operation is apparent near the 8.5 millisecond mark. However the error is small (approximately 0.02 pu = 0.1 x 0.2). This is due to the state 0 current error slope being predominantly negative as control of the current transfers from the J regulator, to both, and then back to the J regulator instead of proceeding from one regulator to the other as would occur with a more constant current reference waveform.

Figure 21 shows the current harmonic spectrum of the inductor current up to above twice the switching frequency. The switching frequency band is still relatively narrow. The spectrum in figure 22 shows the low order harmonics.

The final example is a current controlled voltage source inverter intended to filter the harmonics currents from one phase of a 12 pulse thyristor switched current source inverter (CSI). The intention is to use a small current controlled voltage source inverter to remove the low order harmonics generated by a 12 pulse CSI (1 1 th, 13th, 23rd, 25th, etc.) and bring the whole current THD below 8%. The tricky part of this application is a requirement to be able to handle line notches as short as 100 microseconds, which means that the current reference waveform will make large shifts in that time period. Therefore, a fast current slew rate is required, which will be accomplished by increasing the dc link voltage. The switching frequency will need to be kept high to meet the conflicting requirements of a fast slew rate and a low ripple current. The chosen and determined parameter values are as shown here:

ir* = 0.060 pu f_sw* = 18 kHz

V_dc = 2.50 pu K_fn = 49

X_r = 0.045 pu L_r = 144 uH

In this application, the current reference waveform is the CSI phase current minus the desired sinusoidal line current. This waveform consists solely of the harmonic currents drawn by the CSI, and is intended to result in the line current being predominantly fundamental. The CSI phase current waveform was constructed as described on page 389 of Mohan, Undeland and Robbins, "Power Electronics, Converters, Applications, and Design, First Ed., John Wiley & Sons, Toronto, 1989. Figure 23 shows the line voltage, the inverted load current, and the line current drawn from an ac line with no impedance. Again, this is intended to demonstrate the ability of the current regulation alone, without line impedance generated harmonics coloring the results. Figure 24 shows, from top to bottom, the reference waveform offset by 1.0 pu, the inductor current along the zero axis, the current error signal offset by -1.0 pu and multiplied by 2, and the voltage across the ripple inductance, offset by -2.0 pu and multiplied by 0.2. Dual regulator operation is required each time the current reference waveform jumps. The line current harmonic spectrum up to above twice the switching frequency is shown in figure 25. Again, a narrow switching frequency band is apparent. The line current in figure 23 has a THD of 6.34%, of which 6.10% is contributed by frequencies above 10 kHz. This is close to the intended design ripple current content. The harmonics below 10 kHz which contribute 0.24% to the THD are attributable to tracking errors in the current regulation, and are not significant. The spectrum in figure 26 shows the low order harmonics still quite low, verifying that there are only insignificant steady-state or transient errors in the current regulation.

It will be understood that the circuit can be implemented using PLDs (programmable logic devices), or any digital signal processing means, or analog circuitry. It will also be appreciated that while the example has been given in relation to a single phase power converter, it will be understood that the a number of control circuits according to the invention can be used to control current in a number of inductors in a multiphase power converter.

It should be appreciated that the scope of the invention is not limited to the particular examples given here.

Claims

THE CLAIMS DEFINING THE INVENTION ARE AS FOLLOWS

1. A control circuit for a switching regulator having an inductor, said control circuit having a first controller to switch between a positive voltage and an alternating voltage across said inductor, and a second controller to switch between a negative voltage and said alternating voltage across said inductor, where said first controller and said second controller normally alternate to operate said switching regulator in half-bridge switching mode to produce a current waveform in said inductor; where the timing of switching instants is calculated to achieve an average current error signal close to or near zero, based on timing of previous switching instances relative to zero crossing times of the current error signal during a previous excursion at least during half bridge switching mode; wherein when it is calculated that a desired zero crossing time of said current error signal will be overshot, said control circuit starts the inactive controller of said first and said second controllers to cause said inactive controller to operate when said desired zero crossing time has been overshot, to bring said current error signal rapidly to zero crossing.

2. A control circuit as claimed in claim 1 wherein on said inactive controller commencing operation, both said first and said second controllers operate said switching regulator in plural half bridge switching mode until it is determined that a desired zero crossing time of said current error signal is reached early, whereafter half bridge switching mode operation of said switching regulator is resumed.

3. A control circuit as claimed in claim 1 or 2 wherein said inactive controller operates from the previous zero crossing of the current error signal in a time from 0.5 target switching periods and not exceeding ten target switching periods when first activated in said plural half bridge switching mode.

4. A control circuit as claimed in claim 4 wherein said time lies from 0.52 to 2 times the target switching period.

5. A control circuit as claimed in claim 4 wherein said time lies from 0.54 to 1 times the target switching period.

6. A control circuit as claimed in claim 4 wherein said time lies from 0.56 to 0.75 times the target switching period.

7. A control circuit as claimed in claim 4 wherein said time lies from 0.6 to 0.64 times the target switching period.

8. A control circuit as claimed in claim 4 wherein said time is approximately 0.62 times the target switching period.

9. A control circuit as claimed in any one of the preceding claims wherein said current error signal is derived through said control circuit having a first input for receiving a current measurement signal proportional to the magnitude and direction of current in an inductor in said switching regulator; said control circuit having a reference current generating means for deriving a reference current signal representing the magnitude and direction of the desired current or current waveform in said inductor; where processing means determines the difference between said current measurement signal and said reference current signal to generate said current error signal representative of the difference or representative of the polarity of the difference.

10. A control circuit as claimed in any one of the preceding claims wherein, in either said first or second controller operating alone, in said control circuit the next switching instant timing is based on a previous switching instant timing during a current error signal excursion in a half period ending one current error signal zero crossing before the most recent current error signal zero crossing.

11. A control circuit as claimed in claim 10 wherein, in either said first or second controller operating alone, said control circuit operates to switch a negative voltage across said inductor approximately when T_ar

operates to switch a positive voltage across said inductor approximately

- T_ar is the calculated time when switching is to occur after the current error signal has crossed zero rising,

- T_a is the measured time the current error signal was above zero in a previous excursion, - T_sw / 2 is the desired time between successive current error signal zero crossings (T_sw is the desired switching period),

- T_bf is the calculated time when switching is to occur after the current error signal has crossed zero falling,

- T_bfp is the measured time the current error signal was below zero before a said previous switching instant (below zero and falling), and

- T_b is the measured time the current error signal was below zero in a previous excursion.

12. A control circuit as claimed in any one of the preceding claims wherein, the first controller when operating in conjunction with the second controller in said control circuit operates to switch a positive voltage across said inductor with timing based on a previous switching instant timing relative to the current error signal crossing.

13. A control circuit as claimed in claim 12 wherein, the first controller when operating in conjunction with the second controller in said control circuit operates to switch a positive voltage across said inductor approximately τ Λ when T_hf = ^lbfp (τ

-^ ] , and operates to switch an alternating voltage

across said inductor approximately an amount of time not exceeding one quarter of the target switching period after the rising zero crossing of the current error signal, where:

- T_sw / 2 is the desired time between successive current error signal zero crossings (T_sw is the desired switching period), - T f is the calculated time when switching is to occur after the current error signal has crossed zero falling,

- T fp is the measured time the current error signal was below zero before a said previous switching instant (below zero and falling), and

14. A control circuit as claimed in claim 13 wherein said amount of time lies between 1 % and 15% of the target switching period.

15. A control circuit as claimed in claim 13 wherein said amount of time lies between 2% and 10% of the target switching period.

16. A control circuit as claimed in claim 13 wherein said amount of time lies from 3% to 4% of the target switching period.

17. A control circuit as claimed in any one of the preceding claims wherein, the second controller when operating in conjunction with the first controller in said control circuit operates to switch a negative voltage across said inductor with timing based on a previous switching instant timing relative to the current error signal zero crossing.

18. A control circuit as claimed in claim 17 wherein, the second controller when operating in conjunction with the first controller in said control circuit operates to switch a negative voltage across said inductor approximately τ_arX( τ, when r. = and operates to switch an alternating voltage

across said inductor approximately an amount of time not exceeding one quarter of the target switching period after the falling zero crossing of the current error signal, where: - T_ar is the calculated time when switching is to occur after the current error signal has crossed zero rising,

- T_arp is the measured time the current error signal was above zero before a said previous switching instant (above zero and rising), - T_a is the measured time the current error signal was above zero in a previous excursion,

- T_sw / 2 is the desired time between successive current error signal zero crossings (T_sw is the desired switching period).

19. A control circuit as claimed in claim 18 wherein said time not exceeding one quarter of the target switching frequency lies between 1% and 15% of the target switching frequency.

20. A control circuit as claimed in claim 18 wherein said time not exceeding one quarter of the target switching frequency lies between 2% and 10% of the target switching frequency.

21. A control circuit as claimed in claim 18 wherein said time not exceeding one quarter of the target switching frequency lies between 3% and 4% of the target switching frequency.

22. A control circuit as claimed in any one of the previous claims wherein said first controller and said second controller are incorporated into a single controller with data swapping to enable smooth operation.

23. A control circuit as claimed in any one of the preceding claims including further controllers to switch between different positive and/or negative voltages across said inductor, operating with said first and second controllers.

24. A control circuit for a switching regulator, substantially as herein described with reference to the description of the embodiment and drawings.