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WO2001024517A1 - Procede et appareil de derivation d'un sous-systeme graphique - Google Patents

Procede et appareil de derivation d'un sous-systeme graphique Download PDF

Info

Publication number
WO2001024517A1
WO2001024517A1 PCT/US1999/022305 US9922305W WO0124517A1 WO 2001024517 A1 WO2001024517 A1 WO 2001024517A1 US 9922305 W US9922305 W US 9922305W WO 0124517 A1 WO0124517 A1 WO 0124517A1
Authority
WO
WIPO (PCT)
Prior art keywords
digital
video
analog
signal
graphics
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US1999/022305
Other languages
English (en)
Inventor
David E. Zeidler
Robert M. Simons
Joseph A. Petry
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Arris Technology Inc
Original Assignee
General Instrument Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by General Instrument Corp filed Critical General Instrument Corp
Priority to PCT/US1999/022305 priority Critical patent/WO2001024517A1/fr
Priority to DE19983982T priority patent/DE19983982T1/de
Priority to AU61635/99A priority patent/AU6163599A/en
Priority to GB0207050A priority patent/GB2370444B/en
Priority to CNB99816920XA priority patent/CN1164093C/zh
Priority to BR9917505-3A priority patent/BR9917505A/pt
Publication of WO2001024517A1 publication Critical patent/WO2001024517A1/fr
Priority to US10/107,346 priority patent/US7116377B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/41—Structure of client; Structure of client peripherals
    • H04N21/426—Internal components of the client ; Characteristics thereof
    • H04N21/42653—Internal components of the client ; Characteristics thereof for processing graphics
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/434—Disassembling of a multiplex stream, e.g. demultiplexing audio and video streams, extraction of additional data from a video stream; Remultiplexing of multiplex streams; Extraction or processing of SI; Disassembling of packetised elementary stream
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/41—Structure of client; Structure of client peripherals
    • H04N21/426—Internal components of the client ; Characteristics thereof
    • H04N21/42607—Internal components of the client ; Characteristics thereof for processing the incoming bitstream
    • H04N21/4263—Internal components of the client ; Characteristics thereof for processing the incoming bitstream involving specific tuning arrangements, e.g. two tuners
    • H04N21/42638—Internal components of the client ; Characteristics thereof for processing the incoming bitstream involving specific tuning arrangements, e.g. two tuners involving a hybrid front-end, e.g. analog and digital tuners
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
    • H04N5/46—Receiver circuitry for the reception of television signals according to analogue transmission standards for receiving on more than one standard at will

Definitions

  • the present invention relates to cable television (CATV) systems. More
  • the present invention pertains to a method and apparatus for bypassing
  • the graphics are typically laid over a video signal received
  • a separate remote source such as a broadcast television transmission, a video
  • phase lock loop (PLL) circuit uses phase lock loop (PLL) circuit to generate a reference clock
  • changeover signal generator generates changeover control signals to output only the
  • sub-carrier which includes a sub-carrier phase locked loop, a digital character
  • phase locked loop separately generates a color sub-carrier and a system clock signal
  • digital video encoder is responsive to the color sub-carrier and system clock signals
  • the switching means directs the analog video output signal from the digital
  • subsystem bypass circuit is provided for passing inbound analog video source signals
  • Figure 1 is a block diagram of a system containing a graphics subsystem
  • Figure 2 is a flow diagram for the operation of the system in Figure 1.
  • tuner 12 coupled to a cable input from a community antenna television
  • a switch 14 is coupled to the output of the tuner 12. It should be appreciated
  • switch 14 may optionally
  • demodulator 16 is coupled to the first switch output 15 along the analog video path
  • channel video demodulator 16 may also optionally include a descrambler in systems
  • a digital channel demodulator 18 is coupled to the second switch output 17
  • the digital channel demodulator 18 may optionally include a decryptor
  • OSD graphics subsystem 40 Also included in the OSD graphics subsystem 40 is an OSD insertion
  • subsystem 40 including the A/D convertor 42, the switch 43, the OSD insertion unit
  • a graphics bypass switch 24 having two inputs 56, 54, is coupled to the OSD
  • Video output 60 is provided from the graphics bypass switch output 58.
  • Memory 52
  • an input channel from the tuner 12 is split or switched.
  • the memory 52 contains OSD graphics image information in digital
  • the switch 14 directs the selected channel to the analog channel video demodulator 16 through the analog video path 19 or to a digital channel
  • the digital channel typically contains MPEG
  • each of these channels may carry other information content in the form of analog and
  • the analog channel video demodulator 16 serves to demodulate the analog
  • channel and also optionally serves to descramble any scrambled analog video signal.
  • a demodulated analog video signal is fed from the analog channel video
  • the digital channel demodulator 18 serves to demodulate the digital channel
  • a demodulated digital signal may be demodulated
  • the MPEG decoder 20 serves to decode the MPEG
  • the digital video signal coming from the MPEG decoder 20 is fed to the MPEG decoder 20 .
  • the switch 43 is operated by the microprocessor 26 to feed the A/D converted video signal to the OSD insertion unit 44 during selected time
  • the switch 43 is also
  • MPEG decoder 20 to the OSD insertion unit 44 during other selected time intervals
  • the OSD insertion unit 44 combines the digital video signal from the digital
  • composite signal is then fed to the D/A convertor 46 for conversion to an analog
  • bypass path 22 serves to pass the analog
  • the analog video signal may be passed directly to a video output 60 without degradation experienced

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Computer Graphics (AREA)
  • Studio Circuits (AREA)
  • Controls And Circuits For Display Device (AREA)

Abstract

L'invention concerne un sous-système graphique d'affichage à l'écran permettant la superposition d'images graphiques s'affichant à l'écran sur des signaux de source vidéo analogiques ou numériques. Le système graphique d'affichage à l'écran comporte un trajet de dérivation (22) graphique vidéo et un commutateur de dérivation (24) graphique permettant de diriger un canal vidéo analogique autour du sous-système graphique d'affichage à l'écran pendant des intervalles de temps lorsque ledit sous-système n'a pas à insérer un graphique dans le signal de source.
PCT/US1999/022305 1999-09-27 1999-09-27 Procede et appareil de derivation d'un sous-systeme graphique Ceased WO2001024517A1 (fr)

Priority Applications (7)

Application Number Priority Date Filing Date Title
PCT/US1999/022305 WO2001024517A1 (fr) 1999-09-27 1999-09-27 Procede et appareil de derivation d'un sous-systeme graphique
DE19983982T DE19983982T1 (de) 1999-09-27 1999-09-27 Verfahren und Vorrichtung zur Umgehung eines grafischen Subsystems
AU61635/99A AU6163599A (en) 1999-09-27 1999-09-27 Graphics subsystem bypass method and apparatus
GB0207050A GB2370444B (en) 1999-09-27 1999-09-27 Graphics subsystem bypass method and apparatus
CNB99816920XA CN1164093C (zh) 1999-09-27 1999-09-27 图形子系统旁路方法和设备
BR9917505-3A BR9917505A (pt) 1999-09-27 1999-09-27 Subsistema gráfico de vìdeo, e, método para inserir sinais gráficos intermitentes em um sinal de vìdeo analógico
US10/107,346 US7116377B2 (en) 1999-09-27 2002-03-26 Graphics subsystem bypass method and apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US1999/022305 WO2001024517A1 (fr) 1999-09-27 1999-09-27 Procede et appareil de derivation d'un sous-systeme graphique

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US10/107,346 Continuation US7116377B2 (en) 1999-09-27 2002-03-26 Graphics subsystem bypass method and apparatus

Publications (1)

Publication Number Publication Date
WO2001024517A1 true WO2001024517A1 (fr) 2001-04-05

Family

ID=22273689

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1999/022305 Ceased WO2001024517A1 (fr) 1999-09-27 1999-09-27 Procede et appareil de derivation d'un sous-systeme graphique

Country Status (6)

Country Link
CN (1) CN1164093C (fr)
AU (1) AU6163599A (fr)
BR (1) BR9917505A (fr)
DE (1) DE19983982T1 (fr)
GB (1) GB2370444B (fr)
WO (1) WO2001024517A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1450557A3 (fr) * 2003-02-21 2004-09-22 Lg Electronics Inc. Dispositif et procédé d'affichage d'une image OSD dans un appareil vidéo combiné

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7075543B2 (en) * 2003-07-08 2006-07-11 Seiko Epson Corporation Graphics controller providing flexible access to a graphics display device by a host
US6985152B2 (en) * 2004-04-23 2006-01-10 Nvidia Corporation Point-to-point bus bridging without a bridge controller

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0701367A2 (fr) * 1994-09-09 1996-03-13 Thomson Consumer Electronics, Inc. Interface pour guide de programme
US5541666A (en) * 1994-07-06 1996-07-30 General Instrument Method and apparatus for overlaying digitally generated graphics over an analog video signal
US5638112A (en) * 1995-08-07 1997-06-10 Zenith Electronics Corp. Hybrid analog/digital STB
GB2326551A (en) * 1997-05-30 1998-12-23 Daewoo Electronics Co Ltd On screen display signal mixing

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5541666A (en) * 1994-07-06 1996-07-30 General Instrument Method and apparatus for overlaying digitally generated graphics over an analog video signal
EP0701367A2 (fr) * 1994-09-09 1996-03-13 Thomson Consumer Electronics, Inc. Interface pour guide de programme
US5638112A (en) * 1995-08-07 1997-06-10 Zenith Electronics Corp. Hybrid analog/digital STB
GB2326551A (en) * 1997-05-30 1998-12-23 Daewoo Electronics Co Ltd On screen display signal mixing

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1450557A3 (fr) * 2003-02-21 2004-09-22 Lg Electronics Inc. Dispositif et procédé d'affichage d'une image OSD dans un appareil vidéo combiné
CN1527594B (zh) * 2003-02-21 2010-04-28 Lg电子株式会社 用于在混合视频设备中显示屏幕显示图像的装置和方法

Also Published As

Publication number Publication date
GB2370444A (en) 2002-06-26
CN1164093C (zh) 2004-08-25
AU6163599A (en) 2001-04-30
GB0207050D0 (en) 2002-05-08
CN1367979A (zh) 2002-09-04
DE19983982T1 (de) 2002-12-05
GB2370444B (en) 2003-10-08
BR9917505A (pt) 2002-06-04

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