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WO2001020649A1 - Reduction du couplage entre un substrat semiconducteur et une bobine integree sur ce dernier - Google Patents

Reduction du couplage entre un substrat semiconducteur et une bobine integree sur ce dernier Download PDF

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Publication number
WO2001020649A1
WO2001020649A1 PCT/DE2000/003100 DE0003100W WO0120649A1 WO 2001020649 A1 WO2001020649 A1 WO 2001020649A1 DE 0003100 W DE0003100 W DE 0003100W WO 0120649 A1 WO0120649 A1 WO 0120649A1
Authority
WO
WIPO (PCT)
Prior art keywords
trenches
coil
surface area
substrate
filled
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/DE2000/003100
Other languages
German (de)
English (en)
Inventor
Wolfgang Klein
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of WO2001020649A1 publication Critical patent/WO2001020649A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/20—Inductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the invention relates to a semiconductor integrated circuit having on a first surface region of a substrate disposed trenches and having disposed over a second surface area coil, the trenches filled with an insulating material and in comparison with the size of the second l surface region are narrow.
  • the invention further relates to a method for producing an integrated semiconductor circuit, in which trenches are arranged on a first surface area of a substrate and a coil is formed over a second surface area, which coil is narrow compared to the size of the second surface area, and wherein Trenches can be filled with an insulating material.
  • This isolator is deposited isotropically and is deposited in the deep but narrow trenches on the bottom and on the sides at the same time.
  • the trenches are closed by lateral growth, the layer thickness of the insulator to be deposited only having to slightly exceed half the width of the trench.
  • the substrate area below the coil is provided with a grid or network of isolated or interconnected narrow trenches, which are first etched and then filled by isotropic deposition.
  • the insulator to be introduced would have to be filled from the bottom over the entire etching depth, it is sufficient to fill up the trench structure according to the invention, which is formed from narrow trenches, by depositing a layer with a thickness of half a trench width.
  • a relatively deep area below the coil is additionally filled with an insulator.
  • the trench structure is a line grid of parallel trenches or a network of intersecting trenches.
  • FIGS. 2a and 2b show, by way of example, two trench structures that can be easily produced from a grid of parallel trenches or a network of intersecting trenches.
  • the structuring of substrate areas below coils is not only suitable, but in particular in the case of integrated semiconductor circuits which contain narrow, isotropically filled trenches in order to isolate their components.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)

Abstract

L'invention concerne un circuit intégré à semiconducteurs et un procédé pour produire ce dernier, consistant à réaliser des tranchées sur une première zone superficielle d'un substrat (1) et à former une bobine (2) sur une deuxième zone superficielle. Les tranchées sont étroites, par rapport à la taille de la deuxième zone superficielle, et sont remplies d'un matériau isolant. Avant la formation de la bobine, une structure constituée de tranchées étroites supplémentaires (3) est formée par attaque dans le substrat, dans la deuxième zone superficielle, et remplie de matériau isolant, en même temps que les tranchées étroites de la première zone superficielle, par dépôt isotrope. De préférence, les tranchées de la première zone superficielle et la structure de tranchées sont produites simultanément par attaque. On obtient ainsi, sans effort supplémentaire, une structure remplie d'un diélectrique isolant, sous la bobine, qui réduit le couplage entre cette dernière et le substrat.
PCT/DE2000/003100 1999-09-15 2000-09-07 Reduction du couplage entre un substrat semiconducteur et une bobine integree sur ce dernier Ceased WO2001020649A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19944306A DE19944306B4 (de) 1999-09-15 1999-09-15 Integrierte Halbleiterschaltung mit integrierter Spule und Verfahren zu deren Herstellung
DE19944306.8 1999-09-15

Publications (1)

Publication Number Publication Date
WO2001020649A1 true WO2001020649A1 (fr) 2001-03-22

Family

ID=7922170

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2000/003100 Ceased WO2001020649A1 (fr) 1999-09-15 2000-09-07 Reduction du couplage entre un substrat semiconducteur et une bobine integree sur ce dernier

Country Status (2)

Country Link
DE (1) DE19944306B4 (fr)
WO (1) WO2001020649A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002017399A1 (fr) * 2000-08-24 2002-02-28 Infineon Technologies Ag Dispositif a semi-conducteurs et son procede de production
CN114823638A (zh) * 2022-04-27 2022-07-29 电子科技大学 一种低寄生电容集成电感结构

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997045873A1 (fr) * 1996-05-31 1997-12-04 Telefonaktiebolaget Lm Ericsson Conducteurs pour circuits integres
US5742091A (en) * 1995-07-12 1998-04-21 National Semiconductor Corporation Semiconductor device having a passive device formed over one or more deep trenches
JPH10144784A (ja) * 1996-11-11 1998-05-29 Nec Corp 半導体装置及びその製造方法
DE19847440A1 (de) * 1997-12-22 1999-06-24 Inst Halbleiterphysik Gmbh Integrierte Schaltung mit verringerten parasitären kapazitiven Einflüssen und Verfahren zu ihrer Herstellung
JPH11233727A (ja) * 1997-12-27 1999-08-27 Korea Electronics Telecommun シリコン基板上のインダクタ装置及びその製造方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5717243A (en) * 1996-04-24 1998-02-10 Harris Corporation Integrated circuit with an improved inductor structure and method of fabrication

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5742091A (en) * 1995-07-12 1998-04-21 National Semiconductor Corporation Semiconductor device having a passive device formed over one or more deep trenches
WO1997045873A1 (fr) * 1996-05-31 1997-12-04 Telefonaktiebolaget Lm Ericsson Conducteurs pour circuits integres
JPH10144784A (ja) * 1996-11-11 1998-05-29 Nec Corp 半導体装置及びその製造方法
DE19847440A1 (de) * 1997-12-22 1999-06-24 Inst Halbleiterphysik Gmbh Integrierte Schaltung mit verringerten parasitären kapazitiven Einflüssen und Verfahren zu ihrer Herstellung
JPH11233727A (ja) * 1997-12-27 1999-08-27 Korea Electronics Telecommun シリコン基板上のインダクタ装置及びその製造方法

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 1998, no. 10 31 August 1998 (1998-08-31) *
PATENT ABSTRACTS OF JAPAN vol. 1999, no. 13 30 November 1999 (1999-11-30) *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002017399A1 (fr) * 2000-08-24 2002-02-28 Infineon Technologies Ag Dispositif a semi-conducteurs et son procede de production
US6838746B2 (en) 2000-08-24 2005-01-04 Infineon Technologies Ag Semiconductor configuration and method for fabricating the configuration
CN114823638A (zh) * 2022-04-27 2022-07-29 电子科技大学 一种低寄生电容集成电感结构

Also Published As

Publication number Publication date
DE19944306B4 (de) 2005-05-19
DE19944306A1 (de) 2001-05-03

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