WO2001018962A1 - Flip-flop circuit, and method of holding and synchronizing data using clock signal - Google Patents

Abstract

A low-power, high-speed flip-flop circuit is provided that has a simplified, smaller circuit configuration. A flip-flop comprises two latch hold circuits composed of transistors (B1-B4) and transistors (B5-B8), respectively; and a clock-input differential circuit composed of transistors (B9-B12). With clock inputs (CP) and (CN) being high and low, respectively, transistors (B9, B10) turn on, and the current from a constant current source (12) turns transistor (B2, B3) off. Similarly, transistors (B5, B8) are also turned off, causing the second latch hold circuit to be in hold state. With clock inputs (CP) and (CN) being low and high, respectively, the states of the first and second latch hold circuits are switched, resulting in flip-flop operation.

Description

 Description = flip-flop circuit and method for holding and synchronizing data with clock signal

 The present invention relates to an electronic device, and more particularly to an ECL-type low-voltage and low-power-consumption flip-flop circuit using a bipolar transistor.

Background art

 Flip-flop circuits are becoming increasingly important in electronic devices such as semiconductor devices, and low-voltage operation, low-power operation, high-speed operation, a simple structure, and a small number of components are desired. Conventional ECL flip-flop circuits that operate at a low voltage include a circuit according to the technology of Japanese Patent Application Laid-Open No. 2-217177 (FIG. 5) and a circuit according to the technology of Japanese Patent Application Laid-Open No. 10-51278 ( Figure 6).

 The flip-flop circuit in Fig. 5 consists of two latch-hold circuits and a clock circuit that constitute a master circuit and a slave circuit. Each transistor has a configuration in which a current source is connected to the negative power supply VEE in the emitter, and a collector is connected to the positive power supply VCC or a resistor to the positive power supply VCC. However, the number of force current sources that make the circuit suitable for low-voltage operation was as large as five, making it unsuitable for low-current operation. The number of transistors is as large as 14 transistors.

The flip-flop circuit in Fig. 6 is composed of two buffer circuits, two latch hold circuits, and a clock circuit. Each transistor is connected between a positive power supply and a negative power supply with a resistor and a current source. This is suitable for low-voltage operation, and the number of current sources is four, which is smaller than that of the circuit in Fig. 5. However, it takes time to transmit data by the buffer circuit connected before each latch-hold circuit, which is disadvantageous for high-speed operation, and furthermore, lower-voltage operation is desired. Transit evenings are also as large as 14 pieces. Disclosure of the invention

 Therefore, in the conventional flip-flop circuit, low-voltage operation, low-power operation, high-speed operation, a simple structure, and few components are desired. An object of the present invention is to provide such a flip-flop circuit.

 The flip-flop circuit according to the present invention includes: (Α) a first latch-hold circuit; (Β) a second latch-hold circuit cascaded to the latch-hold circuit; and (C) the two latch-hold circuits. A clock circuit for providing a control signal;

 Each of the latch and hold circuits takes two states, a transparent state and a hold state, depending on the potential difference between the input and output. The clock circuit controls the two states of each latch and hold circuit. Details of each embodiment are described in detail below.

 The latch-hold circuit uses transistors # 1 to # 4, each emitter connected to a common constant current source, and connects each base of the transistors # 1 and # 4 to a pair of positive and negative inputs. The collectors of transistors Β 1 and Β 2 and the base of Β 3 are connected to the negative output, and the collectors of transistors Β 3 and Β 4 and the base of Β 2 are connected to the positive output. And

 When each input is lower in potential than each output, transistors Β1 and Β4 are turned off, and transistors Β2 and Β3, which are positive feedback, are turned on, maintaining the hold state and the potential difference is reversed. Becomes a transparent state because the on / off state of each transistor is reversed.

 The clock circuit is composed of transistors # 9 to # 12, each emitter connected to a common constant current source I2, and the bases of transistors # 9 and # 10 are both negative clock inputs. The bases of transistors Β11 and Β12 are both positive clock inputs. The collectors of transistors Β9 and Β10 are connected to the negative and positive outputs of master and latch hold circuit 11, respectively, and the collectors of transistors Bl1 and B12 are latched and held on the slave side, respectively. Connected to positive and negative outputs of circuit 12.

The input of the master-side latch-hold circuit 11 is connected to the output of a similar flip-flop in the previous stage, or the output of the flip-flop circuit when the clock input is at Hi level and Low level. An intermediate bias voltage is provided. When the clock input is at the L level, the output of the master-side latch-hold circuit 11 has a lower potential than its input, and the master-side latch-hold circuit 11 is in a transparent state. Set the input of 2 to a lower potential than its output, and set the slave latch-hold circuit 12 to the hold state. Conversely, when the clock input is at the H level, the master latch-hold circuit 11 enters the hold state, and the slave latch-hold circuit 12 enters the transparent state. BRIEF DESCRIPTION OF THE FIGURES

 Figure 1

 1 is a schematic block diagram showing an example of an embodiment of the present invention.

 Figure 2

 FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

 Fig. 3

 FIG. 3 is a waveform chart showing an example of a waveform at each position in FIG. 2.

 Fig. 4

 FIG. 6 is a circuit diagram showing a second embodiment of the present invention.

 Fig 5

 FIG. 9 is a circuit diagram illustrating an example of a conventional flip-flop circuit.

 Fig. 6

 FIG. 11 is a circuit diagram illustrating another example of a conventional flip-flop circuit. Explanation of reference numerals

 1 1 Mass latch side hold circuit

 1 2 Slave latch-hold circuit

1 3 Clock circuit

 B 1 to B 1 2 transistor

R 1 to R 6 resistance

I 1 to I 3 constant current source

VCC Positive power supply pin VE E Negative power supply terminal

 D P Positive data input

 DN Negative data input

 C P Positive clock input

 C N Negative clock input

 Q P Positive output

 BEST MODE FOR CARRYING OUT THE INVENTION

 In FIG. 1, a master-side latch / hold circuit 11 receives a data signal 15 and a clock signal 20 generated by a clock circuit 13. The master latch hold circuit 11 takes two states, a transparent state and a hold state, according to the levels of the data signal 15 and the clock signal 20. Outputs the data / clock signal 16 reflecting the levels 5 and 18. The data clock signal 16 includes both a data signal component and a clock signal component.

 The slave latch-hold circuit 12 is supplied with the data / clock signal 16 from the master latch-hold circuit 11 via the data clock signal path, and the clock signal 13 from the clock circuit 13. Is supplied. Similarly to the master-side latch-hold circuit 11, the slave-side latch-hold circuit 12 takes two states, a transparent state and a hold state, according to the levels of the data clock signal 16 and the clock signal 21. The flip-flop output 19 reflecting the state, the level of the data / clock signal 16 and the clock signal 21 is output. In this figure, each signal path is shown by only one line for simplicity of the figure, but each signal path is actually composed of one or two or more lines. In the embodiments of FIGS. 2 and 4 described later, each signal path is composed of two to four lines.

The configuration of the embodiment in FIG. 2 will be described. This flip-flop circuit is roughly composed of a master-side latch-hold circuit 11, a slave-side latch-hold circuit 12, and a clock circuit 13. The master-side latch-hold circuit 1 1 is a transistor B 1 -B4, resistors R1 and R2, and constant current source I1.Emitters of transistors B1 to B4 and the sink side of constant current source I1 are connected, and collectors of transistors B1 and B2 and B 3 is connected to one terminal of the resistor R1, and the negative output of the mass circuit マ ス 1N. The collectors of the transistors B3 and B4, the base of B2, and one terminal of the resistor R2 are connected, and the positive output of the master circuit 〇1P. The other terminals of the resistors R 1 and R 2 are connected to the positive power supply V CC.

 The slave-side latch-hold circuit 12 has the same configuration as the master-side latch-hold circuit 11, and includes transistors B5 to B8, resistors R3 and R4, and a constant current source 13, and each of the transistors B5 to B8 In the evening, the sink side of the constant current source I3 is connected, the collectors of the transistors B5 and B6, the base of B7 and one terminal of the resistor R3 are connected, and the flip-flop output becomes the negative output QN. Transistor The collectors of B7 and B8, the base of B6, and one terminal of resistor R4 are connected, and the positive output 01P of the master circuit. The other terminals of resistors R3 and R4 are connected to the positive power supply VCC.

 The clock circuit 13 includes transistors B9 to B12 and a constant current source I2, the negative clock input CN is connected to each base of the transistors B9 and B10, and the positive clock input CP is connected to the transistor B11. And B12 are connected to each base. Each emitter of the transistors B9 to B12 is connected to the sink side of the constant current source I2. The collector of transistor B 9 is connected to the positive output 〇 1 P of the master latch latch circuit 11, the collector of transistor B 10 is connected to the negative output 01 N of the master latch hold circuit 11, and the collector of transistor B 11 is connected to The collector of the transistor B 12 is connected to the positive output QP of the slave latch-hold circuit 12, and the negative output QN of the slave latch hold circuit 12. The source side of the constant current source I2 is connected to the negative power supply VEE.

Since all of the transistors B1 to B12 are connected only between the positive power supply and the negative power supply via the current source and the resistor, low power supply voltage operation is possible as in the conventional circuit. Also, unlike the conventional circuit in Fig. 6, a buffer circuit is not required before the latch and hold circuit, so that data signals can be directly connected to the latch and hold circuit, and no delay occurs, making it suitable for high-speed operation. Also, the number of components is significantly reduced as compared with the conventional circuit. An example For example, the number of transistors is reduced from 16 to 12 as compared with the embodiment of FIG. In addition, since the master-side latch-hold circuit 11, the slave-side latch-hold circuit 12, and the clock circuit 13 have good symmetry, noise, operation stability, and manufacturability are improved.

 The operation of the flip-flop circuit of FIG. 2 will be described with reference to FIG. When the clock signal CN applied to the bases of B9 and B10 is at high level (Hi) and CP is at low level (L0) (when waveform (A) in Fig. 3 is Lo), B9 and B10 are on The current flows to each collector, and the current drawn by I1 flows to Rl and R2. Comparing the potentials at the bases of B2 and B1, the potential at the base of B2 is lower and B1 turns on, B2 turns off, and similarly, B4 turns on and B3 turns off .

 Here, when DP is Hi, B1 is turned on and the voltage of 01N further drops. At this time, DN is Lo, so B4 is off, 01P is Hi, and 01N is Lo. This state is the transparent mode, and waveform B is not latched and appears in waveform C as it is.

 When waveform A is Lo, B9 and B10 are turned off, and if the base potential of Bl and B4 is set lower than the base potential of B2 and B3, Bl and B4 are turned off. Becomes Immediately before the waveform A becomes Lo, two states of the master-side latch-hold circuit 11 and the waveform C are determined depending on whether B2 or B3 is on.

 Thus, 01P and 01N (waveform C) are supplied to the slave-side latch and hold circuit 12. This signal includes a data signal component and a clock signal component. This is a feature of the present invention not found in the prior art. According to the present invention, a signal including both a short-time signal component and a quick signal component is supplied to a signal path connecting the two latch hold circuits 11 and the slave latch-hold circuit 12 in this manner. As a result, the configuration of the entire circuit could be greatly simplified.

FIG. 3 shows the change of the waveform at each position, and if the person who understands the operation of the flip-flop circuit can refer to the above description, the configuration of FIG. 2, and the waveforms A and B, You can see that waveforms C and D are obtained. As shown in FIG. 3, the waveform C, which is the output of the master-side latch hold circuit 11, has a time (2) to (3), (6) to (9), It is Hi in (13) to (16) and Lo in other times. The waveform D, which is the flip-flop output, is high at times (7) to (10) and (14) to (17), and is L0 at other times. Waveforms A and B provide the appropriate waveform D as a flip-flop output. On the right side of the waveform of 01N and 0IP of waveform C, the voltage at which the circuit of Fig. 2 actually operates is shown. The present invention can be operated even with a low potential difference of 0.8V.

 The configuration of the second embodiment in FIG. 4 will be described. Compared to the configuration in Fig. 2, separate resistors R5 and R6 are connected between the two resistors connected to the positive power supply VCC of each latch-hold circuit 11 and slave latch-hold circuit 12 and the positive power supply VCC. Are connected. As a result, a required potential difference between the input and output of each latch and hold circuit can be generated with a smaller current than in the first embodiment. Since all of the transistors B1 to B12 are connected between the positive power supply and the negative power supply via only the current source and the resistor, low power supply voltage operation similar to that of the conventional circuit is possible.

 As described above, the flip-flop circuit of the present invention comprises a two latch circuit composed of transistors B1 to B4 and B5 to B8 and a clock differential circuit composed of transistors B9 to B12. In a flip-flop circuit having a circuit, when the clock input CP is at the Hi level and the CN is at the Lo level, the transistors B9 and B10 are in the camion state, and the transistors B2 and B3 are turned on by the current of the constant current source I2. The transistor is turned off, the first latch and hold circuit is in a transparent state, and similarly, the transistors B5 and B8 are also in the off state, so that the second latch and hold circuit is in the hold state. When the clock input CP is at L level and CN is at H level, the states of the first and second latch and hold circuits are switched, and the flip-flop operation is performed. With this configuration, a simpler configuration, smaller circuit scale, low-voltage operation, low-power operation, high-speed operation, and fewer components are possible.

Claims

The scope of the claims  1. (A) a first latch and hold circuit to which a data signal and a peak signal are input; (B) a second latch that is cascaded directly to the first latch and hold circuit without passing through another circuit, is supplied with the output of the first latch and hold circuit, and outputs the flip-flop output of the flip-flop circuit A hold circuit,  (C) a flip-flop circuit having a clock circuit that supplies a clock signal to the first and second latch-hold circuits,  The output of the first latch circuit includes a data signal component and a clock signal component. A flip-flop circuit characterized by the above-mentioned.  2. (A) a first latch and hold circuit to which a data signal and a clock signal are inputted; and (B) a cascade connection to the first latch and hold circuit, wherein the output of the first latch and hold circuit is supplied, A second latch hold circuit that outputs a flip-flop output of the flip-flop circuit;  (C) a clock circuit that directly supplies a clock signal to the first and second latch-hold circuits without passing through another circuit,  The output of the first latch and hold circuit includes a data signal component and a clock signal component A flip-flop circuit characterized by the above-mentioned. 3. The first latch and hold circuit includes first, second, third, and fourth transistors, and the bases of the first and fourth transistors are respectively connected to the two data input terminals. The bases of the second and third transistors are each connected to one of the two output lines of the first latch and hold circuit;  The second latch and hold circuit includes fifth, sixth, seventh and eighth transistors, and the bases of the fifth and eighth transistors are respectively connected to two lines of the output of the first latch and hold circuit. 3. The flip-flop circuit according to claim 1, wherein one is connected, and the bases of the sixth and seventh transistors are each connected to one of two lines of the flip-flop output. 4. (A) First latch and hold circuit, (B) a second latch-hold circuit directly cascaded to the first latch-hold circuit without passing through another circuit;  (C) a flip-flop circuit having a clock circuit for supplying a control clock signal to the first and second latch hold circuits,  The first and second latch and hold circuits take two states, a transparent state and a hold state, according to a potential difference between an input and an output.  The clock circuit performs control for giving two states of a transparent state and a hold state of the first and second latch and hold circuits,  By connecting the output of the clock circuit to the outputs of the first and second latch and hold circuits, two states of the transparent and hold states of the first and second latch and hold circuits are controlled. A flip-flop circuit characterized by the above-mentioned.  5. A method of holding and synchronizing data with a clock signal using a master circuit consisting of a first transistor group and a slave circuit consisting of a second transistor group, comprising: A step of inputting into the mass circuit;  (B) inputting a first clock signal to a master circuit;  (C) switching on / off states of some transistors of the first transistor group using the first clock signal;  (D) switching on and off states of some of the transistors of the first transistor group using the data signal;  (E) generating a data clock signal by performing an operation from the data signal and the first clock signal using a first transistor group, and directly outputting the data clock signal to the slave circuit without passing through another circuit;  (F) inputting a second clock signal to the slave circuit;  (G) using a second clock signal to switch on and off states of some of the transistors in the second transistor group;  (H) a step of switching between the ON state and the OFF state of a portion of the second transistor group using the first signal, (I) a second transistor from the data clock signal and the second clock signal Calculating using the group and outputting the output of the slave circuit; and A method for retaining and synchronizing data with a clock signal, comprising:  6. A method of holding and synchronizing data with a clock signal using a master circuit composed of a first transistor group and a slave circuit composed of a second transistor group. Inputting to the  (B) a step of directly inputting the first clock signal to the master circuit without passing through other circuits;  (C) switching on and off states of some transistors of the first transistor group using the first clock signal;  (D) switching on and off states of some of the transistors of the first transistor group using the overnight signal;  (E) calculating a data Z signal from the data signal and the first clock signal using a first transistor group, and outputting the generated clock signal to a slave circuit; (F) a step of directly inputting the second clock signal to the slave circuit without passing through another circuit;  (G) using a second clock signal to switch on and off states of some of the transistors in the second transistor group;  (H) switching between an on state and an off state of a part of the second transistor group using the data knock signal;  (I) outputting the output of the slave circuit by performing an operation using the data Z clock signal and the second clock signal using a second transistor group; A method for holding and synchronizing data with a clock signal.