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WO2001011558A1 - Procedes d'apprentissage pour systemes binaires - Google Patents

Procedes d'apprentissage pour systemes binaires Download PDF

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Publication number
WO2001011558A1
WO2001011558A1 PCT/JP1999/004237 JP9904237W WO0111558A1 WO 2001011558 A1 WO2001011558 A1 WO 2001011558A1 JP 9904237 W JP9904237 W JP 9904237W WO 0111558 A1 WO0111558 A1 WO 0111558A1
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Prior art keywords
layer
input
binary
pseudo
neuron
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PCT/JP1999/004237
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English (en)
Inventor
Tang Zheng
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SOWA INSTITUTE OF TECHNOLOGY Co Ltd
Sowa Inst of Tech Co Ltd
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SOWA INSTITUTE OF TECHNOLOGY Co Ltd
Sowa Inst of Tech Co Ltd
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Priority to BR9915915-5A priority Critical patent/BR9915915A/pt
Priority to PCT/JP1999/004237 priority patent/WO2001011558A1/fr
Priority to AU51948/99A priority patent/AU765460B2/en
Publication of WO2001011558A1 publication Critical patent/WO2001011558A1/fr
Priority to NO20011689A priority patent/NO20011689L/no
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means

Definitions

  • This invention relates to learnable binary systems .
  • the present invention is developed in consideration of the above drawback, and the object of this invention is to provide learning methods in binary systems, by modifying the connected states of the circuit in each of the basic binary circuits in binary combined logical and sequential circuits composed with basic binary gates such as AND, OR, NOT, NAND, NOR and EXOR gates .
  • the learning is performed under the connected states , in which the first binary gate is connected to the second binary gate by selecting any one of the following four connected states :
  • this learning is performed by modifying the pseudo- potential energies expressing the above connecting states.
  • the above-mentioned sequential circuits are composed with the combined circuit and a memory circuit and the connection between them as shown in Fig. 4, and the combined circuit is constructed with the basic binary gates such as AND, OR, NOT, NAND, NOR and EXOR gates.
  • Thesis learning methods are further characterized in that the above connected states are expressed by using a pseudo-potential energy (hereafter called PPE).
  • PPE pseudo-potential energy
  • binary combinational logic circuits are characterized in that they are composed with an input layer, a connecting layer, an AND layer and an OR layer as shown in Fig. 5.
  • binary combinational logic circuits are also characterized in that they are composed with an input layer, a connecting layer, an OR layer and AND layer as shown in Fig . 6.
  • the above binary combinational logic circuits are also characterized in that they are composed with an input layer, a connecting layer, an intermediate NAND layer, and an outputting NAND layer as shown in Fig. 7.
  • the above binary combinational logic circuits are also characterized in that they are composed with an input layer, a connecting layer, an intermediate NOR layer and an outputting NOR layer as shown in Fig. 8.
  • the above binary combinational logic circuits are also _characterized in that they are composed with an input layer, a connecting layer, an intermediate EX0.R layer and an outputting EXOR layer as shown in Fig. 9.
  • Fig. 1 shows the order of pseudo-potential energy of connection states
  • Fig. 2 shows the modification method of pseudo-potential energy of connection states
  • Fig. 3 shows a block diagram of a combinational network
  • Fig. 4 shows a block diagram of a sequential network
  • Fig. 5 shows a block diagram of an AND-OR network
  • Fig. 6 shows a block diagram of an OR-AND network
  • Fig. 7 shows a block diagram of a network by NAND gates
  • Fig. 8 shows a block diagram of a network by NOR gates
  • Fig. 9 shows a block diagram of a network by EXOR gates
  • Fig. 10 shows a truth table for an exa pler binary function
  • Fig. 11 shows a Karnaugh map for an exampler binary function
  • Fig. 12 shows a logic circuit for an exampler binary function
  • Fig. 13 shows a diagram of threshold function and model of the pseudo-neuron
  • Fig. 14 shows the expression of the connection state with pseudo-neuron
  • Fig. 15 shows one output AND-OR network with pseudo-neuron
  • Fig. 16 shows a continuous valued function approximated to OR gate
  • Fig. 17 shows a continuous valued function approximated to AND gate
  • Fig. 18 shows a truth table of learning signals
  • Fig. 19 shows a truth table of learning signals
  • Fig. 20 shows a Karnaugh map of the threshold update ⁇ i:j ;
  • Fig. 21 shows state assignment of the connection states by pseudo-netfron
  • Fig. 22 shows a Karnaugh map of pseudo-neuron output ( Y . ) with input (X and state assignment (q 3 , q 2 , q ;
  • Fig. 23 shows circuit implementation of learning algorithm
  • Fig. 24(a) shows the state transition diagram of threshold learning ⁇ ;
  • Fig. 24(b) shows a state transition diagram of weight learning ⁇ W
  • Fig. 25(a) shows a state transition table of threshold learning
  • Fig. 25(b) shows a state transition table of weight learning
  • Fig. 26 shows a truth table for threshold learning circuit
  • Fig. 27 shows a truth table for weight learning circuit
  • Fig. 28 shows a truth table of weight and threshold modification circuits
  • Fig. 29 shows a Karnaugh map of q 3 ' ;
  • Fig. 30 shows a Karnaugh map of q 2 ' ;
  • Fig. 31 shows a Karnaugh map of q 1 ' ;
  • Fig. 32 shows a modification circuit diagram using a combinational network
  • Fig. 33 shows a modification circuit diagram using sequential network
  • Fig. 34 shows a truth table of pseudo-neuron connecting circuit
  • Fig. 35 shows a circuit of the pseudo-neuron connection
  • Fig. 36 shows a block diagram of the whole learning circuit
  • Fig. 37 shows a truth table of connection function
  • Fig. 38 shows a learning algorithm circuit using pseudo- potential energy method
  • Fig. 39 shows a truth table of connection state learning circuit
  • Fig. 40 shows a learning modification circuit using sequential network
  • Fig. 41 shows the diagram of connection circuit
  • Fig. 42 shows a block diagram of the whole learning circuit using pseudo-potential energy method
  • Fig. 43 shows learning in sequential network.
  • any logic function is expressed with logical sum form (composed with AND-OR circuit shown in Fig. 5).
  • a logic function shown in Fig. 10 becomes expressed in Eq.(2) by simplifying with a Karnaugh map shown in Fig. 11.
  • Z Xi x 2 + x 2 x 3 + x 2 x 3 x 4 Eq - ( 2 )
  • Eq.(2) The logic function shown in Eq.(2) is expressed in a block diagram shown in Fig. 12 by applying an AND-OR network.
  • the connecting states between an input layer and an AND layer are determined in any one of the following four connected states in accordance to the logic function, namely:
  • Input X ⁇ is included in logic term AND._ (for example, as X 2 shown in Fig. 12 is included both in AND X and AND 2 , X 2 is directly connected);
  • any logical function having n variables can be realized with an AND-OR network consisting of at most 2 (n_1 +1 AND gates .
  • the connections between input layer and AND layer are realized by applying any one of the above-mentioned connections .
  • the above connected conditions can be expressed by applying a pseudo-neuron (hereinafter "PN").
  • PN pseudo-neuron
  • the connected conditions between inputs and outputs in the pseudo-neuron are expressed with a threshold function shown in Eq.(3) or Eq.(4).
  • Y ij output of the ij-th pseudo-neuron W i;j : weight factor of input X i to the ij-th pseudo-neuron ⁇ ⁇ j : the threshold of the ij-th pseudo-neuron.
  • the pseudo-neuron has only one input and one output, and W ij takes either 1 or -1, and ⁇ ij takes one among -1.5, -0.5, 0.5 or 1.5 as shown in Fig. 13(a) or (b) .
  • the output from the pseudo-neuron takes either 1 or 0 in accordance to weight factor W i;j and threshold ⁇ L - as shown in
  • the network shown in Fig. 15 is stratum-like which is composed of an input layer, a pseudo-neuron layer, an AND layer and an OR layer, and each layer is composed of adequate numbers of gates without any connection in each layer itself. Further, the connection between each layer is limited only in one direction (namely, a feed-forward type) from one input layer to output layer. In gates of each layer excepting the connection between any input layer and any pseudo-neuron layer, the connection with the forwardly placed gate is specified as binary 1.
  • the response function of the PN is approximated by a Sigmoid function, and AND, OR gates are approximated by continuous valued minimum, maximum functions, many algorithms, for example, such as the error back propagation method, can be used. However, modification or learning is performed only by applying weights and thresholds of the PN.
  • a learning algorithm for connected conditions between input layer and AND layer in the binary system is derived as follows .
  • desired outputs or the teacher's signals are supposed, as T 1 , T 2 , T m for the given inputs X 1 , X 2 , X n
  • the outputs of the network shown in Fig. 5 are supposed as Z ⁇ r Z 2 , Z m
  • an error function E is defined as sum of squares, as shown in Eq.(5).
  • each OR gate is approximated by following continuous functions shown in Eq.(ll).
  • M is maximum of the input excepting AND . Namely,
  • ⁇ W i: - ⁇ w (Z-T)Sgn(AND : -M)Sgn(m-Y ⁇ ;] )X i and
  • ⁇ 13 and ⁇ have respectively simple logic relations with output Z, teacher's signal T, output of the AND gate AND._, output of the PN, ⁇ and input X ⁇ .
  • the learning rules can be realized with logic circuits.
  • the modification is limited to 1,-1 or 0 which represent that current weights and thresholds are increased, decreased or held as much as one unit, and the one unit is defined as 1 for weights and 2 for thresholds .
  • the learning algorithm is composed only with logical operations between inputs, output signals, teacher's signals, outputs from AND layers and outputs from PNs, and gives a learning signal against PNs whether to increase or to decrease or to hold respective weights and thresholds .
  • the modifications of the weights and thresholds are determined by input X x , output Z, output from PN (Y i3 ), AND ⁇ and teacher's signal T. Then, allocating the connected conditions (8 conditions) of the PN shown in Fig. 14 to the conditions shown in Fig. 21 by applying 3 bits (q 3 , q 2 , q , the logic function composed of the output of the PN, inputs and variables (q 3 , q 2 , q ⁇ ) is expressed by Karnaugh map shown in Fig. 22, further following Eq.(19) is obtained from that Karnaugh map.
  • the logic circuit for the learning signals shown in Eqs.(17) and (18) is expressed as shown in Fig. 23, and the logic circuit shown in Fig. 23 gives 0 or 1 or HP according to the above-described learning algorithm.
  • the learning circuit is expressed as shown in Fig. 33.
  • the connecting circuit is expressed as shown in Fig. 35, and the block diagram of the whole learning circuits using PN is shown in Fig. 36.
  • PPE method learning algorithms applied with pseudo-potential energy method
  • each connected state is defined by applying the pseudo-potential energy. Further, the order from high to low of the pseudo-potential energy is assumed as follows. For 0-input, (1) 1-connected, (2) inverter-connected, (3) direct-connected, (4) 0-connected; and for 1-input, (1) 1-connected, (2) direct- connected, (3) inverter-connected and (4) 0-connected.
  • S(l), S(x), S(l-x) andS(O) denote 1-connected, directly-connected, inverter-connected, and 0-connected states of a pseudo-neuron, and allocating 11, 10, 01, 00 to each of the above four connected states by applying 2 bits (g 2 , q ⁇ ) binary code.
  • the logical relation between Y and current states q 2 q lf input X 1 is expressed by the truth table shown in Fig. 37, and further the logical relation thereof is expressed by the following Eq. (24) .
  • the truth table for the combinational network in the seguential network can be expressed in Fig. 39.
  • the state transition function can be obtained from Eg. (25).
  • the learning modification circuit can be realized with a circuit as shown in Fig. 40.
  • the connected circuit also can be realized with a circuit as shown in Fig. 41.
  • the block diagram of the whole learning circuit using the pseudo-potential energy method is shown in Fig. 42.
  • a binary system for example, a system shown in Fig. 5 is a multi-layered feed forward network consisting of a connecting layer, an AND layer, an OR layer.
  • the learning is to change the connecting function C by applying gradient descent method or pseudo-potential energy method.
  • a sequential network composed of a combinational network with a connecting layer, an AND layer, an OR layer, and a memory network with D flip-flops is considered.
  • the sequential network can be represented as the following equations .
  • Z(t) f(C x (t), X(t), C 2 (t-1), X(t-l), D(t-2)) wherein C : (t), C 2 (t) are connection functions at the time of step t, and
  • X(t), Z(t) and D(t) are input, output and internal states at the time of step t, respectively.
  • connection functions C : (t), C 2 (t-1) by gradient descent method or pseudo-potential energy method.
  • the first binary gate and the second binary gate are defined as one of gates comprising OR, AND, NOR, NAND and EXOR gate, and the first gate is connected to the second gate in any one state among the following four connected states composed with:
  • the learning is performed by selecting any one connected state among the above four states .
  • an input is connected to any one gate among OR, AND, NOR, NAND and EXOR gate in any one state among the following four connected states composed with:
  • the learning is performed by selecting any one connected state among the above four states .
  • the learning is performed by selecting any one connected state among the above four states .
  • connection between above first binary gate or an input and the second binary gate is constructed so as to select any one state among the above four connected states, at least according to the computed result between the input signal into the first binary gate and the teacher's signal for learning.
  • the connection between the first binary gate (or inpute ) and the second binary gate is defined by the pseudo-neuron Q and the selection of the connection (i.e., the learning) is carried out by modifying weights and thresholds of the pseudo-neuron Q.
  • W the weight between the input and the pseudo-neuron Q
  • ⁇ the threshold of the pseudo-neuron Q.
  • the systems are comprised with an input layer letting a plural of binary input data input, an AND layer having a plural of AND gates, an OR layer having a plural of OR gates letting the outputs from the AND layer input, an output layer inputting the outputs from the OR layer and a connecting layer having pseudo-neurons Q provided between the input layer and the AND layer, and the connections between the input layer and the AND layer are selected among the following connected states :
  • X is the input signal into the pseudo-neuron Q
  • W is the weight between the input and the pseudo-neuron
  • ⁇ is the threshold of the pseudo-neuron.
  • the system is comprised with an input layer letting a plural of binary input data input, an OR layer having a plural of OR gates , an AND layer having a plural of AND gates letting the output from the OR layer input therein, an output layer inputting the outputs from the AND layer, and a connecting layer having pseudo-neurons Q provided between the input layer and the OR layer, and the connections between the input layer and the OR layer are selected among the following four connected states :
  • X is the input signal into the pseudo-neuron Q
  • W is the weight between the input and the pseudo-neuron
  • ⁇ is the threshold of the pseudo-neuron.
  • the system is comprised with an input layer letting a plural of binary data input, an intermediate NAND layer having a plural of NAND gates , an output NAND layer having a plural of NAND gates inputting the output from the intermediate NAND layer, an output layer inputting the output from the output NAND layer and a connecting layer having pseudo-neurons Q provided between the input layer and the intermediate NAND layer, and the connections between the input layer and the intermediate NAND layer selected among the following connected states :
  • the input layer is directly connected to the NAND layer
  • X is the input signal input to the pseudo-neuron Q
  • W is the weight between the input and the pseudo-neuron
  • ⁇ is the threshold of the pseudo-neuron.
  • the system is comprised with an input layer letting a plural of binary data input, an intermediate NOR layer having a plural of NOR gates, an output NOR layer having a plural of NOR gates inputting the output from the intermediate NOR layer, an output layer inputting the output from the output NOR layer and a connecting layer having pseudo-neurons Q provided between the input layer and the intermediate NOR layer selected from among the following connected states :
  • X is the input signal input to the pseudo-neuron Q
  • W is the weight between the input and the pseudo-neurons
  • ⁇ is the threshold of the pseudo-neuron
  • the system is comprised with an input layer letting a plural of binary data input, an intermediate EXOR layer having a plural of EXOR gates, an output EXOR layer having a plural of EXOR gates inputting the output from the intermediate EXOR layer, an output layer inputting the output from the output EXOR layer and a connecting layer having pseudo-neurons Q provided between the input layer and the intermediate EXOR layer, and both layers are connected by any method selected from the following four connected states :
  • X is the input signal input to the pseudo-neuron Q
  • W is the weight between the input and the pseudo-neuron
  • ⁇ is the threshold of the pseudo-neuron.
  • these learning methods are expected to be used widely in image processing, voice processing, natural word processing and motion control.

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Abstract

La présente invention concerne des procédés d'apprentissage pour systèmes binaires, consistant à modifier les états de connexion du circuit au niveau de chacune des portes binaires de base dans des circuits binaires logiques et séquentiels combinés composés de portes binaires de base, telles que ET, OU, NON, NON-ET, NON-OU et OU exclusif. Etant donné que la théorie des pseudo-neurones et la théorie de l'énergie pseudo-potentielle ont été présentées de façon habile, il est possible d'obtenir des effets d'apprentissage spécifiés au cours d'une période d'apprentissage très courte. En outre, la mise en oeuvre de ces procédés d'apprentissage sur un ordinateur traditionnel ou autre équipement numérique étant simple, le procédé selon l'invention devrait connaître un large usage dans diverses applications, notamment le traitement des images, le traitement de la voix ou le traitement des mots naturels.
PCT/JP1999/004237 1999-08-05 1999-08-05 Procedes d'apprentissage pour systemes binaires Ceased WO2001011558A1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
BR9915915-5A BR9915915A (pt) 1999-08-05 1999-08-05 Métodos de aprendizado em sistemas binários
PCT/JP1999/004237 WO2001011558A1 (fr) 1999-08-05 1999-08-05 Procedes d'apprentissage pour systemes binaires
AU51948/99A AU765460B2 (en) 1999-08-05 1999-08-05 Learning methods in binary systems
NO20011689A NO20011689L (no) 1999-08-05 2001-04-04 L¶refremgangsmåter i bin¶re systemer

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PCT/JP1999/004237 WO2001011558A1 (fr) 1999-08-05 1999-08-05 Procedes d'apprentissage pour systemes binaires

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1992004687A1 (fr) * 1990-09-11 1992-03-19 Siemens Aktiengesellschaft Procede et dispositif de mise en ×uvre booleenne de reseaux neuronaux de type adaline
WO1992012497A1 (fr) * 1991-01-02 1992-07-23 Claude Abin Reseau neuronal a operateurs binaires et procedes pour sa realisation
EP0841621A1 (fr) * 1996-11-06 1998-05-13 Sowa Institute of Technology Co., Ltd. Méthodes d'apprentissage dans des systèmes binaires

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5212765A (en) * 1990-08-03 1993-05-18 E. I. Du Pont De Nemours & Co., Inc. On-line training neural network system for process control
US5226092A (en) * 1991-06-28 1993-07-06 Digital Equipment Corporation Method and apparatus for learning in a neural network

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1992004687A1 (fr) * 1990-09-11 1992-03-19 Siemens Aktiengesellschaft Procede et dispositif de mise en ×uvre booleenne de reseaux neuronaux de type adaline
WO1992012497A1 (fr) * 1991-01-02 1992-07-23 Claude Abin Reseau neuronal a operateurs binaires et procedes pour sa realisation
EP0841621A1 (fr) * 1996-11-06 1998-05-13 Sowa Institute of Technology Co., Ltd. Méthodes d'apprentissage dans des systèmes binaires

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
ELIASHBERG V: "A RELATIONSHIP BETWEEN NEURAL NETWORKS AND PROGRAMMABLE LOGIC ARRAYS", PROCEEDINGS OF THE INTERNATIONAL CONFERENCE ON NEURAL NETWORKS (ICNN),US,NEW YORK, IEEE, vol. -, 1993, pages 1333 - 1337, XP000379470, ISBN: 0-7803-0999-5 *
VESELKO GUSTIN: "ARTIFICIAL NEURAL NETWORK REALIZATION WITH PROGRAMMABLE LOGIC CIRCUIT", MICROPROCESSING AND MICROPROGRAMMING,NL,ELSEVIER SCIENCE PUBLISHERS, BV., AMSTERDAM, vol. 35, no. 1 / 05, 1 September 1992 (1992-09-01), pages 187 - 192, XP000325123, ISSN: 0165-6074 *

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AU5194899A (en) 2001-03-05
AU765460B2 (en) 2003-09-18
NO20011689D0 (no) 2001-04-04

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