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WO2001097285A3 - Elektronisches bauteil aus einem gehäuse und einem substrat - Google Patents

Elektronisches bauteil aus einem gehäuse und einem substrat Download PDF

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Publication number
WO2001097285A3
WO2001097285A3 PCT/DE2001/001989 DE0101989W WO0197285A3 WO 2001097285 A3 WO2001097285 A3 WO 2001097285A3 DE 0101989 W DE0101989 W DE 0101989W WO 0197285 A3 WO0197285 A3 WO 0197285A3
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
housing
electronic component
contact
component consisting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/DE2001/001989
Other languages
English (en)
French (fr)
Other versions
WO2001097285A2 (de
Inventor
Hans-Juergen Hacke
Holger Huebner
Axel Koeniger
Max-Gerhard Seitz
Rainer Tilgner
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of WO2001097285A2 publication Critical patent/WO2001097285A2/de
Anticipated expiration legal-status Critical
Priority to US10/320,946 priority Critical patent/US6930383B2/en
Publication of WO2001097285A3 publication Critical patent/WO2001097285A3/de
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985—Flexible insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
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    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
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    • H01L2924/01013—Aluminum [Al]
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    • H01L2924/01019—Potassium [K]
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    • H01L2924/01029—Copper [Cu]
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    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
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    • H01L2924/01327—Intermediate phases, i.e. intermetallics compounds
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Multi-Conductor Connections (AREA)

Abstract

Die Erfindung betrifft ein elektronisches Bauteil aus einem Gehäuse (1) und einem mindestens eine integrierte Schaltung aufweisenden ersten Substrat (2), wobei eine Vielzahl von Kontaktflächen (4) willkürlich auf der Oberfläche des ersten Substrats (2) verteilt angeordnet ist und ein gehäusebildendes zweites Substrat (3) flächig über eine isolierende Verbindungsschicht (5) mit der Oberfläche des ersten Substrats (2) mechanisch verbunden ist, wobei das zweite Substrat (3) Kontaktanschlußflächen (6) aufweist, die mit den Kontaktflächen (4) des ersten Substrats (2) flächig und elektrisch leitend verbunden sind und symmetrisch angeordnete Außenkontaktflächen (9) aufweist, die über Durchkontakte (8) in dem zweiten Substrat (3) mit den Kontaktanschlußflächen (6) leitend verbunden sind.
PCT/DE2001/001989 2000-06-14 2001-05-28 Elektronisches bauteil aus einem gehäuse und einem substrat Ceased WO2001097285A2 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US10/320,946 US6930383B2 (en) 2000-06-14 2002-12-16 Electronic component including a housing and a substrate

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10029269.0 2000-06-14
DE10029269A DE10029269B4 (de) 2000-06-14 2000-06-14 Verfahren zur Herstellung eines elektronischen Bauteiles aus gehäusebildenden Substraten

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US10/320,946 Continuation US6930383B2 (en) 2000-06-14 2002-12-16 Electronic component including a housing and a substrate

Publications (2)

Publication Number Publication Date
WO2001097285A2 WO2001097285A2 (de) 2001-12-20
WO2001097285A3 true WO2001097285A3 (de) 2003-01-03

Family

ID=7645679

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2001/001989 Ceased WO2001097285A2 (de) 2000-06-14 2001-05-28 Elektronisches bauteil aus einem gehäuse und einem substrat

Country Status (3)

Country Link
US (1) US6930383B2 (de)
DE (1) DE10029269B4 (de)
WO (1) WO2001097285A2 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10240461A1 (de) 2002-08-29 2004-03-11 Infineon Technologies Ag Universelles Gehäuse für ein elektronisches Bauteil mit Halbleiterchip und Verfahren zu seiner Herstellung
DE102004027094A1 (de) * 2004-06-02 2005-12-29 Infineon Technologies Ag Halbleitermodul mit einem Halbleiter-Sensorchip und einem Kunststoffgehäuse sowie Verfahren zu dessen Herstellung
DE102005058654B4 (de) * 2005-12-07 2015-06-11 Infineon Technologies Ag Verfahren zum flächigen Fügen von Komponenten von Halbleiterbauelementen
KR101009103B1 (ko) * 2008-10-27 2011-01-18 삼성전기주식회사 양면 전극 패키지 및 그 제조방법
JP2015056641A (ja) 2013-09-13 2015-03-23 株式会社東芝 半導体装置及びその製造方法
KR101672641B1 (ko) * 2015-07-01 2016-11-03 앰코 테크놀로지 코리아 주식회사 반도체 디바이스의 제조 방법 및 이에 따른 반도체 디바이스
US10748850B2 (en) 2018-03-15 2020-08-18 Semiconductor Components Industries, Llc Thinned semiconductor package and related methods

Citations (9)

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Publication number Priority date Publication date Assignee Title
DE3740773A1 (de) * 1987-12-02 1989-06-15 Philips Patentverwaltung Verfahren zum herstellen elektrisch leitender verbindungen
DE19532250A1 (de) * 1995-09-01 1997-03-06 Daimler Benz Ag Anordnung und Verfahren zum Diffusionslöten eines mehrschichtigen Aufbaus
JPH1032224A (ja) * 1996-07-15 1998-02-03 Shinko Electric Ind Co Ltd 半導体装置及びその製造方法
DE19702186A1 (de) * 1997-01-23 1998-07-30 Fraunhofer Ges Forschung Verfahren zur Gehäusung von integrierten Schaltkreisen
US5886409A (en) * 1996-01-16 1999-03-23 Hitachi, Ltd. Electrode structure of wiring substrate of semiconductor device having expanded pitch
US5918113A (en) * 1996-07-19 1999-06-29 Shinko Electric Industries Co., Ltd. Process for producing a semiconductor device using anisotropic conductive adhesive
US6004867A (en) * 1996-12-16 1999-12-21 Samsung Electronics Co., Ltd. Chip-size packages assembled using mass production techniques at the wafer-level
EP0973197A2 (de) * 1998-07-16 2000-01-19 Nitto Denko Corporation Packungsstruktur in Halbleiterscheibengrösse und darin angewendete Schaltungsplatte
US6020220A (en) * 1996-07-09 2000-02-01 Tessera, Inc. Compliant semiconductor chip assemblies and methods of making same

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US5723917A (en) * 1994-11-30 1998-03-03 Anorad Corporation Flat linear motor
US5904499A (en) * 1994-12-22 1999-05-18 Pace; Benedict G Package for power semiconductor chips
WO1996019829A1 (en) * 1994-12-22 1996-06-27 Pace Benedict G Device for superheating steam
US6072236A (en) * 1996-03-07 2000-06-06 Micron Technology, Inc. Micromachined chip scale package
US5889462A (en) * 1996-04-08 1999-03-30 Bourns, Inc. Multilayer thick film surge resistor network
DE19636112A1 (de) * 1996-09-05 1998-03-12 Siemens Ag Trägerelement für einen Halbleiterchip
WO1998020557A1 (en) * 1996-11-08 1998-05-14 W.L. Gore & Associates, Inc. Method for reducing via inductance in an electronic assembly and device
US6103992A (en) * 1996-11-08 2000-08-15 W. L. Gore & Associates, Inc. Multiple frequency processing to minimize manufacturing variability of high aspect ratio micro through-vias
US5833759A (en) * 1996-11-08 1998-11-10 W. L. Gore & Associates, Inc. Method for preparing vias for subsequent metallization
JP2000505948A (ja) * 1996-11-08 2000-05-16 ダブリュ．エル．ゴア アンド アソシエイツ，インコーポレイティド 公称位置合せを向上させるための基準手法を用いる方法
US6140734A (en) * 1998-04-03 2000-10-31 Nikon Corporation Of Japan Armature with regular windings and having a high conductor density

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3740773A1 (de) * 1987-12-02 1989-06-15 Philips Patentverwaltung Verfahren zum herstellen elektrisch leitender verbindungen
DE19532250A1 (de) * 1995-09-01 1997-03-06 Daimler Benz Ag Anordnung und Verfahren zum Diffusionslöten eines mehrschichtigen Aufbaus
US5886409A (en) * 1996-01-16 1999-03-23 Hitachi, Ltd. Electrode structure of wiring substrate of semiconductor device having expanded pitch
US6020220A (en) * 1996-07-09 2000-02-01 Tessera, Inc. Compliant semiconductor chip assemblies and methods of making same
JPH1032224A (ja) * 1996-07-15 1998-02-03 Shinko Electric Ind Co Ltd 半導体装置及びその製造方法
US5918113A (en) * 1996-07-19 1999-06-29 Shinko Electric Industries Co., Ltd. Process for producing a semiconductor device using anisotropic conductive adhesive
US6004867A (en) * 1996-12-16 1999-12-21 Samsung Electronics Co., Ltd. Chip-size packages assembled using mass production techniques at the wafer-level
DE19702186A1 (de) * 1997-01-23 1998-07-30 Fraunhofer Ges Forschung Verfahren zur Gehäusung von integrierten Schaltkreisen
EP0973197A2 (de) * 1998-07-16 2000-01-19 Nitto Denko Corporation Packungsstruktur in Halbleiterscheibengrösse und darin angewendete Schaltungsplatte

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 1998, no. 06 30 April 1998 (1998-04-30) *

Also Published As

Publication number Publication date
US20030116840A1 (en) 2003-06-26
DE10029269A1 (de) 2002-01-17
US6930383B2 (en) 2005-08-16
WO2001097285A2 (de) 2001-12-20
DE10029269B4 (de) 2005-10-13

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