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WO2001077818A3 - Method for predicting the instruction execution latency of a de-coupled configurable co-processor - Google Patents

Method for predicting the instruction execution latency of a de-coupled configurable co-processor Download PDF

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Publication number
WO2001077818A3
WO2001077818A3 PCT/US2001/010687 US0110687W WO0177818A3 WO 2001077818 A3 WO2001077818 A3 WO 2001077818A3 US 0110687 W US0110687 W US 0110687W WO 0177818 A3 WO0177818 A3 WO 0177818A3
Authority
WO
WIPO (PCT)
Prior art keywords
cpu
coprocessor
predicting
fcop
instruction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2001/010687
Other languages
French (fr)
Other versions
WO2001077818A2 (en
Inventor
Muhammad Afsar
Stash Czaja
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies North America Corp
Original Assignee
Infineon Technologies North America Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies North America Corp filed Critical Infineon Technologies North America Corp
Publication of WO2001077818A2 publication Critical patent/WO2001077818A2/en
Publication of WO2001077818A3 publication Critical patent/WO2001077818A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

A method and an apparatus for predicting the execution latency of coprocessor are disclosed. As a method, a central processing unit (CPU) fetches an instruction to be executed by a de-coupled flexible coprocessor (FCOP). The instruction is decoded into an opcode (command) and corresponding data by the CPU which are then passed to the FCOP for execution during coprocessor runtime. Since the CPU has the capability of predicting the corresponding coprocessor runtime, the CPU continues to execute other instructions concurrently with the FCOP executing the FCOP instruction. In this way, the CPU does not suspend operation during coprocessor runtime.
PCT/US2001/010687 2000-04-05 2001-04-03 Method for predicting the instruction execution latency of a de-coupled configurable co-processor Ceased WO2001077818A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US54305100A 2000-04-05 2000-04-05
US09/543,051 2000-04-05

Publications (2)

Publication Number Publication Date
WO2001077818A2 WO2001077818A2 (en) 2001-10-18
WO2001077818A3 true WO2001077818A3 (en) 2002-06-27

Family

ID=24166383

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/010687 Ceased WO2001077818A2 (en) 2000-04-05 2001-04-03 Method for predicting the instruction execution latency of a de-coupled configurable co-processor

Country Status (1)

Country Link
WO (1) WO2001077818A2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7933276B2 (en) * 2004-11-12 2011-04-26 Pmc-Sierra Israel Ltd. Dynamic bandwidth allocation processor
EP2278452A1 (en) * 2009-07-15 2011-01-26 Nxp B.V. Coprocessor programming

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0294487A1 (en) * 1986-12-23 1988-12-14 Fanuc Ltd. System for controlling coprocessors
US5214764A (en) * 1988-07-15 1993-05-25 Casio Computer Co., Ltd. Data processing apparatus for operating on variable-length data delimited by delimiter codes
US5287466A (en) * 1990-07-17 1994-02-15 Mitsubishi Denki Kabushiki Kaisha Method and apparatus for parallel loads equalizing utilizing instruction sorting by columns based on predicted instruction execution time
US5530889A (en) * 1991-07-03 1996-06-25 Hitachi, Ltd. Hierarchical structure processor having at least one sub-sequencer for executing basic instructions of a macro instruction

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0294487A1 (en) * 1986-12-23 1988-12-14 Fanuc Ltd. System for controlling coprocessors
US5214764A (en) * 1988-07-15 1993-05-25 Casio Computer Co., Ltd. Data processing apparatus for operating on variable-length data delimited by delimiter codes
US5287466A (en) * 1990-07-17 1994-02-15 Mitsubishi Denki Kabushiki Kaisha Method and apparatus for parallel loads equalizing utilizing instruction sorting by columns based on predicted instruction execution time
US5530889A (en) * 1991-07-03 1996-06-25 Hitachi, Ltd. Hierarchical structure processor having at least one sub-sequencer for executing basic instructions of a macro instruction

Also Published As

Publication number Publication date
WO2001077818A2 (en) 2001-10-18

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