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WO2001061868A3 - Method, apparatus, and product for use in generating crc and other remainder based codes - Google Patents

Method, apparatus, and product for use in generating crc and other remainder based codes Download PDF

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Publication number
WO2001061868A3
WO2001061868A3 PCT/US2001/005477 US0105477W WO0161868A3 WO 2001061868 A3 WO2001061868 A3 WO 2001061868A3 US 0105477 W US0105477 W US 0105477W WO 0161868 A3 WO0161868 A3 WO 0161868A3
Authority
WO
WIPO (PCT)
Prior art keywords
remainder based
based codes
preliminary
product
remainder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2001/005477
Other languages
French (fr)
Other versions
WO2001061868A2 (en
Inventor
Rasekh Rifaat
Boris Lerner
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Analog Devices Inc
Original Assignee
Analog Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Analog Devices Inc filed Critical Analog Devices Inc
Priority to JP2001560547A priority Critical patent/JP2003523682A/en
Priority to EP01911029A priority patent/EP1260023A2/en
Publication of WO2001061868A2 publication Critical patent/WO2001061868A2/en
Publication of WO2001061868A3 publication Critical patent/WO2001061868A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
    • H03M13/091—Parallel or block-wise CRC computation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6569—Implementation on processors, e.g. DSPs, or software implementations

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
  • Detection And Correction Of Errors (AREA)

Abstract

A method, apparatus and product for user in generating a remainder based code generates a plurality of preliminary remainder based codes in response to specified data, and synthesizing a remainder based code for the specified data, in response to the plurality of preliminary remainder based codes. In one embodiment, the plurality of preliminary remainder based codes includes at least two preliminary remainder based codes each generated in response to a respective portion of the specified data. In another embodiment, at least two preliminary remained based codes are generated at least partially concurrently with one another.
PCT/US2001/005477 2000-02-17 2001-02-20 Method, apparatus, and product for use in generating crc and other remainder based codes Ceased WO2001061868A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2001560547A JP2003523682A (en) 2000-02-17 2001-02-20 Method, apparatus, and product for use in generating CRC and other remainder-based codes
EP01911029A EP1260023A2 (en) 2000-02-17 2001-02-20 Method, apparatus, and product for use in generating crc and other remainder based codes

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US18319700P 2000-02-17 2000-02-17
US60/183,197 2000-02-17

Publications (2)

Publication Number Publication Date
WO2001061868A2 WO2001061868A2 (en) 2001-08-23
WO2001061868A3 true WO2001061868A3 (en) 2002-02-21

Family

ID=22671853

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/005477 Ceased WO2001061868A2 (en) 2000-02-17 2001-02-20 Method, apparatus, and product for use in generating crc and other remainder based codes

Country Status (5)

Country Link
US (1) US6912683B2 (en)
EP (1) EP1260023A2 (en)
JP (1) JP2003523682A (en)
CN (1) CN1411630A (en)
WO (1) WO2001061868A2 (en)

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US7458006B2 (en) * 2002-02-22 2008-11-25 Avago Technologies General Ip (Singapore) Pte. Ltd. Methods for computing the CRC of a message from the incremental CRCs of composite sub-messages
US6961893B1 (en) * 2002-03-28 2005-11-01 Adaptec, Inc. Separable cyclic redundancy check
US20050271246A1 (en) * 2002-07-10 2005-12-08 Sharma Ravi K Watermark payload encryption methods and systems
US20040158794A1 (en) * 2002-07-19 2004-08-12 Niesen Joseph W. Reduced overhead CRC functionality for packets and link layer superframes
US7336667B2 (en) * 2002-11-21 2008-02-26 International Business Machines Corporation Apparatus, method and program product to generate and use CRC in communications network
US7082563B2 (en) * 2003-01-31 2006-07-25 Italtel S.P.A. Automated method for generating the cyclic redundancy check for transmission of multi-protocol packets
US7231581B2 (en) * 2003-12-31 2007-06-12 Intel Corporation Communicating using a partial block in a frame
US7543214B2 (en) * 2004-02-13 2009-06-02 Marvell International Ltd. Method and system for performing CRC
US8127137B2 (en) 2004-03-18 2012-02-28 Digimarc Corporation Watermark payload encryption for media including multiple watermarks
EP1728346A1 (en) * 2004-03-19 2006-12-06 Novo Nordisk A/S A reduced size transmission data packet header format for a medical device
US20060168495A1 (en) * 2005-01-25 2006-07-27 Analog Devices, Inc. Computation of cyclic redundancy check
US20080201689A1 (en) * 2005-06-30 2008-08-21 Freescale Semiconductor, Inc. Vector Crc Computatuion on Dsp
US7958436B2 (en) 2005-12-23 2011-06-07 Intel Corporation Performing a cyclic redundancy checksum operation responsive to a user-level instruction
CN101507120A (en) 2006-08-22 2009-08-12 松下电器产业株式会社 Parallel residue arthmetic operation unit and parallel residue arthmetic operating method
US8671331B2 (en) * 2006-08-25 2014-03-11 Tellabs Operations, Inc. Apparatus and method for communicating FEC mode and alarming mismatch
JP4787732B2 (en) * 2006-12-26 2011-10-05 富士通株式会社 Information bit string division method and apparatus
US8689078B2 (en) * 2007-07-13 2014-04-01 Intel Corporation Determining a message residue
JP4831018B2 (en) * 2007-08-28 2011-12-07 日本電気株式会社 Parallel cyclic code generation apparatus and parallel cyclic code inspection apparatus
US8555148B2 (en) * 2007-09-18 2013-10-08 Samsung Electronics Co., Ltd. Methods and apparatus to generate multiple CRCs
EP2187526B1 (en) 2008-11-07 2013-01-02 Alcatel Lucent Fast computation of frame check sequences (FCS/CRC)
US9003259B2 (en) * 2008-11-26 2015-04-07 Red Hat, Inc. Interleaved parallel redundancy check calculation for memory devices
CN101527615A (en) * 2009-04-07 2009-09-09 华为技术有限公司 Implementation method of cyclic redundancy check (CRC) codes and device
US8266499B2 (en) * 2009-05-28 2012-09-11 Kabushiki Kaisha Toshiba CRC protection of data stored in XOR buffer
US8381080B2 (en) 2010-06-15 2013-02-19 Lsi Corporation Reducing a degree of a polynomial in a polynomial division calculation
US8745476B1 (en) 2010-10-13 2014-06-03 Marvell Israel (M.I.S.L.) Ltd. Systems and methods for cyclic redundancy check implementation
US8984377B2 (en) * 2011-04-19 2015-03-17 National Kaohsiung First University Of Science And Technology Stopping methods for iterative signal processing
US8775894B1 (en) * 2011-06-24 2014-07-08 Altera Corporation Lane specific CRC
US8607129B2 (en) * 2011-07-01 2013-12-10 Intel Corporation Efficient and scalable cyclic redundancy check circuit using Galois-field arithmetic
US20140173392A1 (en) * 2012-12-19 2014-06-19 Advanced Micro Devices, Inc. Hardware enforced protection of software data structures
US9154161B1 (en) * 2014-04-01 2015-10-06 Cisco Technology, Inc. Calculating cyclic redundancy checks over overlapping windows of streaming data
KR102353983B1 (en) * 2015-05-20 2022-01-20 아크리비스 시스템즈 피티이 엘티디 How to arrange an algorithm in Cyclic Redundancy Check (CRC)

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WO1999037030A1 (en) * 1998-01-20 1999-07-22 3Com Corporation High-speed calculation of cyclical redundancy check sums
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Also Published As

Publication number Publication date
JP2003523682A (en) 2003-08-05
US6912683B2 (en) 2005-06-28
WO2001061868A2 (en) 2001-08-23
CN1411630A (en) 2003-04-16
US20030061561A1 (en) 2003-03-27
EP1260023A2 (en) 2002-11-27

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