WO2001054196A1

WO2001054196A1 - Dual-sided, surface mountable integrated circuit package

Info

Publication number: WO2001054196A1
Application number: PCT/US2001/001492
Authority: WO
Inventors: Charles R. Magill; Deborah L. Goldstein; Mark A. Monroe
Original assignee: SUNRISETEK LLC
Current assignee: SUNRISETEK LLC
Priority date: 2000-01-18
Filing date: 2001-01-17
Publication date: 2001-07-26
Anticipated expiration: 2002-07-18
Also published as: AU2001229547A1

Abstract

A dual-sided integrated circuit package implemented as a temperature compensated crystal oscillator circuit component. The package includes a ceramic substrate having a top surface supporting various electronic components including a crystal (24) and a bottom surface supporting various sintered component elements. The top surface components are protected by an RF interference shield (30) connected to a ground plane. An oscillator circuit (22) is constructed, tested and a curve fitting software calculates desired optimal values dependent on the specific output characteristics of the circuit. Utilizing laser trimming, the sintered components on the bottom surface are trimmed to the optimal values to achieve the desired output curve characteristics of the circuit.

Description

DUAL-SIDED, SURFACE MOUNTABLE INTEGRATED CIRCUIT PACKAGE

FIELD OF THE INVENTION In general, this invention relates to a surface mounted, dual-sided integrated circuit package and in particular, to a laser calibrated, surface mounted, temperature compensated crystal oscillator circuit component.

BACKGROUND OF THE INVENTION Temperature compensated crystal oscillators allow manufacturers of various electronic instruments such as base stations, cellular communications devices, and test and measurement equipment to employ more precise timing devices in their circuits. Specifically, a temperature compensated crystal oscillator circuit utilizes the unique curve characteristics of a crystal and then adjusts the curve using a resistor- thermistor network. Thus, the output curve of a temperature compensated crystal oscillator can ideally be adjusted to be within a range of frequencies called for in the equipment in which it is implemented.

In general, a conventional temperature compensated crystal oscillator includes an oscillator circuit, an amplifier circuit, and a compensation circuit whose qualities are defined by such characteristics as frequency, output wave, package size, stability over temperature and temperature range. Accordingly, the reputation and quality of a temperature compensated crystal oscillator manufacturer is based on their ability to control these characteristics.

One conventional method of manufacturing temperature compensated crystal oscillators includes 1) designing the circuit layout; 2) manufacturing the PC board; 3) populating the board with components; 4) cycling through multiple iterations of testing the oscillator over a temperature range to refine the compensation circuit by adjusting the resistive network; 5) sealing the part; and 6) shipping or discarding the component. Additionally, in step 4, some conventional manufacturing processes utilize more imprecise resistor components, requiring a manufacturer to go through multiple iterations. Thus, the manufacture continuously interchanges the resistive components on the circuit until an acceptable output from the circuit is achieved. As would be understood, these multiple iterations are inefficient and increase overall manufacturing costs.

As an alternative to iteratively correcting each oscillator circuit as described above, other conventional manufacturing methods sample the curve characteristics of a single oscillator circuit and develop a standard compensation circuit value based on the sampled output characteristics of the single oscillator circuit. Then, a larger quantity of oscillator circuits are manufactured using the standard values for the compensation circuit. Because the curve characteristics of every crystal is unique, use of a standard value compensation circuit produces a fluctuation in the quality of the output of each oscillator circuit. Accordingly, in such mass production methods, components which do not meet the output characteristic ranges are sometimes discarded rather than corrected. Thus, this conventional method is inefficient in producing oscillator circuits with more imprecisely adjusted output characteristics and in discarding some percentage of all the oscillators built. Thus, there is a need for a manufacturing method which can efficiently produce temperature compensated crystal oscillators which have more precise adjusted output characteristics.

Many conventional integrated circuit devices also use a 14-pin dual-in-line pin (DTP) package as the adhering mechanism to attach the integrated circuit component to a substrate of another integrated circuit. In such a configuration, the pins of the DIP package are inserted into one or more pre-bored plated holes maldng an electrical and physical contact with the substrate. One conventional method of mounting the circuit component on another substrate entails hand placement of the DIP package in the pre- bored holes followed by hand soldering. Accordingly, this method of hand placement decreases the number of integrated circuits which can be mounted in a given-time period while increasing the overall labor costs of circuit construction.

Other conventional methods of mounting an integrated circuit to a substrate includes the machine placement of the integrated circuit on the substrate. However, because the dimensions of the DIP package are relatively small and the pins are delicate in nature, the machine placement of the circuit on the plated holes must be precise. Accordingly, the machine process is relatively slow and inefficient, thereby increasing the overall cost of the integrated circuit board construction. Yet another conventional method of mounting an integrated circuit to a substrate includes bending the DIP package and spot soldering the pins of the DIP package to the surface of a substrate. This method requires increased labor costs in bending the DIP package leads, either by hand or mechanically, and carefully spot soldering the circuit to the substrate. Additionally, because the DIP package is typically constructed of a light metal conductive material, the pins are susceptible to breaking. Thus, in the terms of a bulk manufacturing environment, the conventional bending method for mounting an integrated circuit via a DIP package is deficient.

Some conventional manufacturing methods have attempted to addressed the fragile nature of the DIP package by incorporating a flush mounted integrated circuit. In such a system, the integrated circuit component is mounted flush to the substrate of the other integrated circuit via a plurality of connectors on the surface of the component. However, flush mounting presents problems of undesired electrical interference. As applied to integrated circuit components which utilize the surface which will be flush with the other substrate for placement of electrical components, some of the circuit traces may have exposed conductor or unsealed connections which can contact the other substrate and interfere or short out the desired connections.

Additionally, in the event that the circuit component substrate is of a material having different thermal properties than the mounting substrate, the coefficient of thermal expansion differences in the two substrates can cause cracks in the substrates or cause the solder connections to break. Thus, there is a need for a surface mounted integrated circuit which can accommodate components on the mounting surface without increasing electrical interference and which can accommodate differences between thermal properties of two substrates. Therefore, there is a need for an integrated circuit package which allows the manufacturer to efficiently adjust a compensation circuit needed to optimize the performance characteristics of the circuit and which can be surface mounted to another integrated circuit substrate without causing electrical interference and accommodating thermal expansions of the substrate materials. SUMMARY OF THE INVENTION The present invention satisfies the above-mentioned need by providing a method and device implementing a laser calibrated, surface mounted, temperature compensated crystal oscillator. Generally described, the present invention provides an integrated circuit package. The integrated circuit package includes a first surface having mounted thereto a plurality of components electrically connected by conductive material, a second surface having mounted thereto a plurality of components electrically connected by conductive material, a nonconductive substrate located between the first surface and the second surface and a shield attached to the first surface and protecting the plurality of components on the first surface. Additionally, the first and second surface are electrically connected.

In another aspect of the present invention, an adjustable crystal oscillator component is provided. The crystal oscillator components includes a top surface having at least one crystal and a plurality of electrical components mounted on the first surface, and a bottom surface having a plurality of electrical components fused onto the bottom surface. Additionally, the top surface and the bottom surface are electrically connected.

In a further aspect of the present invention, a method of manufacturing a crystal oscillator component including a crystal, a plurality of circuit components and a substrate having a top surface and a bottom surface is provided. The method assembles and attaches the circuit components and the crystal, tests and analyzes the output properties of the circuit, and adjusts the circuit according to the output properties.

In yet another aspect of the present invention, a method of manufacturing a crystal oscillator circuit including a crystal, one or more sintered elements, and a substrate having a top surface and a bottom surface is provided. The method constructs a circuit containing the crystal and the resistive elements, determines a crystal curve characteristic of the crystal, calculates desired sintered component values corresponding to a desired crystal curve characteristic, laser trims the sintered elements to achieve the desired crystal curve characteristics, and shields the top surface. In a still further aspect of the present invention, an integrated circuit package for temperature compensated crystal oscillator circuit components is provided. The integrated circuit package includes a nonconductive substrate having a first and a second surface that are electrically connected, a plurality of electronic components electrically connected by preprinted conductive material, a crystal having a crystal curve output in the range from about 1 Hz to about 5 GHZ, and a plurality of solder terminals. Additionally, some of the electronic components are mounted on the first surface and the rest are mounted on the second surface. Also, the solder terminals are located on the substrate to allow for surface mounting, and the electronic components on the second surface include a sintered component element adjusted to control the curve characteristic of the crystal. In another aspect of the present invention, a surface mounted circuit package for mounting to a surface on an integrated circuit is provided. The surface mounted circuit package includes a bottom surface for fusing a plurality of circuit components and at least two interconnects mounted on the bottom surface for adhering the package to the integrated circuit and for maldng an electrical connection with the integrated circuit and the package. Additionally, the interconnects form an air barrier with respect to the bottom surface and a top surface of the integrated circuit.

BRIEF DESCRIPTION OF THE DRAWING Objects and features of the invention denoted above are explained in more detail with reference to the drawing figures, and in which like reference numerals are used to indicate like parts in the various views:

FIG. 1 is a top elevational view of the dual-sided integrated circuit package of the present invention;

FIG. 2 is a back elevational view of the dual-sided integrated circuit package of the present invention; FIG. 3 is a side elevational view of the dual-sided integrated circuit package of the present invention;

FIG. 4 is an exploded view of the side elevational view of the dual-sided adjustable electronic package of the present invention;

FIG. 5 is a flow diagram of the methods used to adjust the typical embodiment of the preferred embodiment; FIG. 6 is a graph representative of the output crystal curve characteristics of the preferred temperature compensated crystal oscillator integrated circuit of the present invention; and

FIG. 7 is a schematic of a representative circuit component layout for the preferred temperature compensated crystal oscillator circuit of the present invention.

DETAILED DESCRIPTION OF THE INVENTION For a better understanding of the present invention, reference may be had to the following detailed description taken in conjunction with the appended claims and accompanying drawings. In essence, the present invention includes a dual-sided, surface mountable integrated circuit package facilitating placement of electronic circuit components on two working surfaces. The dual-sided feature organizes the components into two possible working environments which are electronically connected utilizing conductive vias in the substrate. Utilizing a surface mounted solder system, the package is attached directly to the substrate of another integrated circuit without need for an external pin package.

FIGS. 1, 2, 3 and 4 are representative of a preferred temperature compensated crystal oscillator integrated circuit package of the present invention. As would be understood, the dual-sided integrated circuit package should not be limited solely to the example components disclosed for this embodiment. With reference to FIGS . 1, 2, and 3 , the present invention provides a dual- sided integrated circuit package, designated generally by the reference numeral 10. The package 10 is based on a thick film substrate 12, which preferably is constructed of alumina ceramic or other suitable substrate materials. The substrate 12 typically includes a top surface 14 and a bottom surface 16. In general, the substrate 12 is substantially nonconductive. To support electric conductivity between various electrical components, the top surface 14 and the bottom surface 16 have a paste material 18 overlaid on one or more of the surfaces of the nonconductive substrate 12. Preferably, the paste material 18 and other various components are sintered one either of the surfaces of the substrate 12 in a plurality of layers. The package 10 supports a variety of electronic components on either surface. With reference to FIG. 4, the top surface 14 establishes electric conductivity with the bottom surface 16 through a plurality of interconnecting vias 20. The vias 20 are preferably pre-bored holes within the substrate 12 which are coated with gold. Alternatively, the vias 20 are coated with other conductive material such as palladium, silver or platinum, or a combination of such materials. By placing the conductive paste material 18 on the surfaces such that it contacts the vias 20, a component mounted on the top surface 14 can be electrically connected to any components mounted on the bottom surface 16. As would be understood, the number, placement, and use of the vias 20 depends on the type of integrated circuit constructed on the package 10.

With continued reference to FIGS. 1, 2 and 3, a preferred embodiment of the package 10 comprises a temperature compensated crystal oscillator circuit, designated generally by reference numeral 22. The temperature compensated crystal oscillator circuit 22 generally includes a crystal 24, one or more capacitors 26, one or more active devices 27, and one or more resistors 28. FIG. 7 is a schematic of a representative circuit component layout utilizing a variety of electrical components on the package 10 of the present invention. As would be understood, there are a plurality of oscillator circuit layouts, as well as other integrated circuit layouts, which are considered within the scope of the present invention. In a preferred configuration, the crystal 24, one or more capacitors 26, one or more active devices 27, and one or more resistors 28 are mounted on the top surface 14. These components can be mounted utilizing conductive adhesive, a spot soldering or reflow soldering or are directly printed on the surface 14.

Because the circuit 22 is vulnerable to radio interference and because a variety of the components could be sensitive to handling, the package 10 preferably includes an RF interference shield 30. The shield 30 is preferably constructed of metal or other metalized materials, is of a rectangular shape, and seals the perimeter of the top surface 14. Because some components, such as the capacitor 26, may have user adjustable features, the shield 30 includes an access hole 32. The access hole 32 provides limited access to the components on the top surface 14 without defeating the shielding function of the shield 30. As would be understood, the shield 30 may also be of a varied dimension such that it only covers a portion of the top surface 14. Additionally, while the shield 30 is typically a rectangular shape, different shaped and sized shields are considered within the scope of the present invention. Additionally, operatively connected to the shield 30 is a ground plane 29 which performs part of the shielding function. The ground plane 29 preferably is of a dimension such that it encompasses the perimeter of the substrate 12.

As illustrated in FIG. 2, the bottom surface 16 supports sintered components, such as resistors 28, which are electrically connected to themselves or other components via the printed paste material 18. Preferably, the sintered components, such as the resistors 28 , are constructed of a paste, such as a resistive paste, whose dimensions control its electric properties, and which can be sintered onto the bottom surface 16. As would be understood, the bottom surface 16 can support other components which can be printed onto the surface or which are of a dimension not to interfere with the mounting function of the package 10.

With reference to FIGS. 2 and 3, the package 10 is preferably surface mounted when incorporated as a component into another integrated circuit design. Surface mounting is accomplished utilizing a plurality of terminals 34. Preferably four ball shaped terminals 34 are found at the corners of the package 10 and function as standoffs which provide electronic conductivity to the package 10. As would be understood, the dimensions of the ball shaped terminals 34 provide an air barrier between the bottom surface 16 and the top surface of another substrate. This air barrier protects the components mounted on the bottom surface 16 from electrical interference due to exposed conductors or unsealed connections on the surface 16. Additionally, in the event that the package 10 is mounted on an integrated circuit having a substrate possessing different thermal properties, the air barrier allows for expansion and contraction of both substrates without causing either substrate to crack or without cracking or damaging the interconnects for the components on the package 10.

As an alternative to prevent electrical interference problems with the components of the other integrated circuit, a polymer coat (not shown) is added to the bottom surface 16 prior to surface mounting. Preferably, the polymer coats seals any exposed areas of the components on the bottom surface. It should be understood that the application of a variety of coating materials is considered within the scope of the present invention. Moreover, the polymer coat is preferably utilized in conjunction with the air barrier formed by the ball shaped terminals 34.

Because the package 10 does utilize a DIP package, the use of the ball shaped terminals 34 allows machine placement of package 10 in a more efficient manner. Specifically, multiple packages 10 can be placed on a machine fed tape and are self- aligning, maldng installation cost and time efficient.

FIG. 5 is a flow diagram representative of the manufacturing processes required to construct the temperature compensated crystal oscillator circuit of the present invention. The method begins with the sintering of the various components into the substrate at S500. Next, the crystal and the components are assembled onto the package, as indicated at S505. At S510, a determination is made whether the components of the circuit are operational per specifications made by the manufacturer. Preferably, this includes testing crystal to insure its curve characteristics are within a predetermined frequency range. If at S510 the components are not functional, the manufacturing process fails as illustrated at S515. Preferably, either the failing component(s) can be replaced or the entire circuit may be discarded or recycled. If the components are functional, the process progresses to S520.

At S520, the component properties and characteristics are analyzed to examine the crystal curve characteristics of the circuit and to calculate appropriate adjustments. Preferably, the analysis involves the use of curve fitting software whose output is illustrated in FIG. 6. As would be understood, the curve characteristics of an oscillator circuit has a characteristic S-curve 36 shape with a maximum output frequency 38 and a minimum output frequency 40 over a range of temperatures. Since the output of the circuit is based on a mathematical equation, the S-curve 36 is modified by adjusting the compensation circuit values so that it has a new desired maximum frequency 42 and a new desired minimum frequency 44 as illustrated in modified curve 46. Preferably, the curve fitting software varies only the resistive network values of the oscillator circuit to adjust the circuit S-curve 36.

With continued reference to FIG. 5, once the circuit characteristics and adjustments have been calculated, the shield is attached and the top surface is sealed in S530. At S540, the sintered components on the bottom surface are laser trimmed to the calculated optimal values. Because the sintered components are constructed of paste materials, the dimensions of the resistor are preferably laser trimmed during the manufacturing process to achieve discrete optimal values. As will be understood, other methods of adjusting sintered component values may be considered within the scope of the present invention. Additionally, S530 may also be implemented anywhere throughout the manufacturing process.

Once the sintered component values have been adjusted, the circuit goes through a final test in S550 and the construction method is complete.

The present invention, with the use of a dual-sided, flush mounted integrated circuit package in conjunction with the manufacturing method, facilitates the manufacture of integrated circuit components. Specifically, the present invention facilitates the manufacture and installation of crystal oscillator circuits, while ensuring better component characteristics.

In the foregoing specification, the present invention has been described with reference to specific exemplary embodiments thereof. The invention is considered to have been described in such full, clear, concise and exact terms as to enable a person of ordinary skill in the art to make and use the same. It will be apparent to those skilled in the art, that a person understanding this invention may conceive of changes or other embodiments or variations, which utilize the principles of this invention without departing from the broader spirit and scope of the invention as set forth in the appended claims. All are considered with the sphere, spirit and scope of the invention. The specification and drawings are, therefore, to be regarded in an illustrative rather than restrictive sense. Accordingly, it is not intended that the invention be limited except as may be necessary in view of the appended claims or their equivalents, which particularly point out and distinctly claim the subject matter Applicants regard as their invention.

Claims

CLAIMS What is Claimed:

1. An integrated circuit package, the package comprising: a first surface having mounted thereto a plurality of components electrically connected by conductive material; a second surface having mounted thereto a plurality of components electrically connected by conductive material and wherein the first surface and the second surface are electrically connected; a nonconductive substrate located between the first surface and the second surface; and a shield attached to the first surface, and protecting the plurality of components.

2. The integrated circuit package of claim 1, wherein the substrate is ceramic.

3. The integrated circuit package of claim 1 , wherein the package is surface mounted.

4. The integrated circuit package of claim 3, wherein the surface mounting includes at least two interconnects for adhering the package to a substrate.

5. The integrated circuit package of claim 4, wherein the interconnects are ball shaped.

6. The integrated circuit package of claim 5 further comprising a coating on the second surface to prevent electrical conductivity outside of the bottom surface.

7. The integrated circuit package of claim 1, wherein one of the plurality of components on the top surface is a crystal.

8. The integrated circuit package of claim 1, wherein the shield includes an access hole.

9. The integrated circuit package of claim 1 , wherein the plurality of components on the bottom surface are sintered component elements.

10. The integrated circuit package of claim 1 , wherein the first surface and the second surface are electronically connected by a plurality of conductive interconnects through the substrate.

11. The integrated circuit package of claim 1 , wherein the plurality of components on the top and the bottom surfaces are printed on the surfaces in a plurality of layers.

12. An adjustable crystal oscillator circuit component, the component comprising: a top surface having at least one crystal, and a plurality of electrical components mounted thereon; and a bottom surface having a plurality of electrical components fused thereon; wherein the top surface and the bottom surface are electrically connected.

13. The adjustable crystal oscillator circuit component of claim 12, wherein the top and the bottom surfaces contain printed conductive material for electrically connecting the components.

14. The adjustable crystal oscillator circuit component of claim 13, further comprising a nonconductive substrate located between the top surface and the bottom surface.

15. The adjustable crystal oscillator circuit component of claim 14, wherein the substrate is ceramic.

16. The adjustable crystal oscillator circuit component of claim 15, wherein the component is surface mounted.

17. The adjustable crystal oscillator circuit component of claim 16, wherein the surface mounted component includes interconnects for adhering the package to a circuit.

18. The adjustable crystal oscillator circuit component of claim 17 further comprising a coating on the mounted surface to prevent electric conductivity.

19. The adjustable crystal oscillator circuit component of claim 13, further comprising a shield attached to the top surface.

20. The adjustable crystal oscillator circuit component of claim 19, wherein the shield includes an access hole.

21. A method of manufacturing a crystal oscillator circuit component, wherein the component includes a crystal, a plurality of circuit components, and a substrate having a top surface and a bottom surface, the method comprising: assembling and attaching the circuit components and the crystal; testing and analyzing the output properties of the circuit; and adjusting the circuit according to the output properties.

22. The method of manufacturing a crystal oscillator circuit of claim 21 wherein the assembly of the circuit includes mounting a variety of the components on the top surface and mounting at least one passive element of the electronic components on the bottom surface.

23. The method of manufacturing a crystal oscillator circuit component of claim 21 wherein the testing and analyzing the properties of the circuit includes analyzing a crystal curve characteristic of the crystal.

24. The method of manufacturing a crystal oscillator circuit component of claim 23 wherein the adjusting step includes applying a curve fitting program to the crystal curve characteristic and determining desired values of the electronic components to match a target specification.

25. The method of manufacturing a crystal oscillator circuit component of claim 24, wherein the adjusting step further includes adjusting a passive element mounted on the bottom surface to the desired value.

26. The method of manufacturing a crystal oscillator circuit component of claim 25, wherein the adjustment step includes laser trimming a resistor.

27. The method of manufacturing a crystal oscillator circuit component of claim 21, further comprising shielding the top surface of the circuit.

28. The method of manufacturing a crystal oscillator circuit component of claim 21 further comprising sealing the bottom surface.

29. The method of manufacturing a crystal oscillator circuit component of claim 28 wherein the sealing step includes placing a coating on the bottom surface.

30. A method of manufacturing a crystal oscillator circuit, wherein the circuit includes a crystal, one or more sintered elements, and a substrate having a top surface and a bottom surface, the method comprising: constructing a circuit containing the crystal and the resistive elements; determining a crystal curve characteristic of the crystal; calculating desired sintered component values corresponding to a desired crystal curve characteristic; laser trimming the sintered elements to achieve the desired crystal curve characteristic; and shielding the top surface.

31. The method of manufacturing a crystal oscillator circuit of claim 30, wherein the calculation step includes applying curve fitting software to calculate the sintered elements to the curve characteristic of the crystal.

32. The method of manufacturing a crystal oscillator circuit of claim 30 further comprising sealing the bottom surface.

33. An integrated circuit package for temperature compensated crystal oscillator circuit components, the package comprising: a nonconductive substrate having a first and a second surface which are electrically connected; a plurality of electronic components electrically connected by preprinted conductive material; a crystal having a crystal curve output in the range from about 1 Hz to about 5 GHZ; and a plurality of solder terminals; wherein some of the electronic components are mounted on the first surface and the rest are mounted on the second surface; wherein the solder terminals are located on the substrate to allow for surface mounting; and wherein the electronic components on the second surface includes a sintered component element adjusted to control the curve characteristic of the crystal.

34. The integrated circuit package of claim 33 further comprising a shield having an access hole, wherein the shield is mounted on the first surface.

35. The integrated circuit package of claim 33, wherein the sintered component element is adjusted by laser trimming.

36. The integrated circuit package of claim 33, wherein the second surface is sealed.

37. A surface mounted circuit package for mounting to a surface on an integrated circuit, the package comprising: a bottom surface for fusing a plurality of circuit components; and at least two interconnects, the interconnects mounted on the bottom surface for adhering the package to the integrated circuit and for making an electrical connection with the integrated circuit and the package; and wherein the interconnects form an air barrier with respect to the bottom surface and a top surface of the integrated circuit.

38. The surface mounted integrated circuit package of claim 37, wherein the interconnects are ball shaped.