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WO2001045261A2 - Modele pour boucle a phase asservie a pompe a charge - Google Patents

Modele pour boucle a phase asservie a pompe a charge Download PDF

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Publication number
WO2001045261A2
WO2001045261A2 PCT/US2000/042679 US0042679W WO0145261A2 WO 2001045261 A2 WO2001045261 A2 WO 2001045261A2 US 0042679 W US0042679 W US 0042679W WO 0145261 A2 WO0145261 A2 WO 0145261A2
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WO
WIPO (PCT)
Prior art keywords
current
voltage
clock edge
current step
readable medium
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2000/042679
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English (en)
Other versions
WO2001045261A3 (fr
Inventor
Stephen Mcdonagh
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ceva Technologies Ltd
SILICON SYSTEMS (US) Inc
Original Assignee
Parthus Technologies Ltd
SILICON SYSTEMS (US) Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Parthus Technologies Ltd, SILICON SYSTEMS (US) Inc filed Critical Parthus Technologies Ltd
Priority to AU47139/01A priority Critical patent/AU4713901A/en
Publication of WO2001045261A2 publication Critical patent/WO2001045261A2/fr
Publication of WO2001045261A3 publication Critical patent/WO2001045261A3/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump

Definitions

  • the field of invention relates generally to circuit modeling and; more specifically, to modeling a phase lock loop having a charge pump.
  • FIG 1 illustrates the block diagram of a typical charge pump phase locked loop 100 (CP-PLL), which may also be referred to as a phase lock loop or phase locked loop (PLL).
  • the Voltage-Controlled Oscillator 101 VCO
  • VCO Voltage-Controlled Oscillator
  • CLK clock
  • Clk clock
  • the input clock may also be referred to as a reference clock (REF or Ref).
  • This feedback loop consists of a phase /frequency detector (PFD) 102, charge-pump 103 and filter 104.
  • PFD phase /frequency detector
  • phase /Frequency Detector monitors the phase difference between two clocks.
  • a PFD is a sequential state- machine that changes state on clock transitions.
  • Figure 2 illustrates the state-diagram 200 of PFD 102 of Figure 1.
  • the PFD outputs (UP, DOWN) indicate which clock (REF or CLK) is
  • Charge-Pump Referring back to Figure 1, the charge-pump 103 (CP) sources or sinks current depending on the control inputs, UP and DOWN. This block is used to charge /discharge a loop filter 104.
  • the loop filter 104 affectively integrates current pulses provided by the charge pump 103.
  • the loop filter 104 may consist of a series capacitor-resistor (Rz & Cs) in parallel with another smaller capacitor (Cp) as seen in Figure 1.
  • the series capacitor-resistor is used to stabilize the PLL.
  • the smaller capacitor is used to smooth out any high frequency jumps across the resistor due to mismatch in the circuitry.
  • Other loop filter designs may be used.
  • VCO voltage controlled oscillator 101
  • CLK clock
  • the VCO input voltage 301 also referred to as a control voltage
  • CLK output clock
  • the phase detector 102 and charge-pump 103 help generate a current pulse which is equal to the time difference between the input (REF) and VCO clock (CLK).
  • This current pulse is used to charge or discharge the filter 104.
  • the polarity of the current pulse is typically designed such that the filter voltage will be decreased if the VCO clock (CLK) leads the input clock (REF) and will be increased if the VCO clock (CLK) lags the input clock (REF).
  • This filter voltage is then used to control the VCO 101. This will create the necessary feedback to align both clocks.
  • the loop will settle when the phase difference between the input and VCO clock is zero (i.e. the loop is phase-locked).
  • PLL The design goal of a PLL is to generate a clock (CLK) which is exactly aligned to the input clock (REF). For this reason, PLLs are commonly used in applications which require clock-skew elimination, clock generation and clock/data recovery. PLLs are generally implemented as mixed-mode and non-linear feedback control systems. Typically, they exhibit a low system bandwidth while the internal circuitry operates at a much higher frequency.
  • a method and apparatus that represents a charge pump output signal as a superposition of current steps that step in opposite directions at different times.
  • Figure 1 shows a charge pump phase locked loop (CP-PLL);
  • Figure 2 shows a state diagram for a phase detector
  • FIG. 3 demonstrates voltage controlled oscillator (VCO) operation
  • Figure 4 shows a model for a charge pump and a filter
  • Figure 5 shows a mathematical representation of a VCO
  • Figure 6 demonstrates the operation of a PLL
  • Figure 7 demonstrates a methodology for a model of a PLL
  • Figure 8 shows an example of a filter voltage that may be produced with the PLL model shown in Figure 7;
  • Figure 9 shows an example of a VCO output clock period that may be produced with the PLL model shown in Figure 7;
  • Figure 10 shows an example of a first jitter transfer function that may be produced with the PLL model shown in Figure 7;
  • Figure 11 shows an example of a second jitter transfer function that may be produced with the PLL model shown in Figure 7;
  • Figure 12 shows an example of a VCO transfer function that may be produced with the PLL model shown in Figure 7.
  • the CP-PLL can be modeled by deriving mathematical representations/equations for the behavior of each individual block and combining them in an algorithm to describe the PLL feedback operation.
  • Phase Detector All reference clocks are known during the simulation run- time. When the VCO clock edges are calculated, an 'if' statement performs the phase detector function. This will indicate if the VCO clock is leading or lagging and therefore the polarity of the correction pulse.
  • the output of the charge pump is a stream of current pulses.
  • This can be modeled as the summation 402 of unit steps 401a, 401b of alternating polarity. That is, the superposition of current steps that step in opposite directions at different times. This is illustrated on the left-hand side of Figure 4.
  • This unit steps are time-shifted to the points where the VCO & input clock edges occur.
  • the polarity of the pulses is dictated by the phase detector.
  • the filter is modeled by an equation which describes the time response of the filter to a unit step response. These step responses 403a, 403b are shifted in time (to where the VCO and input clock edges occur), multiplied by the correct polarity and added to construct the filter voltage response 404. This is illustrated on the right-hand side of Figure 4.
  • the step response of the filter shown in Figure 1 to a step impulse can be found through the Laplace transform.
  • the filter voltage at time t can be found by adding together all the previous step responses.
  • P k and t k consist of the polarities and time-shifts of the k lh unit step respectively and N is the number of unit steps.
  • V 0 is the initial voltage on the filter.
  • the VCO may be modeled as an ideal relaxation oscillator.
  • Figure 5 illustrates the mathematical representation of such a VCO.
  • the input control voltage 501 is integrated 502 and compared to a reference voltage.
  • the next VCO edge e.g., edge 503 occurs when this integral equals the reference voltage.
  • the integral is set to zero and the process is repeated.
  • This mathematical representation may look different to the VCO illustrated in Figure 3. However, in this embodiment, only the location of the rising edges are of importance to the phase-detector and so the calculations are simplified.
  • the VCO integral voltage can be defined as
  • Vvco (t) >n 0 - (t - t x )+ k, - V fill ⁇ t)dt Eqn. 3
  • VCO gain K 0 is denoted as a fractional change of the VCO free-running frequency per unit (volt) of input
  • ⁇ 0 t-t x + ⁇ 0 - [v ⁇ i ⁇ t)dt
  • t is the next VCO switching point (i.e., edge).
  • a numerical method such as the Newton-Raphson method is used to solve this equation.
  • Figure 6 illustrates the behavior of a CP-PLL which can be analyzed in terms of whether the VCO clock is leading or lagging the input clock at successive comparison instants. It can be seen that if the VCO is lagging the input clock, an UP pulse is initiated by the input clock. This pulse will act to increase the filter voltage which will cause the VCO to switch at an earlier instant. Therefore, the next VCO switching point must be re-evaluated to include an extra unit step due to the input clock. If the VCO clock occurs before the next input clock, the next case is LEAD and the time point is valid.
  • the filter voltage can be determined by adding the unit step responses due to all previous input and VCO edges and is described by equation (2).
  • the VCO switching point is determined by integrating the filter voltage and equating it to a reference level. This time point can be found by solving equation (7).
  • Figure 7 illustrates a detailed flow chart 700 of an embodiment of the PLL simulation method.
  • the inputs to the algorithm are the location of the input clock edges, the first VCO clock edge and the filter voltage.
  • the PLL simulation will output the VCO switching times.
  • the filter voltage can be re-constructed by using these time values and adding the filter unit step responses all shifted by the appropriate time with the correct polarity.
  • the phase error is just the difference in time between the input reference edges and the VCO switching times.
  • the initial conditions may be provided. T err for the initial phase error and V 0 for the initial filter voltage.
  • the variables of the algorithm include: 1) P n which is the polarity of the n lh unit step; 2) t n which is the location of the n" 1 unit step; 3) t x which is the last VCO switching time; 4) V x which is the filter integral at t x ; and 5) LAG which is true if the VCO clock edge occurs after the next input clock edge.
  • variable arrays are initialized 701 depending on whether the first case is LEAD or LAG. Then, the next case is assumed to be LEAD 702. The next VCO switching point is then found 703. If the VCO clock edge occurs after the input clock edge, the next case is LAG. As such, the variable arrays are updated and the VCO switching point is recalculated 704. Variable arrays are then updated 705 depending on whether the case is LEAD or LAG. The variables that contain the last VCO switching point and the last VCO integral voltage are then updated 706. The next VCO switching point is then calculated if the simulation is not finished.
  • the model may be used to extract the frequency and transient responses of a PLL. It can also be used in an optimization routine and can include error sources such as jitter, noise and leakage which interfere with normal PLL operation.
  • the input clock edges are always known during the simulation and so the edges can be shifted during the run. Therefore the model can be used to plot the frequency response of the PLL.
  • random jitter is added to the input clock of the PLL.
  • An FFT is performed on the input and output jitter and the two results are divided. The results are shown in Figure 11.
  • the frequency response of the loop to VCO jitter can also be derived. After each VCO switching point is calculated, random jitter is added to the time-point. The response is derived by dividing the FFT of the output jitter with the VCO jitter as illustrated in Figure 12.
  • Filter leakage is a problem if there is some leakage current flowing between PD/CP refresh times. These leakage current will slowly discharge the filter voltage and the VCO frequency will begin to drift between refresh instants ( Figure 13). This can be very troublesome at high divider rates. This effect can be modeled by adding an extra step at time equals zero to the filter voltage equation.
  • the model can also include a divider in the feedback path by quantizing the threshold 'a' in equation (4) by the division ratio.
  • Jitter can be introduced if the CP charging and discharging currents are unequal.
  • the standard sequential PD will have generate both up and down pulses together to avoid dead-zone problems. If the currents are exactly equal the filter is not disturbed. However if the they are unequal, this will introduce jitter on the filter voltage which will modulate the output clock. Extra unit steps can be added to the equations to model this effect.
  • the model can also include a divider in the feedback path to simulate clock multiplication and /or fractional N synthesis.
  • a 3rd order Z-transform of a CP-PLL may be derived using an impulse invariant transform.
  • the open-loop gain G(z) is given by
  • the closed loop transfer function H( ⁇ ) can be found using
  • the model may be synthesized as a digital circuit and /or used as an ADPLL (All Digital PLL). It is to be understood that embodiments of this invention may also be used as or to support software programs executed upon some form of processing core (such as the CPU of a computer) or otherwise implemented or realized upon or within a machine readable medium.
  • a machine readable medium includes any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer).
  • a machine readable medium includes read only memory (ROM); random access memory (RAM); magnetic disk storage media; optical storage media; flash memory devices; electrical, optical, acoustical or other form of propagated signals (e.g., carrier waves, infrared signals, digital signals, etc.); etc.

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

La présente invention concerne un procédé et un appareil qui représentent un signal de sortie d'une pompe à charge sous forme de superposition d'étages de courant, pour lesquels la polarité est inversée par périodes distinctes.
PCT/US2000/042679 1999-12-07 2000-12-07 Modele pour boucle a phase asservie a pompe a charge Ceased WO2001045261A2 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU47139/01A AU4713901A (en) 1999-12-07 2000-12-07 Model for charge pump phase-locked loop

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US23946999P 1999-12-07 1999-12-07
US60/239,469 1999-12-07

Publications (2)

Publication Number Publication Date
WO2001045261A2 true WO2001045261A2 (fr) 2001-06-21
WO2001045261A3 WO2001045261A3 (fr) 2002-02-21

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013117751A2 (fr) 2012-02-10 2013-08-15 Novo Nordisk A/S Méthodes liées au traitement des maladies inflammatoires
WO2013164440A1 (fr) 2012-05-03 2013-11-07 Novo Nordisk A/S Procédés relatifs au traitement de maladies et de troubles inflammatoires
EP3098968A1 (fr) * 2015-05-27 2016-11-30 Altera Corporation Modèle de simulation du comportement de boucle à phase asservie de récupération de données d'horloge
CN108471307A (zh) * 2017-10-30 2018-08-31 四川和芯微电子股份有限公司 电荷泵电路
US10289778B2 (en) 2014-07-31 2019-05-14 Samsung Electronics Co., Ltd. Simulating electronic circuits including charge pumps

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH064351A (ja) * 1992-06-24 1994-01-14 Toshiba Corp ビジュアル・シミュレーション装置
US5987238A (en) * 1996-11-29 1999-11-16 Cadence Design Systems, Inc. Method and system for simulating and making a phase lock loop circuit

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013117751A2 (fr) 2012-02-10 2013-08-15 Novo Nordisk A/S Méthodes liées au traitement des maladies inflammatoires
WO2013164440A1 (fr) 2012-05-03 2013-11-07 Novo Nordisk A/S Procédés relatifs au traitement de maladies et de troubles inflammatoires
US10289778B2 (en) 2014-07-31 2019-05-14 Samsung Electronics Co., Ltd. Simulating electronic circuits including charge pumps
EP3098968A1 (fr) * 2015-05-27 2016-11-30 Altera Corporation Modèle de simulation du comportement de boucle à phase asservie de récupération de données d'horloge
US9898561B2 (en) 2015-05-27 2018-02-20 Altera Corporation Behavioral simulation model for clock-data recovery phase-locked loop
CN108471307A (zh) * 2017-10-30 2018-08-31 四川和芯微电子股份有限公司 电荷泵电路
CN108471307B (zh) * 2017-10-30 2021-05-28 四川和芯微电子股份有限公司 电荷泵电路

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Publication number Publication date
WO2001045261A3 (fr) 2002-02-21
AU4713901A (en) 2001-06-25

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