WO2000018145A1

WO2000018145A1 - Hitless software activation/switchover through usage of class interface towards target hardware

Info

Publication number: WO2000018145A1
Application number: PCT/EP1999/006403
Authority: WO
Inventors: Hans-Jürgen GAPPA; Joachim Ebinger
Original assignee: Nokia Telecommunications Oy; Nokia Networks Oy
Current assignee: Nokia Oyj
Priority date: 1998-09-19
Filing date: 1999-09-01
Publication date: 2000-03-30
Anticipated expiration: 2001-03-19
Also published as: AU5857399A; DE19843048C2; DE19843048A1

Abstract

The invention relates to a method for a change of access of software stored in a first memory (FB1) to software stored in a second memory (FB2) in the network node of a telecommunications network. To provide a method which enables a safe change where disturbances of data transmission through the network node are avoided, the method comprises the following steps: change of access of at least one software area of the network node from the software of the first memory (FB1) to the software of the second memory (FB2); during the initialisation phase of the software areas (SWB1, SWB2), in which a new configuration corresponding to the new software in the software areas (SWB1, SWB2) takes place, writing of the configuration values generated for the hardware (HW) to a buffer memory (SP) whose values can be transferred to the hardware while at the same time disabling the transfer; and after completion of the initialisation phase in all software areas (SWB1, SWB2) of the network node, which software areas supply configuration values for the hardware (HW), transmitting all current configuration values from the buffer memory (SP) to the hardware (HW). The invention also relates to a network node of a telecommunications network for implementing such a method.

Description

Hitless software activation/switchover through usage of class interface towards target hardware

The invention relates to a method for a software change of access from software stored in a first memory to software stored in a second memory in the network node of a telecommunications network. The invention also relates to a network node of a telecommunications network, said node comprising a first memory and a second memory for storing one software version each, as well as hardware responsible for controlling the data traffic passing the network node and a buffer memory, into which memory, configuration values can be written which are generated for the hardware by at least one software area of the network node which software area is coupled to the software used, from where the configuration values can be made available to the hardware.

In telecommunications networks, network nodes are used for various tasks such as for example for data multiplexing. On the software level, the network nodes comprise various software areas such as access to network management, application-related software and access to the hardware used for data transfer through the network node. The various software areas generate the configuration values required by the hardware for carrying out the data transfer. These configuration values can be made available to the hardware in that they are written into registers contained in the hardware. The configuration values written into the registers can either be values changeable during the execution time of application software or else, configuration values can comprise default values which are set once at the program start by an initialisation software and then kept.

The updateable software for the node which also helps to determine the configuration values delivered to the hardware, is stored in a memory (flash bank) . Usually in network nodes two independent memories are provided, with a different software version being storable in each of these memories. In this way it is possible, during continuous operation of the node, to load a new software version into the memory not being used at the time. After completion of loading, especially after completion of loading in all or selected nodes of the network, a changeover from the software in the memory used so far to the software in the second memory can take place without interrupting the data traffic through the node.

However, during such a change in software, the problem arises that in spite of an immediate changeover, the data traffic through the access node can be disturbed. During an initialisation phase the new software causes various software areas of the software level of the network node, such as for example the application-oriented software, to configure anew without any coordination amongst themselves. If the resulting non-coordinated configuration values are output to the hardware used for controlling the data traffic, then these values are used for further control, which can lead to an interruption or a deterioration of the data transfer.

In practical application, each software area carries out a check irrespective of other software areas, with the check intended to determine whether a restart was caused by an interruption in the power supply or by a change of access to other software. In this, there is no check of the point in time at which the setting of hardware values is enabled again. An independent check of the status, carried out by the individual software areas, is expensive. In addition the lack of control of the renewed permission to write to the register, can lead to values being placed in the hardware which do not mach, thus presenting the danger of a disturbance to the data transfer in spite of the checks carried out by the individual software areas .

It is thus the object of the invention to provide a method which for a network node of a telecommunications network allows a safely effected change from software stored in a first memory of the node to software stored in a second memory of the node, in which disturbances of the data transmission through the network node are avoided. The invention is also based on the object of providing an improved network node which makes such a change possible.

According to the invention, this object is firstly met by a method for a software change of access from software stored in a first memory to software stored in a second memory in the network node of a telecommunications network, with the configuration values required by hardware for data traffic through the node being provided by at least one software area of the network node coupled to the software of the current memory, characterised by the following steps:

change of access of the software area of which there is at least one, from the software of the first memory to the software of the second memory; during the initialisation phase of the software area of which there is at least one, of the network node, in which a new configuration corresponding to the new software in the software area, of which there is at least one, takes place, writing of the configuration values generated for the hardware to a buffer memory whose values can be transferred to the hardware while at the same time disabling the transfer of the values from the buffer memory to the hardware; and

after completion of the initialisation phase in all software areas of the network node, which software areas supply configuration values for the hardware, transmitting all current configuration values from the buffer memory to the hardware.

Secondly, with a network node of a telecommunications network, this object is met according to the precharacterising part of claim 7 in that means for disabling the transfer of the configuration values written to the buffer memory by the software area of which there is at least one, are allocated to the network node during the initialisation phase of the software area of which there is at least one, after a change of the software, and for causing the output of the entire current content of the buffer memory to the hardware after completion of the initialisation phase of all integrated software areas.

The solution according to the invention takes advantage of the fact that the data transfer through the network node can be maintained for a while by the hardware with existing non-updated configuration values, without problems occurring. For this reason, the configuration values generated during the initialisation phase after a change of access to new software, can first be placed in a buffer memory without it becoming necessary to immediately hand on the configuration values to the hardware. But rather, according to the invention, this transfer to the hardware only occurs when the initialisation phase is completed and when the individual configuration values are matched so that they can sensibly be used by the hardware.

The method according to the invention and the network node according to the invention thus provide the advantage that they permit a change from one software version to another software version in a network node, with said change ensuring uninterrupted error-free data traffic through the node even during the change.

In addition, a single common solution is created for all software areas, thus permitting not only fast development but also simplified maintenance and better detection of errors .

Preferred embodiments of the solutions according to the invention are provided in the subordinate claims .

It is particularly advantageous if the method according to the invention provides that during detection of a fault after changing the software in the second memory, a change to the software in the first memory takes place.

For if the error is already detected during the initialisation phase, then no access to the configuration values of the new software in the second memory takes place, as a result of which further disturbances of the data transfer could be caused. Instead, the configuration values existing in the hardware are used until such time that after changing back to the old software in the first memory, the initialisation phase relating to the old software has been completed. In this way a disturbance of the data transfer can be prevented even in the case of faulty new software, if the fault is detected prior to releasing the buffer memory for transmitting the configuration data to the hardware.

Below, the invention is illustrated in more detail by means of drawings as follows:

Fig. 1 is a diagrammatic representation of the software level of a network node;

Figs. 2a, 2b are diagrammatic representations of an exemplary progression in transmitting configuration values without changing the software of a network node; and

Figs. 3a to 3c are representations of an exemplary progression in transmitting configuration values immediately after changing the software of a network node according to the method according to the invention.

Fig. 1 provides an overview of the software level in a network node of a telecommunications network.

It represents five different software areas SWB1-S B5 belonging to the software level. The area designated S B4 creates access for the node to a management computer. By way of class interface KS and a RAM buffer memory (not shown) the software area S B3 has access to the hardware HW of the node, said hardware HW being responsible for data transmission through the network node. Various functions in the network node have been allocated to the software areas SWBl, SWB2 and SWB5. By way of the RAM buffer memory, the software area SWB3 transfers configuration values generated by the software areas SWBl, SWB2 which are necessary for data transmission, to the hardware H . In this, the RAM buffer memory forms part of the program RAM memory in which for example delay-time variables or similar values are stored.

In addition, a control block CB is connected to the software level, said control block comprising two flash banks FBI, FB2. In the first flash bank FBI, the currently used software is stored. A newer software version can be written into the second flash bank FB2. This writing activity can take place either locally on the network node or else via a remote computer which can also communicate with several network nodes.

If the network node, after writing in a new software version into the second flash bank FB2, receives a signal via the software area SWB4 that a changeover to the new software version is to take place, then a change to the new software is triggered in the software areas SWBl, SWB2 of the network node. Corresponding with the new software, the software areas SWBl, SWB2 start to reconfigure. Only after completion of an initialisation phase are the areas ready again, and also matched to each other, to the extent that sensible configuration values for the hardware can be provided.

Figs. 2a and 2b show the transmission of configuration values in regular operation of the network node without software exchange. The configuration values generated by the various software areas SWBl, SWB2, are transmitted by way of a software-based class interface KS, for example by means of a C++ ASIC class, to the RAM buffer memory SP and from there onward to one of several configuration registers REG (ASIC register map) of the hardware HW .

In order to change a bit in an 8-bit configuration register REG, the entire byte must be written anew, with the other 7 bits having to correspond to the previous values. Any deviation can cause errors in the transmission of the data through the network node. However, this poses a problem in that at least some such 8-bit configuration registers REG are often executed as "write only" registers, so that the 7 bits which should not change cannot be read out again in order to set the correct values during rewriting.

For this reason it is sensible to write into the non- readable area of the ASIC register map by way of a RAM buffer memory SP. In this way, the content of the buffer memory SP can be accessed any time (Fig. 2b), thus ensuring that when resetting a byte of one of the configuration registers REG, only the bit(s) to be changed differ (s) from the existing byte.

By contrast, for all "read-and-write" registers of the hardware, writing via a buffer memory is not necessary in normal operation because the values can be read-out again .

Figs. 3a-3c show the transmission of configuration values generated by the software areas SWBl, SWB2 for the configuration registers REG, for the case where a change to new software is made. A RAM buffer memory is provided for all configuration registers REG of the hardware HW, with each of Figs. 3a-3c showing only one RAM buffer memory SP allocated to a "write only" register. As is the case in Figs. 2a and 2b, the configuration values generated by the software areas SWBl, SWB2 are written into a RAM buffer memory SP and in the case of "write only" registers are read-out again from there, to obtain the hitherto current values for further writing activities. However, by contrast to the method of Figs. 2a, 2b, for the time being there is no transfer to the respective configuration register of the hardware HW, of values newly read into the RAM buffer memory SP. As long as the various software areas SWBl, SWB2 of the software level of the network node are still in the initialisation phase after a change of software, and as long as no useable configuration values are available yet, transfer of the values from the RAM buffer memory SP to the configuration registers REG of the ASIC register maps is disabled.

As a rule, during the initialisation period, data transfer through the network node can be carried out for a while using the old values in the ASIC register map, without any interruption of the data transfer taking place .

The entire content of the RAM buffer memory SP, which during the initialisation phase had been continually updated via the class interface, is copied into the respective hardware configuration register REG only once all affected software areas SWBl, SWB2 of the network node have completed initialisation.

During the further procedure, as is described in relation to Figs. 2a, 2b, in each instance the register in which a bit is to be changed is reset as required via the RAM buffer memory SP, after, for information concerning the current content, the byte of the RAM buffer memory SP pertaining to the register has been read out from the class interface KS .

Claims

A method for a change of access from software stored in a first memory (FBI) to software stored in a second memory (FB2) in the network node of a telecommunications network, with the configuration values required by hardware (HW) for data traffic through the node being provided by at least one software area (SWBl, SWB2) of the network node coupled to the software of the current memory, characterised by the following steps:

change of access of the software area of which there is at least one, from the software of the first memory (FBI) to the software of the second memory ( FB2 ) ;

during the initialisation phase of the software area (SWBl, SWB2) of which there is at least one, of the network node, in which a new configuration corresponding to the new software in the software area (SWBl, SWB2 ) , of which there is at least- one, takes place, writing of the configuration values generated for the hardware (HW) to a buffer memory (SP) whose values can be transferred to the hardware (HW) while at the same time disabling the transfer of the values from the buffer memory (SP) to the hardware (HW) ; and

after completion of the initialisation phase in all software areas (SWBl, SWB2) of the network node, which software areas supply configuration values for the hardware (HW) , transmitting all current configuration values from the buffer memory (SP) to the hardware (HW) .

2. A method according to claim 1, characterised in that outside of the initialisation phases at least a part of the configuration values are always made available by the software areas (SWBl, SWB2) of the hardware (HW) by way of the buffer memory (SP) .

3. A method according to claim 1 or 2, characterised in that for access of the software areas (SWBl, SWB2) to the hardware (HW) , a class interface, for example implemented by a C++ ASIC class, is generated within the framework of a transmission hardware driver

(SWB3) , with the buffer memory (SP) being integrated into said software areas (SWBl, SWB2).

4. A method according to one of the preceding claims, characterised in that prior to the change from the software in the first memory (FBI) to the software in the second memory (FB2), a new software version is written to the second memory (FB2) .

5. A method according to one of the preceding claims, characterised in that in each instance, writing of a new software to the respective second memory (FB2) takes place locally or by way of a remote computer.

6. A method according to one of the preceding claims, characterised in that when a fault is detected after the change in software to the second memory (FB2), a change back to the software in the first memory (FBI) takes place.

. A network node of a telecommunications network, said network node comprising a first memory (FBI) and a second memory (FB2), in each instance for storing a software version, as well as comprising hardware (HW) responsible for controlling the data traffic passing through the network node, and a buffer memory (SP) into which configuration values for the hardware (HW) can be written by at least one software area (SWBl, SWB2) coupled to the software used, of the network node, and from which buffer memory (SP) the configuration values of the hardware (HW) can be made available,

characterised in that means for disabling the transfer of the configuration values written to the buffer memory (SP) by the software area (SWBl, SWB2) of which there is at least one, are allocated to the network node during the initialisation phase of the software area (SWBl, SWB2) of which there is at least one, after a change of the software, and for causing the output of the entire current content of the buffer memory to the hardware (HW) after completion of the initialisation phase of all integrated software areas (SWBl, SWB2).

8. A network node according to claim 7, characterised in that the hardware comprises several configuration registers, in particular an ASIC register map, for storing the configuration values received from the buffer memory (SP) .

9. A network node according to claim 7 or 8, characterised in that the buffer memory (SP) is a RAM buffer.

0. A network node according to one of claims 7-9, characterised in that in each instance, the first and the second memory (FBI, FB2) is a flash bank.