WO2000010248A1 - Circuit for detecting peak voltage in integrated circuits - Google Patents

Abstract

In order to realize a cost-effective circuit for detecting peak voltage in integrated circuits having a digital-analog converter (DA2) disposed on the output, a forward-backward counter (AAZ) is provided in front of the digital-analog converter (DA2), which rapidly counts forward to a count state corresponding to a peak value when a new peak value appears and then slowly counts backward.

Description

description

Circuit arrangement for peak voltage detection for integrated circuits

The invention relates to a circuit arrangement for peak voltage detection for integrated circuits according to the preamble of claim 1.

In order to be able to detect a peak value of a voltage in an integrated circuit for internal purposes, analog peak voltage detectors and peak voltage detectors with an analog-digital converter are known.

Analog peak voltage detectors require an external storage capacitor due to their size and, in turn, an additional connection option. Both increase the cost of peak voltage detection.

A peak voltage detector with an analog-to-digital converter requires a relatively large chip area in an integrated circuit. The increased need for chip area is also due to the provision of a digital comparison and a sequence control that is necessary in this case. The increased need for chip area increases the costs for the peak voltage detection.

It is therefore the object of the present invention, starting from a circuit arrangement of the type mentioned at the outset, to provide a circuit arrangement for peak voltage detection for integrated circuits which is inexpensive.

This object is achieved by a circuit arrangement according to the features of claim 1.

Then an up / down counter with a digital-to-analog converter is used simultaneously as a peak value detector and peak value memory used. The peak value is recorded by quickly waiting up until the peak value is reached. The peak value is stored by slow downward numbers. Due to the slow downward numbers, the recorded value remains virtually constant.

Advantageous embodiments of the invention are the subject of dependent claims.

If the number of bit positions of the up / down counter is selected to be significantly higher than that of the digital-to-analog converter, the low-order bit positions of the up / down counter can be dynamically changed between the peak value acquisition and peak value storage processes without the analog output signal on Digital-to-analog converter changes by more than the voltage corresponding to an LSB step (LSB = Low Significant Bit) of the analog-to-digital converter.

The circuit arrangement enables the stored peak voltage value m to be tapped in digital or analog form without any problems for appropriate further processing.

An exemplary embodiment of the invention is explained in more detail below with reference to a drawing. Show in it

FIG. 1 shows an analog peak voltage detector in accordance with the prior art in a pnzip view,

FIG. 2 shows a peak voltage detector with an analog-digital converter in accordance with the prior art in a pin diagram representation, and

Figure 3 shows a circuit arrangement for peak voltage detection for integrated circuits according to the invention in pnzzipdarstellung.

The analog peak voltage detector shown in FIG. 1 has an m series-connected input diode D and m given order and m parallel connection to a storage capacitor C and output resistor R.

A peak value is detected by the input diode D and stored by the storage capacitor C.

The peak voltage detector with analog-digital converter AD shown in FIG. 2 has, in analogy to the analog-digital converter AD in the order given and m series connection, a sequence control ASV combined with a comparator, furthermore a memory S and a first digital-analog converter DA1.

The analog-digital converter AD detects an input value which is compared to the sequence control ASV combined with a comparator after a short time interval with a previous value. Depending on the result of the comparison, the new or old value is stored digitally in the memory S. The first digital-to-analog converter DA1 converts the stored digital value m into an analog output voltage.

The circuit arrangement shown in FIG. 3 for peak voltage detection for integrated circuits has a comparator K with a plus and a minus input, an oscillator OSZ, an up / down counter AAZ and a second digital / analog converter DA2. Furthermore, a frequency divider FT and a clock switch TU are provided.

An analog input signal E, the peak value of which is to be recorded, is applied to the plus input of the comparator K. The minus input of the comparator K is connected to a circuit arrangement output A, which is simultaneously connected to an output of the second digital / analog converter DA2. The circuit arrangement output A and the minus input of the comparator K thus have the peak value converted by the second digital-to-analog converter DA2 m and stored digitally by the up / down counter AAZ. The result of a comparison of the analog input signal E carried out directly by the comparator K with the analog peak value at the circuit arrangement output A leads to a signal at the output of the comparator K, which as an up / down signal AAS to a payment direction input ZRE of the up / down. Counter AAZ and is applied to a control input of the clock switch TU. The up / down signal AAS controls the up / down counter AAZ either m an upward or m a downward state. At the same time it controls

Up / DOWN signal AAS the clock switch TU m one of two possible positions ST1 or ST2.

In the first position ST1, the clock changeover switch TU switches through an oscillation signal f _{os =} emitted by the oscillator OSZ to a clock input TE of the up / down counter AAZ. In the second position ST2, the clock switch TU switches a result signal f _os _ emitted by the frequency divider FT. to the clock output TE of the up / down payer AAZ. The result _signal f _os is, based on the oscillation _signal f _0j, a clock signal divided by the frequency divider FT by a factor 2 ^r , with n >> 1, 2, 3, ....

The up / down counter AAZ has a higher resolution than the second digital-to-analog converter DA2 connected to it. For example, if the second digital-to-analog converter DA2 has 8 bit positions, the up / down counter AAZ can have 16 bits.

The second digital-to-analog converter DA2 is connected to the most significant bit positions of the up / down counter AAZ. If the up / down counter AAZ has 16 bit positions, the second digital / analog converter DA2 is connected to the most significant bit positions D8 to D15 of the up / down counter AAZ. The stored peak value is present at the analog output of the second digital-to-analog converter DA2 and, as already mentioned at the beginning, is connected to the minus input of the comparator K.

If a new peak value arrives at the input of the circuit arrangement, the output of the comparator K with the up / down signal AAS switches the up / down counter AAZ into the up-counting state and the clock switch TU to the first position ST1. The clock switch TU thus applies the oscillation _signal f _osz , which is higher in frequency than the result _signal f _{oszt of} the frequency divider FT, to the clock input TE of the up / down counter AAZ. The up / down counter AAZ counts up at high speed. The second digital-to-analog converter DA2 simultaneously outputs the numerical value set in the up / down counter AAZ as an analog voltage. The counting continues until the peak output value is slightly higher than the current input signal E. Thereafter, the comparator K switches the up / down signal AAS so that the clock signal present at the clock input TE of the up / down counter AAZ is changed to correspondingly slower frequencies. For this purpose, the clock changeover switch TU is in the second position ST2. The up / down counter AAZ slowly reduces its counter reading in accordance with the reduced frequency f _{os =} / 2 ^π .

As long as there is no new peak value at the input of the circuit, the counter reading of the up / down counter AAZ is slowly lowered. If no peak value _arrives at all, a time of 2 ^m / (f _osz / 2 ⁿ ) = 2 ^m * 2 ⁿ / f _OS z, with 2 ^m = highest count of the up / down counter AAZ, until the up / AbZähler AAZ has counted down from the highest counter reading to counter reading 0.

In a special embodiment of the circuit arrangement it is provided that the numerical value of the up / down counter AAZ can be tapped digitally. When dimensioning the frequency output by the oscillator OSZ and the frequency division carried out by the frequency divider FT, it must be ensured that the frequency output by the oscillator OSZ is high enough to get the up / down counter AAZ fast enough to the new peak value even with short signal peaks to be able to adapt.

The division ratio 2 ⁿ , on the other hand, should not be chosen too small, so that the stored peak value is not lost during longer signal pauses. In addition, the clock ratio 2 ⁿ should not be chosen too large, so that the output level of the circuit arrangement indicates this correctly after a suitable time in the case of operations with falling peak values.

Claims

claims 1. Circuit arrangement for peak voltage detection for integrated circuits with a digital-to-analog converter arranged at the output and having several bit positions, characterized in that before the digital-to-analog converter (DA2) em, when a new peak value occurs up to a number corresponding to the peak value, it goes up rapidly and then slow down paying up / down payer (AAZ) is provided. 2. Circuit arrangement according to claim 1, characterized in that the up / down counter (AAZ) has more bit positions than the digital-to-analog converter (DA2) and that the up / down counter (AAZ) m the way the digital-to-analog converter ( DA2) is connected upstream that the digital-to-analog converter (DA2) is connected to the most significant bit positions of the up / down counter (AAZ). 3. Circuit arrangement according to one of claims 1 or 2, characterized in that the up / down payer (AAZ) has taps for tapping the digital counter. 4. Circuit arrangement according to one of the preceding claims, characterized in that a comparator (K) with a minus and a plus input is provided, at the positive input of which an analog input signal (E) is applied and the minus input with an output of the digital-analog wall. lers (DA2) and in parallel with a circuit arrangement output (A) that an output of the comparator (K) is connected to a payment direction input (ZRE) of the up / down counter (AAZ) and in parallel with a control input of a clock switch (TU) that an oscillating signal (f _{os =} ) emitting oscillator (OSZ) and a frequency divider (FT) are provided, of which the oscillator (OSZ) with one of two inputs gears of the clock switch (TU) and the frequency divider (FT) is connected to the other of the two inputs of the clock switch (TU), and that one in a first position (ST1) of the clock switch (TU) with that connected to the oscillator (OSZ) Input connected and in a second position (ST2) of the clock switch (TU) with the input connected to the frequency divider (FT) connected output of the clock switch (TU) is connected to a clock input (TE) of the up / down counter (AAZ).