[go: up one dir, main page]

WO2000003439A1 - Blindage de protection thermique et antibruit pour circuit integre - Google Patents

Blindage de protection thermique et antibruit pour circuit integre Download PDF

Info

Publication number
WO2000003439A1
WO2000003439A1 PCT/US1999/015335 US9915335W WO0003439A1 WO 2000003439 A1 WO2000003439 A1 WO 2000003439A1 US 9915335 W US9915335 W US 9915335W WO 0003439 A1 WO0003439 A1 WO 0003439A1
Authority
WO
WIPO (PCT)
Prior art keywords
integrated circuit
conductive layer
substrate
bonding pad
heat
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US1999/015335
Other languages
English (en)
Inventor
Akira Ishikawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ball Semiconductor Inc
Original Assignee
Ball Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ball Semiconductor Inc filed Critical Ball Semiconductor Inc
Publication of WO2000003439A1 publication Critical patent/WO2000003439A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0501—Shape
    • H01L2224/05016—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05023—Disposition the whole internal layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/1017—Shape being a sphere

Definitions

  • the invention relates generally to semiconductor integrated circuits, and more particularly, to an apparatus and method for reducing noise and/or heat on a device such as a spherical-shaped semiconductor integrated circuit.
  • Electrical devices such as semiconductor integrated circuits are advancing in many ways. For example, many devices are seeing an increase in operating speed, overall size, and number of transistors. These advancements, while creating smaller and faster electrical devices, result in increased electronic noise from the device. Furthermore, power consumption and heat generation inside the device have greatly increased.
  • heat convection is a heat spreader thermally coupled to the device. Heat flows from the device to the heat spreader. The heat spreader is sufficiently large so that it can receive a large amount of heat from the device and can efficiently radiate the heat, thereby cooling the device.
  • convection is a heat sink thermally coupled to the device, combined with a moving air mass. Heat flows from the device to the heat sink, and as the air mass moves across the surface of the heat sink, heat is transferred to the air mass, where it is carried away from the heat sink and the attached device.
  • Chips are formed from a flat surface semiconductor wafer.
  • the semiconductor wafer is first manufactured in a semiconductor material manufacturing facility and is then provided to a fabrication facility. At the latter facility, several layers are processed onto the semiconductor wafer surface. Once completed, the wafer is then cut into one or more chips and assembled into packages. Although the processed chip includes several layers fabricated thereon, the chip still remains relatively flat.
  • the present invention accordingly, provides an apparatus and method for reducing noise and/or heat on a device such as a spherical-shaped semiconductor integrated circuit.
  • a device such as a spherical-shaped semiconductor integrated circuit.
  • one embodiment provides an integrated circuit formed around a spherical substrate.
  • the integrated circuit includes one or more bonding pads for connecting to power supplies and/or other devices.
  • Surrounding the integrated circuit is a conductive layer.
  • the conductive layer is not connected to the integrated circuit, except through a power supply bonding pad.
  • the conductive layer serves to absorb energy such as heat and/or electromagnetic noise.
  • One advantage of the present invention is that the conductive layer is physically part of the integrated circuit device. This facilitates both energy absorption and handing of the device.
  • Fig. 1 illustrates a spherical shaped integrated circuit device according to one embodiment of the invention.
  • Fig. 2 is a cutaway view of the device of Fig. 1.
  • Fig. 3 illustrates a flat shaped integrated circuit device according to another embodiment of the invention.
  • Fig. 4 is a cutaway view of the device of Fig. 3.
  • Fig. 5 is a flowchart for one embodiment of the present invention.
  • the reference numeral 10 designates, in general, a semiconductor integrated circuit device, preferably of a generally spherical shape.
  • the device could be of the same type formed according to the technique disclosed in the above-identified Patent Application Ser. No. 08/858,004.
  • the device 10 is covered by a protective outer coat 12, which may also serve as an identification means for detecting a type (e.g., memory, logic) of the device.
  • a metal shielding layer 14 Located inside the outer coat 12 is a metal shielding layer 14.
  • the shielding layer 14 may be formed by an inductively coupled plasma powder vaporization technique disclosed in Patent Application Ser. No. 09/033,180 filed March 2, 1998 or metal chemical vapor deposition.
  • the outer coat 12 and shielding layer 14 may be one single layer.
  • the device 10 includes several bonding pads, including pads 16a, 16b, 16c, and 16d.
  • the bonding pad 16c is a power pad (e.g., a ground pad). It is understood that other power supplies and/or additional bonding pads may be used to facilitate the functionality of bonding pad 16c.
  • Solder bumps 18a, 18b, 18c, and 18d are electrically attached to bonding pads 16a, 16b, 16c, and 16d, respectively.
  • the metal shielding layer 14 is connected to the bonding pad 16c and solder bump 18c.
  • energy in the form of heat and/or electromagnetic noise is absorbed through the metal shielding layer 14.
  • heat is dissipated through the layer 14 and convected through the solder bump 18c to an external ground (not shown).
  • the reference numeral 50 designates, in general, another, separate embodiment of a semiconductor integrated circuit device, preferably of a generally flat shape.
  • the device 50 is covered by a protective outer coat 52, which may also serve as an identification means for detecting a type (e.g., memory, logic) of the device.
  • the outer coat 52 may include assembly packaging, such as a leadframe, and a packaging material.
  • the packaging material may be plastic, ceramic, or other suitable material.
  • the device 50 includes several bonding pads, including pads 56a - 56i.
  • the bonding pad 56c is a power pad (e.g., a ground pad). It is understood that other power supplies and/or additional bonding pads may be used to facilitate the functionality of bonding pad 56c.
  • Solder bumps 58a - 58i are electrically attached to bonding pads 56a - 56i, respectively.
  • the metal shielding layer 54 is connected to the bonding pad 56c and solder bump 58c.
  • energy in the form of heat and/or electromagnetic noise is absorbed through the metal shielding layer 54.
  • heat is dissipated through the layer 54 and convected through the solder bump 58c to an external ground (not shown).
  • a cutaway view of the device 50 is provided.
  • the cutaway view illustrates a semiconductor substrate 60 and an integrated circuit pattern layer 62.
  • the metal shielding layer 54 actually goes completely around the device 50.
  • one, two or three sides of the metal shielding layer 54, such as a side 54a may be absent.
  • a method 100 may be used to create one or more of the shielding layers on a semiconductor integrated circuit device.
  • the integrated circuit is first fabricated onto the device.
  • the integrated circuit may be completely finished, or may still require a few more fabrications steps.
  • the shielding layer is applied to the outer surface of the integrated circuit.
  • the shielding layer may be a second metal layer applied to the entire integrated circuit.
  • the shielding layer may be applied after the device has been separated from one or more adjoining devices, such as being sawed from a wafer.
  • portions of the shield are removed, as necessary.
  • the shielding layer When the shielding layer is applied to the outer surface, it will electrically connect all of the pads of the device. Since this is seldom desired, portions of the shielding layer must be removed. Specifically, portions that create undesired electrical or magnetic interference must be removed.
  • This removal process can be mechanical, such as a chemi-mechanical polish, chemical such as a wet or dry etch, or by some other means. Certain removal processes are more applicable to different shaped devices, and it is understood that those of ordinary skill in the art can implement the appropriate process.
  • the device is assembled. It is understood, however, that one or more intervening process steps may occur before assembly, such as adding a protective coating on the outside of the shielding layer. It is also understood that different assembly processes are required for different devices. Certain devices, such as the spherical shaped device 10 of Figs. 1-2 may have a relatively simple assembly process of applying a protective coat to the device's outer surface. Other devices, such as the chip 50 of Figs. 3-4, may be mounted onto a lead frame and packaged accordingly.

Landscapes

  • Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

L'invention concerne un dispositif et un procédé permettant de réduire le bruit et/ou la chaleur auxquels un dispositif, tel qu'un circuit intégré (10) à semiconducteur sphérique, est soumis. Le circuit intégré est formé autour d'un substrat (20) sphérique. Une couche conductrice (14) entoure le circuit intégré. La couche conductrice (14) est connectée uniquement à un plot de connexion au moins du circuit intégré. La couche conductrice (14) sert à absorber l'énergie telle que la chaleur et/ou le bruit électromagnétique.
PCT/US1999/015335 1998-07-10 1999-07-07 Blindage de protection thermique et antibruit pour circuit integre Ceased WO2000003439A1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US9364998P 1998-07-10 1998-07-10
US60/093,649 1998-07-10
US34735999A 1999-07-06 1999-07-06
US09/347,359 1999-07-06

Publications (1)

Publication Number Publication Date
WO2000003439A1 true WO2000003439A1 (fr) 2000-01-20

Family

ID=26787771

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1999/015335 Ceased WO2000003439A1 (fr) 1998-07-10 1999-07-07 Blindage de protection thermique et antibruit pour circuit integre

Country Status (1)

Country Link
WO (1) WO2000003439A1 (fr)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4126812A (en) * 1976-12-20 1978-11-21 Texas Instruments Incorporated Spherical light emitting diode element and character display with integral reflector
US5355016A (en) * 1993-05-03 1994-10-11 Motorola, Inc. Shielded EPROM package
US5945725A (en) * 1996-12-04 1999-08-31 Ball Semiconductor, Inc. Spherical shaped integrated circuit utilizing an inductor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4126812A (en) * 1976-12-20 1978-11-21 Texas Instruments Incorporated Spherical light emitting diode element and character display with integral reflector
US5355016A (en) * 1993-05-03 1994-10-11 Motorola, Inc. Shielded EPROM package
US5945725A (en) * 1996-12-04 1999-08-31 Ball Semiconductor, Inc. Spherical shaped integrated circuit utilizing an inductor

Similar Documents

Publication Publication Date Title
US12230661B2 (en) Electronic device package and fabricating method thereof
US7989942B2 (en) IC package with capacitors disposed on an interposal layer
US6229216B1 (en) Silicon interposer and multi-chip-module (MCM) with through substrate vias
KR101870153B1 (ko) 절연 프레임을 이용한 반도체 패키지 및 이의 제조방법
US7482204B2 (en) Chip packaging process
US7787252B2 (en) Preferentially cooled electronic device
KR102031731B1 (ko) 반도체 패키지 및 이의 제조방법
US7061079B2 (en) Chip package structure and manufacturing method thereof
US7202561B2 (en) Semiconductor package with heat dissipating structure and method of manufacturing the same
US10224254B2 (en) Package process method including disposing a die within a recess of a one-piece material
US8304922B2 (en) Semiconductor package system with thermal die bonding
CN112310003A (zh) 具有天线和emi隔离屏蔽件的半导体封装和相关联方法
US20060006517A1 (en) Multi-chip package having heat dissipating path
KR20190007980A (ko) 고방열 팬아웃 패키지 및 그 제조방법
US7312525B2 (en) Thermally enhanced package for an integrated circuit
US20030112604A1 (en) Multi-chip package with embedded cooling element
KR20130077564A (ko) 반도체 패키지 및 그 제조 방법
CN118899231A (zh) 一种半空腔芯片封装结构及方法
WO2000003439A1 (fr) Blindage de protection thermique et antibruit pour circuit integre
US7256494B2 (en) Chip package
US7629682B2 (en) Wafer level package configured to compensate size difference in different types of packages
US20030151132A1 (en) Microelectronic die providing improved heat dissipation, and method of packaging same
WO2025145649A1 (fr) Structure de boîtier de puce, dispositif électronique, et procédé de fabrication d'une structure de boîtier de puce
CN118507438A (zh) 电子封装件及其制法
KR20090077202A (ko) 웨이퍼 레벨 반도체 패키지

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): JP

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
122 Ep: pct application non-entry in european phase