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WO2000069074A1 - Amenagement de modulateur emboite - Google Patents

Amenagement de modulateur emboite Download PDF

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Publication number
WO2000069074A1
WO2000069074A1 PCT/NZ2000/000071 NZ0000071W WO0069074A1 WO 2000069074 A1 WO2000069074 A1 WO 2000069074A1 NZ 0000071 W NZ0000071 W NZ 0000071W WO 0069074 A1 WO0069074 A1 WO 0069074A1
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WO
WIPO (PCT)
Prior art keywords
modulator
output
stage
signal
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/NZ2000/000071
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English (en)
Inventor
Stephen Ian Mann
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tait Electronics Ltd
Original Assignee
Tait Electronics Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tait Electronics Ltd filed Critical Tait Electronics Ltd
Priority to CA002371083A priority Critical patent/CA2371083A1/fr
Priority to AU44406/00A priority patent/AU4440600A/en
Priority to EP00925763A priority patent/EP1177633A1/fr
Publication of WO2000069074A1 publication Critical patent/WO2000069074A1/fr
Anticipated expiration legal-status Critical
Priority to ARP010105352A priority patent/AR031755A1/es
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
    • H03L7/1974—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division
    • H03L7/1976—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division using a phase accumulator for controlling the counter or frequency divider
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
    • H03M7/3002—Conversion to or from differential modulation
    • H03M7/3004—Digital delta-sigma modulation
    • H03M7/3015—Structural details of digital delta-sigma modulators
    • H03M7/302—Structural details of digital delta-sigma modulators characterised by the number of quantisers and their type and resolution
    • H03M7/3022—Structural details of digital delta-sigma modulators characterised by the number of quantisers and their type and resolution having multiple quantisers arranged in cascaded loops, each of the second and further loops processing the quantisation error of the loop preceding it, i.e. multiple stage noise shaping [MASH] type

Definitions

  • This invention relates to modulator arrangements and particularly but not solely to sigma-delta arrangements for radio frequency synthesisers which use fractional division. More particularly the invention relates to nested modulator arrangements with global feedback. Nested arrangements can be used to modulate the fractional division process in a way which is substantially different from traditional processes.
  • Radio communication devices employ frequency synthesisers to control transmission and reception of signals.
  • a synthesiser generally includes a reference oscillator which generates a stable reference frequency signal and is used to determine the output of a frequency controlled oscillator which in turn generates a variable RF output signal. This output signal is generally coupled to an antenna of the communication device by way of one or more mixers which modulate or demodulate the signal for transmission or reception respectively.
  • the synthesiser is programmed by a control unit such as a digital processor to produce the controlled oscillator signal at a range of frequencies as required by the device.
  • phase locked loops Most frequency synthesisers use one or more phase locked loops to generate the variable output signal from the frequency controlled oscillator.
  • the phase locked loop contains a phase discriminator which generates an output according to the phase difference between the reference signal and a feedback signal.
  • the feedback signal is generally produced by dividing the frequency of the output from the controlled oscillator.
  • Output from the phase discriminator is applied to a loop filter which provides a control signal for the controlled oscillator. Voltage rather than current controlled oscillators are normally used.
  • a feedback loop of this kind attempts to match the frequency of the controlled oscillator to a multiple of the reference frequency and stabilise with a zero phase difference between the reference and feedback signals.
  • Frequency division of the output from the frequency controlled oscillator can be implemented in various ways to enable a relatively low frequency reference to determine a wide range of variable RF output.
  • Fractional-N techniques are commonly used and allow the synthesiser to achieve arbitrarily fine frequency resolution. These techniques modulate the instantaneous integer divide ratio of the feedback to the phase discriminator to produce average non-integer division ratios.
  • limit cycles in the modulation signal cause cyclic variation of the division value and generally produce spurious frequencies and additional phase noise in the synthesised output signal.
  • Various cancellation schemes such as phase interpolation have been employed to reduce the fractional spurs and noise but generally require an increase in complexity and cost of the synthesiser to achieve significant reduction in the amplitude of the spurs.
  • Fractional-N synthesisers which use sigma-delta modulation to reduce phase noise and spurs resulting from non-integer division values are well known.
  • a conventional modulator formed by a cascade of modulators is described in US 4,609,881 for example.
  • the sigma-delta technique arose as a development in analog-to-digital conversion and has since been widely used in electronic communication devices for a range of purposes. It involves feedback to improve the effective resolution of a coarse quantiser and allows shaping of the noise which arises from quantisation.
  • input is fed to the quantiser via an integrator with the quantised output being fed back and subtracted from the input.
  • the output of the modulator therefore contains the original signal plus the first difference of the quantisation error.
  • a detailed discussion of sigma-delta techniques can be found in Delta-Sigma Data Converters, IEEE Press 1997.
  • Higher order sigma-delta modulators generally use two or more integrators each receiving feedback from the output to improve the overall noise performance.
  • a cascade is also sometimes used whereby the output of two or more modulators is combined in a way which cancels the noise that they individually produce.
  • output from the integrator of the first modulator is fed to the second modulator.
  • the output of the second is differentiated and subtracted from the output of the first to provide a resultant signal. This leaves the noise as the second difference of the quantisation error of the second modulator, in a form similar to that of a second order modulator.
  • Multi-level quantisers have also been used to improve the stability of higher order and cascaded modulators.
  • these improvements are enabled by a nested modulator having logic control in a global feedback stage.
  • At least one of the nested elements will also preferably include logic control stages.
  • the invention may broadly be said to consist in a nested modulator arrangement comprising: first and second digital modulation stages having respective inputs and outputs, the outputs of the modulation stages being combined to form a common output producing a resultant modulation signal, the input of the first stage receiving a signal formed by combination of an external control signal with a feedback signal derived from the resultant modulation signal, and the input of the second stage receiving an internal control signal from the first stage.
  • the invention may be said to consist in a cascaded modulator arrangement comprising: two or more modulators each having an output coupled to a common combination stage which produces a resultant output, wherein a first modulator receives an external control signal and subsequent modulators are coupled in series to the first modulator so that each receives a control signal from a preceding modulator, and at least one of the modulators is a nested modulator as set out above.
  • Figure 1 shows a conventional accumulator acting as a first order sigma-delta modulator which might be used in a frequency synthesiser
  • Figure 2 shows a three-stage sigma-delta modulator formed by a cascade of modulators such as shown in Figure 1 ,
  • Figure 3 is an accumulator circuit with logic stages forming an improved first order sigma-delta modulator
  • Figures 4a, 4b are second and third order modulators formed by a nested arrangement of lower order modulators with global feedback
  • Figure 5 is an embodiment of the second order nested modulator in Figure 4a based on the modulator of Figure 3
  • Figure 6 is a table showing how a global feedback logic stage can be implemented in the modulator of Figure 5
  • Figures 7a, 7b show alternative three stage modulators each formed by a cascade including a second order nested modulator
  • Figures 8a, 8b respectively show plots of spectral density for comparison of the performance of a two stage cascade with the second order modulator of Figure
  • FIGS 9a, 9b respectively show sample output from the multi-stage modulator systems of Figures 2, 7a.
  • modulators according to the invention may be constructed in various ways within the scope of the claims.
  • the preferred embodiments are described by way of example only, and are not limited to use in frequency synthesisers.
  • the known components of synthesisers and modulator devices will be understood by a skilled person and a detailed explanation of their function need not be given.
  • Figure 1 shows a simple modulator 10 previously used in control of fractional-N division processes in frequency synthesisers.
  • a controller varies the instantaneous value of N by way of the modulator to create a range of non-integer division values in the feedback path of the phase locked loop.
  • the modulator involves a K-bit adder 11 which receives a control word k from the controller as an input on line 13.
  • a latch 12 holds the current contents c of the adder as another input on line 14.
  • Each clock pulse on line 15 causes the control word to be added to the contents of the adder. If the contents exceed 2 K then an overflow signal is generated on line 16 and causes division by N+l rather than N.
  • the adder will overflow on every 2 K /k clock pulses and produce a signal which represents two-level quantisation of the signal c.
  • the output of the synthesiser is then a non-integer multiple of the reference frequency and the average division value in the feedback path is N + 2 K /k.
  • An accumulator overflow arrangement of this kind functions only approximately as an ideal first order sigma delta modulator.
  • Figure 2 shows a three stage modulator 20 formed by a conventional cascade of first order modulators 21, 22, 23 such as shown in Figure 1.
  • a control word X on line 24 produces a relatively complex signal Y which may be provided to create non-integer division values in the frequency synthesiser.
  • the contents of each accumulator forms an error signal which is provided as an input to the next stage, if any.
  • the overflows of the accumulators can be filtered in various ways to achieve cancellation of successive error signals and reduce phase offsets in the phase locked loop. This leaves only high order error terms in the overall output Y.
  • a conventional selection based on Pascal's triangle is shown.
  • Figure 3 shows a modulator 30 recently developed by the applicant for use in a range of systems such as frequency synthesisers.
  • An n-bit adder 31 has two inputs one of which receives a control word X. The second input receives an error signal e derived from output of the adder after various preferred feedback processes applied to groups of the most and least significant bits.
  • An output logic stage 32 receives a group of t msbs from the adder and operates on the bits during a quantisation process which produces the modulator output Y.
  • a feedback logic stage 33 also receives the group t from adder 31 and operates on the bits in a feedback process which determines overload and stability performance of the modulator.
  • An m-bit adder 34 receives a group of m msbs from the n-bit adder 31 and a group of m bits output by the feedback logic stage 33.
  • a latch 35 receives a group of n-m lsbs from the n-bit adder and a group of m bits from the m-bit adder to form the error signal.
  • the latch receives a clock signal which moves the modulator from one state to the next through addition processes in each of the adders.
  • the output and feedback logic stages may be provided in various ways, such as a dedicated Boolean operation or a multiplexer. Required parameters may be set in hardware or held in registers, for example.
  • FIG. 4a schematically shows a preferred modulator 400 having a nested arrangement according to the invention.
  • a second order modulator is formed by linking a first order modulator 401 to another modulator 402, in an arrangement which can be extended to create still higher order systems.
  • Modulator 401 includes an addition element 403 which receives input on line 404, delay element 405, quantisor 406 which produces output on line 407, and an addition element 408 which produces an error signal on line 409. Addition and delay elements 403 and 405 form an accumulator with output fed back on line 415.
  • Modulator 402 receives the error signal as input and produces output on line 410.
  • the individual outputs on lines 407 and 410 are combined in an addition element 41 1 to form an output signal Y on line 412.
  • An adder 413 at the input of the modulator system combines a control word X with feedback on line 415 derived from signal Y.
  • the input to each modulator stage is summed only once within the particular stage.
  • the resultant output of the arrangement is that signal Y contains only second and higher order error terms.
  • Figure 4b shows a third order modulator 450 formed by linking a first order modulator 451 with a second order modulator 452 such as that in Figure 4a.
  • the arrangement shown is similar but not identical to that of Figure 4a.
  • Output signal Y now contains only third and higher order error terms.
  • an nth order system of this kind can be created by nesting an (n-l)th order system.
  • Each stage or level in the system is preferably formed by an ideal or at least approximate sigma-delta modulator linked to a modulator at a lower level stage , if any.
  • the resultant output is generally a combination of the individual outputs produced at each level.
  • Input to the modulator at each level is derived from an error signal output by the modulator at the next highest level.
  • Input to the system at the highest level is derived from combination of an external control word with feedback from the resultant output.
  • Feedback of this kind may be termed "global" and preferably includes a logic stage.
  • FIG. 5 shows a second order modulator 500 based on the system 400 of Figure 4 and the modulator 30 in Figure 3.
  • the top level modulator 502 is formed by an n-bit adder 503, latch 504, an output logic stage 505, feedback logic 506 and an adder 507, which have been generally described in relation to Figure 3.
  • the logic stages operate in accord with selectable coefficients which may be implemented as previously described.
  • Output from the top level modulator is provided on line 508 by the logic stage 505.
  • a dither signal d may be combined as an input to the feedback logic stage 506 to reduce the likelihood of cyclical patterns.
  • the dither signal is typically a random or pseudo random sequence and is preferably pre- filtered by a transformation (1-z "1 ) to avoid a noise floor.
  • An n-bit error signal is produced on line 509 by a combination of lsbs from latch 504 and msbs from adder 507.
  • the second level modulator 501 receives the error signal and produces an output on line 510.
  • the individual modulator outputs are combined in an m-bit adder 511 to form the resultant output signal Y on line 512.
  • An adder 513 combines an m-bit control word X with feedback derived from the output signal Y.
  • Adder 503 of the top level modulator forms an accumulator arrangement with latch 504 and also receives an n-bit inputs from a combination of the control word X and output from the adder 513.
  • Global feedback on line 515 involves a logic stage 516 which operates according to a set of selectable coefficients to produce a signal on line 520.
  • Figure 6 is a table outlining a possible selection of coefficients for the logic stage 516 in Figure 5.
  • Adder 511 produces a 2-bit output having values ⁇ 0,l,2 ⁇ which are fed back through logic stage 516.
  • Adder 513 might be omitted in this arrangement depending on the range of fractional division values which are required.
  • Figures 7a, 7b respectively show three stage modulators 700, 750 formed by cascades including a second order modulator according to the invention.
  • an input control word X produces a relatively complex signal Y which may be used to create non-integer division values in a fractional-N frequency synthesiser.
  • An error signal output by each stage is provided as an input to the next stage.
  • the outputs of the stages are combined in ways which contain higher order corrections for quantisation errors and thereby reduce phase offsets in the phase locked loop of the synthesiser. Low order error terms may thereby be cancelled in ways which do not necessarily involve the successive rows of a Pascal's triangle arrangement shown in Figure 2.
  • the three stage modulator 700 comprises a second order stage 701 such as that shown in Figure 5 followed by a first order stage 702.
  • the stages may well have different input requirements and produce output and error signals of different bit lengths. Additional logic stages may be required, such as a scaling function 703 which matches the error signal from stage 701 with the input of stage 702.
  • the output of stage 702 is passed through two delay elements 705 and a selection of the output signal and corresponding delayed signals is combined with the output of stage 701 in a combining stage 706.
  • the control word X produces a resultant output signal Y having third order error terms as shown.
  • the three stage modulator 750 comprises a first order stage 751 followed by a second stage 752 such as shown in Figure 5.
  • the stages may have different input and output characteristics, typically due to the modulators including different quantisation functions, and additional logic such as a scaling function 753 may be required.
  • the output of each stage is passed through respective delay element 755 and a simple selection from the outputs and their corresponding delayed signals is made in the combining stage 756.
  • the control word X produces a resultant output signal Y having only high order error terms and may be used as an alternative modulation signal for fractional-N division in a frequency synthesiser.
  • Figures 8a, 8b are respective plots of power spectral density (PSD) in the output of a cascaded modulator formed by two overflow accumulator stages, such as shown in Figure 1, and a second order nested modulator such as that shown in Figure 5.
  • PSD power spectral density
  • Plots with spurs have been generated by deliberate operation of the modulator systems in a limit cycle.
  • the amplitudes of the spurs in Figure 8b are significantly less than those of Figure 8a.
  • Figures 9a, 9b are output samples for the modulator arrangements in Figures 2, 7a respectively.
  • Rows I, II, III in Figure 9a represent output from each of the first order stages 21, 22, 23 respectively before input to the delay elements 25.
  • Row IV represents output from the combination stage 26 as signal Y.
  • Rows I, II, III in Figure 9b represent output from the first stage 502 in Figure 5, and from the first and second order stages 701 and 702 in Figure 7a.
  • Row IV represents output from the combination stage 706.
  • a limit cycle still appears in each output, although in Figure 9b the spurious frequencies which result in the eventual output of the frequency synthesiser are reduced by the relatively active nature of the variations in the signal in Row IV.
  • Modulator arrangements according to the invention can be used in a variety of electronic systems other than frequency synthesisers. In analog-to-digital conversion for example. Various nested and cascade arrangements are possible and those which have been described are given by way of example only.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)

Abstract

L'invention concerne des modulateurs formés selon des aménagements emboîtés d'étages de modulateur d'ordre inférieur avec boucle de rétroaction de sortie globale dirigée vers l'entrée. Un signal de sortie d'erreur à chaque étage forme un signal d'entrée vers l'étage suivant. La boucle de rétroaction de sortie globale comprend de préférence un étage de commande logique. Des modulateurs de ce type peuvent être combinés en cascade pour être utilisés dans des synthétiseurs de fréquence.
PCT/NZ2000/000071 1999-05-11 2000-05-11 Amenagement de modulateur emboite Ceased WO2000069074A1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CA002371083A CA2371083A1 (fr) 1999-05-11 2000-05-11 Amenagement de modulateur emboite
AU44406/00A AU4440600A (en) 1999-05-11 2000-05-11 Nested modulator arrangement
EP00925763A EP1177633A1 (fr) 1999-05-11 2000-05-11 Amenagement de modulateur emboite
ARP010105352A AR031755A1 (es) 2000-05-11 2001-11-16 Disposicion de modulador alojado

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
NZ33570499A NZ335704A (en) 1999-05-11 1999-05-11 Nested digital modulators for frequency synthesis
NZ335704 1999-05-11

Publications (1)

Publication Number Publication Date
WO2000069074A1 true WO2000069074A1 (fr) 2000-11-16

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PCT/NZ2000/000071 Ceased WO2000069074A1 (fr) 1999-05-11 2000-05-11 Amenagement de modulateur emboite

Country Status (6)

Country Link
EP (1) EP1177633A1 (fr)
CN (1) CN1350722A (fr)
AU (1) AU4440600A (fr)
CA (1) CA2371083A1 (fr)
NZ (1) NZ335704A (fr)
WO (1) WO2000069074A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001050611A3 (fr) * 2000-01-07 2001-11-29 Conexant Systems Inc Modulateur de sigma delta destine a la synthese de frequences n-fractionnelles
EP1427108A1 (fr) * 2002-12-03 2004-06-09 Motorola, Inc. Modulateur sigma-delta d'ordre trois pour la mise en forme de bruit dans une boucle à verrouillage de phase et procédé associé
CN117879615A (zh) * 2023-12-05 2024-04-12 北京大学深圳研究生院 模数转换器及其处理方法、设备、介质

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4609881A (en) * 1983-05-17 1986-09-02 Marconi Instruments Limited Frequency synthesizers
US4965531A (en) * 1989-11-22 1990-10-23 Carleton University Frequency synthesizers having dividing ratio controlled by sigma-delta modulator
EP0429217A2 (fr) * 1989-11-22 1991-05-29 Nortel Networks Corporation Synthétiseur de fréquence
US5055802A (en) * 1990-04-30 1991-10-08 Motorola, Inc. Multiaccumulator sigma-delta fractional-n synthesis

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4609881A (en) * 1983-05-17 1986-09-02 Marconi Instruments Limited Frequency synthesizers
US4965531A (en) * 1989-11-22 1990-10-23 Carleton University Frequency synthesizers having dividing ratio controlled by sigma-delta modulator
EP0429217A2 (fr) * 1989-11-22 1991-05-29 Nortel Networks Corporation Synthétiseur de fréquence
US5055802A (en) * 1990-04-30 1991-10-08 Motorola, Inc. Multiaccumulator sigma-delta fractional-n synthesis

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001050611A3 (fr) * 2000-01-07 2001-11-29 Conexant Systems Inc Modulateur de sigma delta destine a la synthese de frequences n-fractionnelles
US6570518B2 (en) * 2000-01-07 2003-05-27 Skyworks Solutions, Inc. Multiple stage delta sigma modulator
EP1427108A1 (fr) * 2002-12-03 2004-06-09 Motorola, Inc. Modulateur sigma-delta d'ordre trois pour la mise en forme de bruit dans une boucle à verrouillage de phase et procédé associé
WO2004051855A3 (fr) * 2002-12-03 2005-01-27 Freescale Semiconductor Inc Agencement, boucle a phase asservie et procede de mise en forme du bruit dans une boucle a phase asservie
US7385451B2 (en) 2002-12-03 2008-06-10 Freescale Semiconductor, Inc. Arrangement, phase locked loop and method for noise shaping in a phase-locked loop
CN117879615A (zh) * 2023-12-05 2024-04-12 北京大学深圳研究生院 模数转换器及其处理方法、设备、介质

Also Published As

Publication number Publication date
CN1350722A (zh) 2002-05-22
EP1177633A1 (fr) 2002-02-06
NZ335704A (en) 2001-01-26
CA2371083A1 (fr) 2000-11-16
AU4440600A (en) 2000-11-21

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