WO2000065651A1 - Semiconductor integrated circuit - Google Patents

Abstract

A semiconductor integrated circuit device comprises a circuit block such as a central processing unit (CB1) synchronized with a clock signal, power supply lines for supplying power to the circuit block, and a timing circuit (TADJ) for the clock signal. The timing circuit adjusts the duty ratio of the clock signal. The adjustment of the duty ratio of the clock signal controls the relative timing between the power supply current flowing through the power supply lines for a circuit responsive to a first state of transition of the clock signal and the power supply current flowing through the power supply lines for a circuit responsive to a second state of transition of the clock signal. This reduces the noises corresponding to the secondary harmonic of the clock signal among the electromagnetic radiation noises due to the change in the power supply current. Accordingly, circuit operation can be achieved without a significant loss of the operation-timing margin. This device is especially suitable for a vehicle electronic system that should suppress noises at frequencies extending to radio frequency bands.

Description

 Description Semiconductor integrated circuit device

Technical field

 The present invention relates to a semiconductor integrated circuit device, and more particularly to a technology for reducing harmonic noise in a specific frequency band. For example, the present invention is applied to a device mounted on an automobile and the like, so-called EMI (Electromagnetic) for a radio frequency band. Interference) It is related to technology effective for reduction. Background art

 2. Description of the Related Art In recent years, in electronic systems using semiconductor integrated circuit devices, high performance and high-speed operation have been achieved in response to technological advances in semiconductor integrated circuit devices. The noise generated by the operation of electronic systems will include non-negligible levels of electromagnetic noise as the operation speeds up. Therefore, it is important for electronic systems to reduce electromagnetic noise emitted from the electronic systems themselves. For example, in equipment mounted on automobiles, the use of semiconductor integrated circuit devices whose operating frequency reaches 40 MHz is started to be considered as necessary, and the electromagnetic noise generated accordingly is 80 MHz. Includes harmonic noise such as z and above. Such harmonic noise components will reach the FM radio frequency band, and if they are emitted outside the electronic system at relatively high levels, they will interfere with FM radio reception.

Conventionally, countermeasures against electromagnetic noise have been taken for the entire equipment using the semiconductor integrated circuit device. Such technology is Nikkei B "Nikkei Electronics" published by Company P Something like the one shown on pages 123 to 148 of the January 3, 1997 issue (N 0.72) . The technology for reducing electromagnetic noise in equipment that uses semiconductor integrated circuit devices as a whole is to prevent electromagnetic noise generated from sources of electromagnetic noise, such as components and wiring in semiconductor integrated circuit devices, in equipment from leaving the housing. Is done. At the same time, semiconductor integrated circuit devices are also required to reduce the generated electromagnetic wave noise.

 One technique for reducing noise is to lower the power supply voltage of a semiconductor integrated circuit device. According to this technology, it is possible to reduce the noise generated from the wiring path by lowering the signal level output from the semiconductor integrated circuit device to the mounting printed circuit board wiring, and also to reduce the operation of the semiconductor integrated circuit device. Since the current can be reduced, noise from the power supply path can also be reduced. However, with this technology alone, noise suppression is required in order to limit the operating power supply voltage at which the circuit can operate and to achieve the required operating speed regardless of the decrease in the load driving force of the circuit. Limits arise.

As another technique, there is a technique of changing the frequency of an operation clock signal. This technique is disclosed, for example, in Japanese Patent Application Laid-Open No. Hei 7-235858. In the technique of changing the frequency of the operation clock signal, for example, the frequency of the clock signal of the semiconductor integrated circuit device is changed within a predetermined range every predetermined time. In this technology, the frequency of the fundamental noise is varied within a predetermined range, and the range of the frequency component where the harmonic noise occurs is expanded, thereby averaging the electromagnetic noise generated from the semiconductor integrated circuit device. By doing so, the generated electromagnetic wave noise is reduced. As still another technique, there is a technique for irregularly generating a delay in a mouthpiece signal. This technology is disclosed in, for example, Japanese Patent Application Laid-Open No. 5-152908 Is shown in In a technique for generating a clock signal with an irregular delay, for example, a clock signal of a semiconductor integrated circuit device is delayed for each pulse, and a plurality of clock signals having different delay times can be used to arbitrarily raise and lower the clock signal. The fall is determined. As a result, the rising and falling timings of the clock signal for operating the semiconductor integrated circuit device are not constant, and the electromagnetic noise generated by each clock signal pulse cancels each other, and the electromagnetic noise is averaged. It will be reduced.

 However, in the technique of varying the frequency of the operation clock signal or the technique of irregularly generating a delay in the clock signal, it is necessary that one circuit be operated by a clock signal having a frequency variation or a delay time variation. Therefore, there is a problem that the operation timing margin of the circuit cannot be made large. In these technologies, noise is dispersed in frequency and time in response to frequency fluctuations and delay time fluctuations, and there is a limit in reducing harmonic noise in a specific frequency band.

 In view of the above technical background, an object of the present invention is to reduce harmonic noise generated in a specific frequency band among the harmonic noise generated from a semiconductor integrated circuit device.

 Another object of the present invention is to reduce subharmonic noise generated in a specific frequency band among subharmonic noises generated from a semiconductor integrated circuit device. Still another object of the present invention is to reduce harmonic noise or subharmonic noise generated in a specific frequency band in a semiconductor integrated circuit device operating in synchronization with a polyphase clock signal. .

Another object of the present invention is to make it possible to use the conventional clock signal design technology as it is, and to easily realize reduction of harmonic noise or subharmonic noise occurring in a specific frequency band. is there. Another object of the present invention is to provide a semiconductor integrated circuit device capable of relatively reducing power supply current noise corresponding to harmonic noise generated in a radio frequency band among harmonic noise with respect to a fundamental frequency of a clock signal. ¾>

 The above and other objects and novel features of the present invention will become apparent from the following description of the present specification and the accompanying drawings. Disclosure of the invention

 A semiconductor integrated circuit device according to the present invention includes a logic circuit block that operates in synchronization with a clock signal, and a timing adjustment circuit that adjusts a phase difference of a current flowing through a power supply wiring. The logic circuit block operates in synchronization with the clock signal, so that an operation current flows in synchronization with the clock signal.

 The clock signal goes to the first transition state, then to the second transition state, then to the first transition state, and so on, periodically and alternately to the first and second transition states. Can be considered to be adopted.

 A logic circuit block is a circuit that operates in synchronization with a first transition state of a clock signal (hereinafter, referred to as a first circuit) because it is a circuit that operates in synchronization with a clock signal. And a circuit that operates in synchronization with the transition state (hereinafter, referred to as a second circuit).

 Therefore, the timing at which the operating current flows through the logic circuit block is synchronized with the first transition state and the second transition state of the clock signal.

 The operating current of the logic circuit block flows to the power supply wiring of the semiconductor integrated circuit device, and changes the power supply current.

The evening adjustment circuit includes a power supply current generated in synchronization with the first transition state of the clock signal and a power supply current generated in synchronization with the second transition state of the clock signal. It operates so as to adjust the phase difference between.

 Thereby, the distribution of the harmonic noise component in the power supply current corresponding to the repetition of the first transition state and the second transition state is changed. If the time from the first transition state to the second transition state of the clock signal is substantially equal to the time from the second transition state to the first transition state, the harmonic noise caused by the change in the power supply current will be , The even harmonic noise with respect to the clock signal has a relatively large level. The timing adjustment circuit reduces a predetermined order harmonic noise level.

 The evening adjustment circuit can take various configurations to conform to the configuration of the logic circuit block.

 The logic circuit block regards the rising edge of the clock signal as the first transition state and operates in synchronization with it.The logic group considers the falling edge of the clock signal as the second transition state and operates in synchronization with it. In the case of mainly using a circuit group, the current flowing through the power supply wiring of the semiconductor integrated circuit device flows in synchronization with the rising edge and the falling edge of the clock signal. In this case, the evening adjustment circuit changes the phase difference between the rising edge and the falling edge of the quick signal for operating the semiconductor integrated circuit device so as to change the phase difference of the current flowing through the power supply wiring. In the case where the present invention is not applied, the clock signal operated by the semiconductor integrated circuit device is set such that the duty ratio is substantially 50%, that is, the phase difference between the rising edge and the falling edge of the clock signal is 1/2. Accordingly, the phase difference of the current flowing through the power supply wiring is also reduced to 1/2.

The change in the phase difference between the rising edge and the falling edge of the clock signal by the timing adjustment circuit is not particularly limited, but may be changed by a circuit configuration that delays the rising edge by a predetermined time or This is enabled by a circuit configuration that delays the edge by a predetermined time. If necessary, the rising and falling edges may be delayed by different times, respectively. As described above, the rising edge and the falling edge of the clock signal are delayed for a predetermined time by the rising edge and the falling edge of the clock signal by the evening adjusting circuit, so that the rising edge and the falling edge of the clock signal are delayed. The edge phase difference is different from 1/2. As a result, of the circuit groups included in the logic circuit block, the current flowing through the power supply wiring by the circuit group that operates in synchronization with the rising edge and the power supply by the circuit group that operates in synchronization with the falling edge The phase difference with the current flowing through the wiring is made different from 1 Z 2. In this way, the phase difference between the current flowing through the power supply wiring when the circuit group operates in synchronization with the rising edge and the current flowing through the power supply wiring when the circuit group operates in synchronization with the falling edge is 1/2. If the phase difference is different from that of the above, the harmonic noise in a specific frequency band will be reduced as compared with when the phase difference is 1/2.

The present invention is further clarified by comparison with the above-described technique for changing the frequency of the operation clock signal and the technique for irregularly generating a delay in the clock signal. It has the characteristic that harmonic noise in the frequency band can be reduced. The present invention also provides a circuit group that operates in synchronization with the first transition of the clock signal and a circuit group that operates in synchronization with the second transition, as is evident from the comparison with the above-described technique that irregularly delays the clock signal. Circuit groups that can operate with a fixed period determined by the period of the clock signal without depending on the phase adjustment by the timing adjustment circuit. The feature is that the operation timing margin can be large and the change can be small. The small change in the operating margin Each circuit group can be operated with a small operation margin, thereby making it possible to prevent each circuit from being improved in performance.

 The timing adjustment circuit can adopt a configuration suitable for a configuration in which the logic circuit block uses a plurality of internal clock signals having different phases. In other words, even if there are a plurality of circuit groups that operate in synchronization with a plurality of internal clock signals having different phases, the operation of each circuit group causes a current to flow through the power supply wiring with a certain phase difference. Because it can be considered. In this case, it is possible to reduce harmonic noise in a specific frequency band by changing the phase difference of the current flowing through the power supply wiring. For this purpose, by connecting the timing adjustment circuit to a desired internal clock signal of the plurality of internal clock signals or by providing the internal clock signal generation circuit with the timing adjustment circuit, a plurality of internal clock signals can be obtained. The phase difference between the rising and falling edges is adjusted. In this case, the timing adjustment circuit connected to each internal clock signal does not need to change the phase difference between the rising edge and the falling edge for all the internal clock signals, or needs to change the phase difference for each internal clock signal. The phase difference may be different, and the semiconductor integrated circuit device as a whole may be in such a state that the phase difference of the current flowing through the power supply wiring is changed from 1/2.

Further, the timing adjustment circuit generates a plurality of clock signals in which the phase difference between the rising edge and the falling edge is changed so that the phase difference of the current flowing through the semiconductor integrated circuit device becomes a different phase difference. By providing a selection circuit for selecting a clock signal having a specific phase difference from the plurality of clock signals, a phase difference of a current flowing through the semiconductor integrated circuit device can be selected, and a frequency band to be reduced can be selected. The harmonic noise of It becomes possible. This facilitates the control of suppressing harmonic noise in a specific frequency band when the period of the clock signal is changed.

 Further, the timing adjustment circuit has a setting circuit for setting a phase difference between a rising edge and a falling edge of the clock signal, and the semiconductor integrated circuit can be freely controlled by the phase difference control data set in the setting circuit. It may be arranged to determine the phase difference of the current flowing through the device. When the semiconductor integrated circuit device includes a microcomputer, the setting circuit is configured by a control register in which the phase difference control data is set and controlled by a central processing unit in the microcomputer, or It may be substantially constituted by a storage circuit that can be referred to by the central processing unit. As a result, the central processing unit sets the above setting circuit, and the timing adjustment circuit sets the phase difference between the rising edge and the falling edge of the clock signal so that the phase difference specified by the setting circuit becomes the same. Change

 Further, the semiconductor integrated circuit device having the timing adjustment circuit is not limited to being formed on one chip semiconductor substrate, but is a multi-chip data processing system composed of a plurality of semiconductor chips. It may be. In this case, each of the semiconductor integrated circuit devices has the above-described timing adjustment circuit, and in each of the semiconductor integrated circuit devices, changes the phase difference of the current flowing through the power supply wiring, thereby causing a harmonic generated in a specific frequency band. By reducing noise, it becomes possible to reduce harmonic noise that occurs in a specific frequency band as a whole data processing system.

In this case, each of the semiconductor integrated circuit devices may not have the above-mentioned timing adjustment circuit, and may have the above-mentioned timing adjustment circuit as a data processing system. Each of them as a data processing system The semiconductor integrated circuit devices can be classified into a plurality of groups that operate in synchronization with the clock signal, and the current flowing on the power supply wiring supplied to the semiconductor integrated circuit devices belonging to each group has a certain phase difference In this case, the data processing system has the above-mentioned timing adjustment circuit, and each of the semiconductor integrated circuit devices changes the phase difference between the clock signals operated synchronously, thereby identifying the data processing system. It is possible to reduce the harmonic noise of the frequency band.

 Also, theoretically, by using the present invention, it is possible to reduce not only harmonic noise in a specific frequency band but also subharmonic noise in a specific frequency band. BRIEF DESCRIPTION OF THE FIGURES

 FIG. 1 is an example of an overall block diagram of a semiconductor integrated circuit device.

 FIG. 2 is a waveform diagram of a single-phase clock signal.

 FIG. 3 is a characteristic diagram showing an example of a change in the noise intensity coefficient of the first to sixth harmonic noises.

 FIG. 4 is a waveform diagram of a multiphase clock signal.

 FIG. 5 is a circuit diagram showing an example of a circuit for generating a two-phase non-overlapping clock signal.

 FIG. 6 is a graph of noise intensity count for each harmonic.

 FIG. 7 is a noise distribution diagram showing an example of a noise distribution of the semiconductor integrated circuit device.

 FIG. 8 is a characteristic diagram showing the intensity of the third to fifth harmonic noises falling within the FM radio frequency band of 60 MHz to 100 MHz.

Figure 9 shows the 2nd to 6th harmonic noise when the phase difference between the rising edge and the falling edge of the clock signal is changed. FIG. 4 is a characteristic diagram showing strength.

 FIG. 10 is a schematic diagram for explaining electromagnetic noise generated from a device on which a semiconductor integrated circuit device is mounted.

 FIG. 11 is a schematic diagram for explaining electromagnetic wave noise generated from the data processing system.

 FIG. 12 is a circuit diagram showing a first embodiment of the evening adjustment circuit according to the present invention.

 FIG. 13 is a waveform chart showing an example of an output signal waveform of the timing adjustment circuit of FIG.

 FIG. 14 is a circuit diagram of a clock signal selection circuit used in a first example of the timing adjustment circuit according to the present invention.

 FIG. 15 is an explanatory diagram of a register which is a first example of a selection signal forming circuit for forming the selection control signals S1 to S3.

 FIG. 16 is an explanatory diagram showing a manner of selecting the clock signals CK d1 to CK d3 with respect to the values of the selection control signals S 1 to S 3.

 FIG. 17 is an explanatory diagram of a register which is a second example of the selection signal forming circuit for forming the selection control signals S1 to S3.

 FIG. 18 is a logic circuit diagram showing an example of a decoder for decoding the outputs S d A and S dB of the register shown in FIG. 17 to form signals S 1 to S 3. FIG. 19 is an explanatory diagram showing an example of a selection mode of the clock signals CKd1 to CKd3 with respect to the values of the decoded signals S1 to S3 of the resist output SdA and Sdb.

 FIG. 20 is a block diagram showing a second example of the timing adjustment circuit according to the present invention.

FIG. 21 is a waveform diagram showing an example of the output waveform of the evening adjustment circuit of FIG. FIG. 22 is a block diagram of a semiconductor integrated circuit device employing a timing adjustment circuit.

 FIG. 23 is a block diagram showing another configuration of a semiconductor integrated circuit device employing a timing adjustment circuit.

 FIG. 24 is a block diagram showing still another configuration of the semiconductor integrated circuit device employing the evening adjustment circuit.

 FIG. 25 is a block diagram showing a configuration of a data processing device employing a timing adjustment circuit.

 FIG. 26 is a schematic view of an automobile equipped with a data processing device using the semiconductor integrated circuit device according to the present invention. BEST MODE FOR CARRYING OUT THE INVENTION

 FIG. 1 is a block diagram of a semiconductor integrated circuit device MPC of an embodiment. Although not particularly limited, the semiconductor integrated circuit device MPC is formed on a single semiconductor substrate such as single crystal silicon by a known CMOS integrated circuit device manufacturing technology. The semiconductor integrated circuit device MPC shown in the figure is composed of a central processing unit CB1, an arithmetic unit CB2, a direct memory access controller CB6, an interrupt controller CB3, a first and a second peripheral so as to constitute a microprocessor. Circuit CB4, CB5, Bus state controller CB7, Evening CB8, AZD converter CB9, Read 'only' memory (ROM) Ml, Random 'Access-memory (RAM) M2, I / O port The circuit includes IOP1 to IOP4, a clock pulse generation circuit CPG, and a timing adjustment circuit TADJ.

Each circuit or circuit block in the figure is coupled to the illustrated data buses DBS 1 and DBS 2, the address buses ABS 1 and ABS 2, and the control bus CBS. I / O port circuits IOP 1 to IOP 4 Are connected to external terminals T a1 to T dn of the semiconductor integrated circuit device MPC. Each circuit or circuit block shown in the figure is connected to an external terminal for receiving power via a power supply line (not shown) of the semiconductor integrated circuit device MPC. Connected to T _VCC and TCJND. The clock signal output via the evening adjustment circuit TADJ is connected to all circuit blocks via a clock signal line (not shown).

 The illustrated central processing unit CB1, arithmetic unit CB2, interrupt controller CB3, etc. receive the clock signal supplied via the timing adjustment circuit TADJ as an operation clock signal. Construct a circuit block.

 The illustrated timing adjustment circuit TADJ will be described in further detail later. Most of the illustrated circuits and circuit blocks except for the evening adjustment circuit TADJ may be the same as those known in the art, and the details thereof are not directly related to the present invention. Description is omitted. Electromagnetic noise that can be considered in the semiconductor integrated circuit device MPC includes electromagnetic noise generated when an internal logic circuit operates in synchronization with a clock signal and current flows through the power supply wiring, and an internal bus noise. Electromagnetic noise caused by signal current flowing through signal wiring such as AB S1, AB S2, DB S1, and DB S2, and input / output port circuits IOP1 to IOP4 of semiconductor integrated circuit devices. Electromagnetic noise generated by charging / discharging the stray capacitance of each of the terminals to give a signal to the external terminals T a1 to T dn which are the input / output terminals of the terminals.

Among these electromagnetic noises, noises other than the noise related to the power supply wiring may be understood to have relatively small levels. That is, the input / output port circuits IOP1 to IOP4 receive various signals to be processed by the central processing unit CB1 in accordance with the program through predetermined ones of the input / output terminals Ta1 to Tdn, and Since various signals formed in accordance with the execution of the program by the central processing unit CB 1 are output to predetermined ones of the terminals, the signals are generally compared with the operation speed of a circuit such as the central processing unit. Therefore, the operation speed is set to be low. Accordingly, the electromagnetic wave noise related to the input / output terminals T a1 to T dn may be regarded as having a low frequency and a low level because the signal change speed of those terminals is relatively slow. . Electromagnetic noise generated by signal wiring such as internal bus wiring has a relatively high frequency due to the high speed of signals to be transmitted by those wirings. However, these signal wirings exclusively transmit signals only, and can take a fine wiring configuration. Therefore, the ratio of the signal wirings to the entire semiconductor integrated circuit device is relatively small. In addition, the power amount corresponding to the signal to be handled by these signal lines is smaller than the power amount in the power supply line. Under these circumstances, it can be considered that the electromagnetic noise caused by the signal wiring also has a relatively small level.

 On the other hand, the electromagnetic noise generated from the power supply wiring is such that the power supply wiring is connected to all the circuit blocks in the semiconductor integrated circuit device and handles the operating current for a circuit such as a clock signal synchronous type. , A high frequency and a high level corresponding to the click signal. That is, a plurality of circuit groups connected via the illustrated bus are operated at the same time under timing control by a clock signal. As a result, a large operating current synchronized with the clock signal flows through the power supply wiring.

The power supply current, that is, the operating current of the circuit block shown in FIG. 0/5 51

 It looks like 14.

 In other words, a logic circuit block consumes current when a plurality of logic gate circuits and arithmetic circuits, such as those present therein, are operated by a clock signal. If a kind of sequential circuit is formed by a connection such as a cascade connection of a plurality of logic gate circuits and arithmetic circuits, the sequential circuit has a plurality of cascaded connections within it under operation control by a clock signal. It operates so that the signal propagates to the circuit one after another. Thus, the sequential circuit consumes current for a period corresponding to the signal propagation delay time of the cascade connection circuit. Even if a circuit is not directly controlled by a clock signal, a circuit that receives an output from a circuit whose operation is controlled by a clock signal at its input will have its input synchronized with the clock signal. By being controlled, it effectively constitutes a circuit whose timing is indirectly controlled by a clock signal.

 A unit circuit, such as a unit logic gate circuit in a circuit block, often has an output at its output node, along with a load drive current to provide a signal to the load, such as stray or parasitic capacitance connected to its output node. A so-called through current also occurs because the output elements, such as p-channel MOSFETs and n-channel MOSFETs for providing signals, conduct simultaneously at the time of signal transition. The shoot-through current also constitutes a current substantially synchronized with the clock signal as it occurs in connection with the signal transition.

As a result, the operating current of the circuit block changes with a relatively large level and time according to the clock signal. Such an operating current is supplied from the power supply wiring. That is, a current flows through the power supply wiring in synchronization with the clock signal, and high-frequency electromagnetic noise is emitted from the entire semiconductor integrated circuit device. Since the current flowing through the power supply wiring is supplied from a power supply device outside the semiconductor integrated circuit device, Not only the device, but also the whole system using the semiconductor integrated circuit device is a factor of generating high-frequency electromagnetic wave noise. Electromagnetic noise based on the current flowing in synchronization with the clock signal, the period of the clock signal to a frequency (hereinafter, f. And shown) not only the fundamental wave noise with, frequency number 2 f _0, frequency 3 f. Electromagnetic noise having a frequency such as harmonic noise or frequency f. / 2, frequency f. Includes electromagnetic noise with frequencies such as 3 or subharmonic noise

とクロック信号 の立ち下がりエッジ （Vhigh

とのそれぞれに同期して動作 する構成とされている場合を示す。 この場合は、 クロック信号の立ち上 がりエッジと立ち下がりエッジとのタイ ミングに同期して、それぞれ電 源電流が流れ、 周波数 2 f 0の基本波ノイズが発生する。 なお、 この場 合、 半導体集積回路装置 MP Cは、 クロック信号の立ち上がりに同期し て動作する回路 （立ち上がり応答回路） と、 立ち下がりに同期して動作 する回路 （立ち下がり応答回路） とを含む。 立ち上がり応答回路と立ち 下がり応答回路とに求められる構成上の相違によって、ク口ック信号の 立ち上がりに同期して流れる電流波形とクロック信号の立ち下がりに 同期して流れる電流波形とに相違が生じる。 そこで、 電源配線を流れる 電流 g ( t ) を、 クロック信号の立ち上がりに同期して流れる電流 g_R ( t ) と、 クロック信号の立ち下がりに同期して流れる電流 g_F ( t ) の和として表わすと、 S (t ) =g_R (t ) +g_F ( t ) ···( 1 ) FIG. 2 shows an example of a single-phase clock signal waveform in which the semiconductor integrated circuit device operates. (A) of FIG. 2 shows the voltage change of the clock signal, the horizontal axis shows time, and the vertical axis shows the voltage intensity. FIG. 2 (b) shows the power supply wiring corresponding to the above clock signal. The horizontal axis indicates time and the vertical axis indicates current intensity. FIG. 2 shows that the semiconductor integrated circuit device MPC detects the rising edge of the clock signal (Vi ^

And the falling edge of the clock signal (Vhigh

Here, a case is shown in which it is configured to operate in synchronization with each of the above. In this case, the power supply currents flow in synchronization with the rising edge and the falling edge of the clock signal, and a fundamental noise having a frequency of 2f0 is generated. In this case, the semiconductor integrated circuit device MPC includes a circuit that operates in synchronization with the rise of the clock signal (rise response circuit) and a circuit that operates in synchronization with the fall (fall response circuit). . Differences in the current waveform that flows in synchronization with the rising edge of the clock signal and the current waveform that flows in synchronization with the falling edge of the clock signal occur due to the difference in configuration required for the rising response circuit and the falling response circuit. . Therefore, representing the current g (t) flowing through the power line, the current g _R (t) flowing in synchronization with the rising edge of the clock signal, as the sum of the current flowing in synchronization with the falling edge of the clock signal g _F (t) When, S (t) = g _R (t) + g _F (t) (1)

Becomes For convenience, when the current flowing in synchronization with the rising edge of the clock signal and the current flowing in synchronization with the falling edge of the clock signal can be considered substantially the same, the above equation (1) becomes

g (t) = g _R (t) + g _R (t— RT)-(2)

Can be expressed as Where R shows the phase difference of g _R (t) and g _F (t). For a clock signal with a duty ratio of 50%, R = 1/2. T is the period of the clock signal, which is 1 / f. Becomes Frequency all-vector G of the n-th harmonic Noizu caused by current flowing through the time power wiring (nf o) is obtained by performing a Fourier transform of the equation (1), g frequency spectrum G of _R (t) _{Using R} (nf.),

G (nf ₀ ) = G _R (nf ₀ ) + e xp (-j nw ₀ RT) G _R (nf ₀ )

= {1 + e X p (-j 2 ττω ₀ Ε T)} G _R (nf)... (3) Where ω. Represents an angular frequency. And the absolute value of G (nf.) Is

IG (nf ₀ ) I = H (nf ₀ ) IG _R (nf ₀ ) |-(4-1)

H (n f 0) = I l + e xp (-j 27rnR) |

= {2 + 2 cos (27rnR)} ^1/ 2-(4-2)

Becomes

FIG. 3 shows an example of a change in the noise intensity coefficient of the first to sixth harmonic noise. In FIG. 3, the vertical axis represents the noise intensity coefficient, and the horizontal axis represents the phase difference. The right side of Fig. 3 shows the correspondence (legend) between the sign assigned to the noise change curve and the harmonic order number. Thus, it is understood that the curve with the square sign is the change curve of the first harmonic noise, and the curve with the round sign is the change curve of the second harmonic noise. In the example of the power supply current waveform shown in Fig. 2 (b), the understanding is easy. Therefore, the difference between the current waveform caused by the operation of the rising response circuit and the current waveform caused by the operation of the falling response circuit is relatively small, and the change in the current waveform corresponding to the repetition of the clock signal is also relatively small. An example is shown.

 However, the current waveform changes according to the difference between the rising response circuit and the falling response circuit. For example, a circuit such as a logic operation circuit configured to receive an input signal at the rising timing of a clock signal and output an output signal at the falling timing of a clock signal is functionally functional. It has both a rising response circuit and a falling response circuit. In this case, the signal input and the signal output are different circuit operations. Therefore, it is not guaranteed that the power supply current when the clock signal rises and the power supply current when it falls have the same waveform.

 The current waveform may also change in multiple cycles of the clock signal, depending on the sequential operation corresponding to the program execution of the central processing unit CB 1 itself and the sequential operation of the circuit controlled by the central processing unit CB 1 . That is, the power supply current changes over a period longer than the period of the clock signal.

 As a result, depending on the power supply current, there may be subharmonic noise having a period longer than that of the clock signal. If necessary, it is possible to set an equation similar to the above equation for subharmonic noise.

FIG. 4 shows an example of the waveforms of the two-phase non-overlapping clock signals ø1 and ø2 formed together with the basic clock signal. That is, (a-1) in FIG. 4 is the period T or the fundamental frequency f. Fig. 4 (a-2) shows the voltage change of the ø1 clock signal of the two-phase clock signal. (a-3) shows the voltage change of the two-phase clock signal of the two-phase clock signal. It is. In FIGS. 4 (a-1) to 4 (a-3), the horizontal axis represents time, and the vertical axis represents voltage intensity. FIG. 4 (b) shows an example of a change in the current flowing through the power supply wiring corresponding to the ø1 clock signal and the ø2 clock signal. The horizontal axis represents time, and the vertical axis represents current intensity. FIG. 5 shows an example of a circuit for generating the above two-phase non-overlapping signal. The current waveform illustrated in (b) of FIG. 4, although not essential, operates in synchronization with the rising edge of the ø1 clock signal and operates in synchronization with the falling edge of the ø2 clock signal The circuits constitute the first group, and the circuit that operates in synchronization with the falling edge of the ø1 clock signal and the circuit that operates in synchronization with the rising edge of the ø2 clock signal are considered to form the second group. It is changed with the form that is done. Under this power supply current, the frequency 2 f is generated by the current flowing when the first group operates and the current flowing when the second group operates. Of the fundamental wave noise. As in the case of the single-phase clock signal, if the current that flows when the first group operates is g _R (t) and the current that flows when the second group operates is g _F (t), the power supply wiring The current g (t) flowing through

S (t) = g _R (t) + g _F (t)-(5)

Can be expressed as For convenience, if the current flowing when the first group operates and the current flowing when the second group operates can be considered substantially the same, the above equation (5) becomes

g (t) = g _R (t) + g _R (i RT) '

Can be expressed as Where R shows the phase difference of g _R (t) and g _F (t). When the first group and the second group operate at regular intervals, R = 1/2. T is the period of the basic clock signal, l / f. Becomes At this time, the nth harmonic noise generated by the current flowing through the power supply wiring Frequency spectrum G (nf.) By using the equation (5) sought Ri by to Fourier transform, g _R (t) of the frequency spectrum _{G R (nf.), G} (nf 0 ) = G _R (nf ₀ ) + exp (-j nw ₀ RT) G _R (nf ₀ )

= {1 + e X p (-j 27Tw ₀ RT)} G _R (nf.) (6) Where ω. Represents an angular frequency. And the absolute value of G (nf o) is

IG (nf o) I = H (nf o) | G _R (nf ₀ ) I-(7)

H (n f o) = | 1 + e xp (-j 2 ττ n R) |

= {2 + 2 cos (27Γ nR)} ^1/2

As in the case of a single-phase clock signal, the noise component can be expressed as an equation.

 Also, in the case of a semiconductor integrated circuit device operated by a multi-phase clock signal, it may be possible to classify the device into three or more groups in the same manner as in the above-described two groups, but even in such a case, there are various cases. The sum of the current flowing for each group is the current flowing in the power supply wiring, and the noise can be captured in the same manner as described above.

 According to the present invention, a current flowing through the power supply wiring of the semiconductor integrated circuit device MPC is treated as a combination of a plurality of currents synchronized with a clock signal, and generated in a specific frequency band by changing a phase difference between the respective currents. Harmonic noise or subharmonic noise.

 The change in the intensity of harmonic noise or subharmonic noise generated in a specific frequency band by changing the phase difference between the currents is expressed by Equation (4-2).

H (nf O) = | 1 + e xp (-j 27rnR) |

Corresponds to changing R in

Each current flows when the circuit operates in synchronization with one clock signal. Therefore, the phase difference between each current is This can be changed by changing the timing of the signal edge.

For example, when the single-phase clock signal shown in Fig. 2 is used, the phase difference between the rising edge and the falling edge of the clock signal is changed from 1/2 to 1/3, so that the falling edge since the operation timing of the synchronizing circuits also changes, Figure 2 (b), to indicate such a current, the phase difference of the g _R and g _F even in response to a change in the clock signal, the 1/3 It will be changed to such a value.

Similarly, in the polyphase clock signal shown in FIG. 4, both the phase difference between the rising edge and the falling edge of the φ1 clock signal and the phase difference between the falling edge and the rising edge of the ø2 clock signal are calculated. by such a value that 1/3 is, the operation timing of the circuit of the second group also changes, that is change the value like 1/3 even phase difference of currents g _R and g _F Becomes

FIG. 6 is, g _R and g retardation R 0.2 50 _F, 0.375, 0.4 1 7,

The intensity coefficient for each harmonic when set to 0.500 is shown. In Fig. 6, the horizontal axis shows the harmonic order, and the vertical axis shows the noise intensity coefficient. As shown in FIG. 6, it is clear that the intensity coefficient of each harmonic noise differs for each phase. In FIG. 6, when R = 1/2, the intensity coefficient of odd-order harmonic noise such as the first, third, and fifth order is set to 0. However, in practice, as is clear from the above, there is no guarantee that g _R (t) and g _F (t) are equal, so odd-order harmonic noise does not always become zero.

7 to 9 are measured when the phase difference between the rising edge and the falling edge of the clock signal is changed in the semiconductor integrated circuit device MPC constituting the micro-computer shown in FIG. Characteristics of noise Here is an example. In this case, the semiconductor integrated circuit device MPC has the clock signal frequency f. Is a relatively high frequency, such as 2 OMHz. Note that the drawing does not show a frequency band of 30 MHz or less, which is twice the frequency of the clock signal or less. Fig. 7 shows a measurement example when the phase difference between the rising edge and the falling edge of the clock signal is 1/2, and Fig. 8 shows a measurement example when the phase difference is about 2/5 (42%). is there. FIG. 8 shows that the intensity of the third to fifth harmonic noise, which falls into the FM radio frequency band from 60 MHz to 100 MHz, is reduced by about 10 dB. FIG. 9 is a graph showing the intensity of the second to sixth harmonic noise when the phase difference between the rising edge and the falling edge of the clock signal is changed. It is clear from this graph that the noise intensity changes due to the phase difference for each harmonic.

 FIG. 10 shows an example of radiation of electromagnetic wave noise generated from a configuration in which semiconductor electronic components in which a semiconductor integrated circuit device MPC is sealed with a resin are mounted on a mounting substrate such as a print substrate.

 A wiring board 66 for mounting electronic components, such as a printed board, is not particularly limited. It is composed of a multilayer wiring board. This type of multilayer wiring board enables supply of power supply current to electronic components 63 including semiconductor integrated circuit devices operating at relatively high frequency under relatively low power supply impedance. An increase in the size of the substrate itself, an increase in the length of the signal wiring 65, and undesired electrical coupling between the signal wirings 65 are avoided as much as possible.

The semiconductor electronic component 63 is a resin package component in which a semiconductor substrate such as a silicon chip 64 constituting the semiconductor integrated circuit device MPC is sealed with a resin. And formed on the semiconductor substrate. The power supply wiring (Vcc, Gnd) connected to the circuit is connected to the power supply wiring 61 formed on the printed circuit board 66 and the like via the lead (pin) which is the connection terminal 62 of the semiconductor electronic component 63, It is supplied with power supply current. When the circuit formed on the semiconductor substrate of the semiconductor integrated circuit device operates, the current flowing through the power supply wiring is supplied from a power supply unit (not shown) coupled to the printed circuit board to the power supply wiring 61 on the printed circuit board and the semiconductor integrated circuit. It is supplied via connection terminals 62 of the circuit arrangement. Therefore, the electromagnetic wave noise generated by the current flowing through the power supply wiring 61 due to the operation of the circuit described above is generated not only by the power supply wiring (Vcc, Gnd) on the semiconductor substrate, but also by the connection terminal 62 and the power supply wiring 6 on the printed circuit board. It has the possibility of being radiated from one.

 FIG. 11 shows an example of electromagnetic wave noise generated from a data processing system using the semiconductor integrated circuit device MPC. In the drawings, two power supply terminals, Vcc and Gnd, are disclosed to avoid complication of the drawing, but in the semiconductor integrated circuit device MPC constituting the microcomputer 73, the power supply terminals are not shown. For example, a plurality of pairs of one power supply terminal Vcc and one reference potential side power supply terminal Gnd are set so that various circuits in the integrated circuit device perform desired operations. Even if such a plurality of power supply terminals are set, they are regarded as the power supply terminals of the present invention in terms of electromagnetic noise.

 Microprocessor 73, dryno IC 74-76, RAM7 1-7

Semiconductor integrated circuit devices such as 2 are connected to power supply wiring (V cc and Gnd), which operate in synchronization with the clock signal CK. As a result, electromagnetic noise is generated by the current flowing through the power supply wiring. In addition, a current also flows through the power supply wiring on the printed circuit board of the data processing system connected to these semiconductor integrated circuit devices in synchronization with a clock signal for operating the semiconductor integrated circuit device, and electromagnetic wave noise is generated. What happens You. The data processing system shown in FIG. 11 is provided with connection connectors A, B, and C for signal output, which are respectively coupled to dryno ICs 76, 75, and 74.

 Although not shown, the electronic system is provided with so-called noise countermeasure electronic components such as a bypass capacitor which is connected between power supply wires near a power supply terminal of the semiconductor integrated circuit device on a mounting board such as a printed board. Can be This minimizes noise on the power supply wiring on the mounting board. However, electronic components for noise suppression are effective in reducing the amount of noise, but they cannot reduce the amount of noise to zero. Therefore, the semiconductor integrated circuit device of the present invention becomes effective. Here, a specific circuit example of the evening adjustment circuit applied to the timing adjustment circuit TADJ in the semiconductor integrated circuit device MPC of FIG. 1 will be described.

The basic clock signal for evening adjustment is supplied from the clock pulse generator CPG in FIG. The clock pulse generation circuit CPG in FIG. 1 is not particularly limited, but a self-propelled oscillation circuit, a waveform shaping circuit composed of an inverter circuit receiving the output, and a waveform shaping circuit. And a frequency dividing circuit receiving the output. The oscillation frequency of the oscillation circuit in the circuit CPG is set relatively accurately by a ceramic oscillator or a crystal oscillator connected to an external terminal (not shown) of the semiconductor integrated circuit device MPC. The waveform shaping circuit forms an oscillation signal having a waveform suitable as a pulse signal based on the oscillation signal output from the oscillation circuit. The frequency divider divides the oscillation signal to generate a clock signal CK and a relatively low frequency peripheral circuit clock signal for the operation of the input / output ports IOP1 to IOP4 in FIG. Although not particularly limited, the clock signal CK and the clock signal (not shown) inverted in phase from the clock signal CK rise. The phase difference between the leading edge and the falling edge is set to substantially 1/2. Although there is no particular limitation, the evening adjustment circuit TADJ adjusts the timing of the clock signal CK of the clock signal CK supplied from the clock pulse generation circuit CPG and the clock signal inverted from the clock signal CK. It is configured as follows.

 FIG. 12 shows an example of a timing adjustment element circuit 100 constituting the timing adjustment circuit TADJ, and FIG. 13 shows an example of the output signal waveform. It should be noted that the evening adjustment circuit TADJ can be constituted by only the timing adjustment element circuit 100.

The circuit 100 shown in FIG. 12 has delay circuits d1 to d4, a NAND gate circuit Gl, NOR gate circuits G2 and G3, and an inverter circuit IV1 to IV3. The clock signal CK _dl obtained via the inverter circuit IV 1 is delayed by the delay circuit d 1 by d 1 at the rising edge, and the clock signal CK _{d 2} obtained via the inverter circuit IV ₂ d is the falling edge by the delay circuit d 2 is caused a delay of only d 2, the clock signal CK _{d 3} obtained through Lee members evening circuit IV 3 is the rising edge by the delay circuit d 3 and d 4 3. Delay the falling edge by d4, and make the phase difference between the rising edge and the falling edge different from 1/2. As a result, in a logic circuit block that operates in synchronization with the peak signal output from the evening adjustment circuit, the current g _R that flows when the circuit operates at the rising edge of the peak signal is output. The phase difference of the current g _F flowing by the operation of the circuit element at the falling edge of the clock signal can be changed from 1/2. At this time, the delay time of the delay circuit in the timing adjustment circuit is set in accordance with the frequency at which the semiconductor integrated circuit device MPC operates and the order of the harmonic noise corresponding to the frequency band in which the harmonic noise is to be reduced. By setting, it is possible to reduce electromagnetic noise generated in a specific frequency band. And have you to timing adjustment element circuit 1 0 0 shown in the first FIG. 2, but to generate a three clock signals of the clock signal CK _d i to CK _{d 3,} Ya number of generated click-locking signal The method of generating the delay time and the mouth signal can be changed.

FIG. 14 shows an example of a selection circuit (also referred to as a multiplexer) 101 for selecting one clock signal from a plurality of clock signals generated by the circuit of FIG. The multiplexer 101 shown in the figure includes select gate circuits G4 to G6 whose operations are controlled by select control signals S1 to S3. The multiplexer 1 0 1, of the first 2 clock signal CK _dl to clock signal CK _{d 3} generated by timing adjustment element circuit 1 00 shown in FIG, Akutibu a Jo of the selection control signals S 1 to S 3 The clock signal selected by the _active signal is output as CK _sei . Only one of the selection control signals S1 to S3 may be made active by a physical switch mechanism (not shown). Use of the configuration is attempted.

 FIG. 15 shows a first example of a selection signal forming circuit for forming the selection control signals S1 to S3. The selection signal forming circuit is capable of setting contents to be held in a programmable manner, and constitutes an example of a setting circuit for instructing a timing adjustment amount based on the held contents. The selection signal forming circuit shown in FIG. 15 has a specific address selected by the address bus ABS2 of the semiconductor integrated circuit device of FIG. 1, and the data from the data bus DBS2 of FIG. 1 in the address selection state. It consists of a 1-bit register RS1 to RS3.

Regis evening 1 3 1 to 133 A setting program such as a state setting program sets the state so that one of the outputs S1 to S3 is at the active level. FIG. 16 exemplifies a manner of selecting the clock signals CK _dl to CK _{d 3} with respect to the values of the selection control signals S 1 to S 3.

FIG. 17 shows a second example of the selection signal forming circuit. In the second example, as in the first example, there are one-bit registers R _{s dA} and R _{s dB} which are initialized by the address bus ABS 2 and the data bus DBS 2. The outputs S _dA and S _dB of the register are supplied to a 2-bit decoder composed of inverter circuits IV 4 and IV 5 and AND gate circuits G 7 to G 9 shown in FIG. The signals are converted into selection signals S1 to S3. Output S _dA of the first 9 FIG Regis evening, selected aspects of the clock signal CK _dl to CK _{d 3} for the values of signals S 1 to S 3 is obtained by decoding the S _{d B} are shown examples. In Fig. 19, the symbol 氺 means that the value in that column is ignored.

FIG. 20 shows another example of a timing adjustment circuit TAD J using a digital delay circuit. FIG. 21 shows an example of the output waveform of the timing adjustment circuit of FIG. In the second 0 view, the basic clock signal f _ck receiving, the basic clock signal f _{e k} by the frequency遁倍control has been eight times periodic clock signal f from the pulse generator CPG as described above. _The control oscillation circuit C scSC that generates _sc , the count value register CCR, and the basic clock signal f _ck rise to the initial state by the rise of the clock signal, and the eight-times-delayed clock signal f from the control oscillation circuit C 0 SC. It has a counter CNTR whose _sc is a count input and whose count is programmed by the register CCR. In timing adjusting circuit shown by this counter value registers evening period specified in C CR, it is a V _{hi gh} state, the clock signal f _ck 'which subsequently a V _{l QW} is generated from counter evening CNTR. In response, Clock signal: fc _k ', for example, if 3 has been specified by the count register evening C CR, the phase difference between the rising and falling edges of 3/8. Similarly, if 5 is specified, the phase difference will be 5/8, and if 2 is specified, a clock signal with a phase difference of 1/4 can be generated. Control oscillator circuit The designation of the multiplier value of the n-times cycle clock signal to be generated by the COSC and the value of the count register CCR is not particularly limited, but the semiconductor integrated circuit device MPC shown in FIG. If it is a micro-computer, use the control register controlled by the central processing unit CB 1 or specify the contents to be specified for the register in the storage circuit that can be referenced by the central processing unit CB 1. It may be set by doing.

FIG. 22 shows an example of a semiconductor integrated circuit device having an evening adjustment circuit TADJ. The semiconductor integrated circuit device shown in FIG. 22 generates the internal clock signal based on the clock signal CK input thereto by the clock pulse oscillation circuit CPG of FIG. 1, and generates the clock signal generated by the clock pulse oscillator. In the timing adjustment circuit TAD J, a clock signal Φ Κ 2, 3 is generated so that a predetermined phase difference is generated in the current flowing through the power supply wiring, and the central processing unit and the like constituting the semiconductor integrated circuit device are generated. It is supplied to logic circuit blocks 1 to 3. This configuration is applied to a semiconductor integrated circuit device operated by a single-phase clock signal shown in (a) of FIG. In _ck ': timing adjustment circuit TAD J clock signal ų 1 to ų 3 generated by the output of the evening Lee timing adjustment circuit of the selected clock signal CK _se or second 0 views by the first 4 Figure multiplexer is there. Also, with respect to the logic circuit blocks 1 to 3, the evening adjustment element circuit 100 of FIG. 12 itself constitutes an evening adjustment circuit TADJ, and outputs CK _{dl to} CK _{d 3} Supply May be used. Thus, the phase difference between the rising edge and the falling edge of the clock signal given to each logic circuit block can be made appropriate in consideration of the operation margin of each logic circuit block.

 The semiconductor integrated circuit device shown in FIG.

The internal clock signals 01 and 02 are generated in the clock pulse oscillation circuit CPG shown in Fig. 1 based on K, and these clock signals ø1 and 02 are respectively supplied by the timing adjustment circuits TAD J1 and TAD J2. It generates clock signals ø, 02 'that cause a predetermined phase difference in the current flowing through the wiring, and supplies the clock signals ø, 02' to logic circuit processes 1 and 2 such as a central processing unit constituting a semiconductor integrated circuit device. This configuration is applied to a semiconductor integrated circuit device operated by a multi-phase clock signal shown in (a-2) and (a-3) of FIG. The phase difference between the rising and falling edges of the clock signals ø1 'and 2' generated by the timing adjustment circuits TAD J1 and TAD J2 is determined by taking into account the operating margin of each logic circuit block 1 and 2. , Each can be appropriate.

 The semiconductor integrated circuit device shown in FIG. 24 does not have a clock pulse generation circuit CPG therein, and is configured so that the logic circuit blocks 1 and 2 operate based on a clock signal CK supplied from the outside. In this case, the input clock signal CK is generated by the timing adjustment circuit TADJ to generate a clock signal øI2 that causes a predetermined phase difference in the current flowing through the power supply wiring, and the semiconductor integrated circuit device is manufactured. It is supplied to the logic blocks 1 and 2 of the central processing unit, etc. to be configured. Thus, the present invention can be applied to a semiconductor integrated circuit device having no clock pulse generating circuit inside.

Figure 25 shows an example of a data processing system with a timing adjustment circuit. An example is shown. Based on the clock signal CK generated by the oscillator, the timing adjustment circuit generates a clock signal with 0, Φ2, and 03 set so that a predetermined phase difference occurs in the current flowing through the power supply wiring of the data processing system. Then, it is supplied to the semiconductor integrated circuit device. Although the semiconductor integrated circuit device is not particularly limited, it may have no oscillator therein and operate based on a supplied clock signal, or may have an oscillator. Good. As a result, even in a data processing system using a semiconductor integrated circuit device having no internal timing adjustment circuit TADJ, a rising edge and a falling edge of a clock signal supplied to the semiconductor integrated circuit device can be reduced. By changing the phase difference, it becomes possible to change the phase difference of the current flowing through the power supply wiring as a whole of the data processing system, thereby reducing the harmonic noise generated in a specific frequency band. Become.

In FIGS. 22 to 25, the phase difference between the rising edge and the falling edge of the clock signals 01, 02, 3, and 01, ø2 generated by the evening adjustment circuit is the same. May be different from each other. The phase difference between the rising edge and the falling edge of the clock signal can be made appropriate in consideration of the operation margin of the logic circuit block or the semiconductor integrated circuit device to which the clock signal is supplied. In addition, the mouth signal 1 to? It is also possible to adopt a configuration in which the rising edge and the falling edge of i3 or ø1 'to ø2' are different from each other. As a result, the current flowing in synchronization with the rising edge of the clock signal of the logic circuit blocks 1 to 3 and the current flowing in synchronization with the falling edge of the clock signal are temporally dispersed, that is, (b) in FIG. ) g _R and g _F are temporally dispersed illustrated in, and current intensity can Rukoto lowered. As a result, noise can be further reduced. Fig. 26 shows an example in which a data processing system having an evening adjustment circuit is used for equipment mounted on a vehicle. Some vehicles are equipped with AM / FM radio receivers, and some are equipped with TV receivers for vehicles. On the other hand, a data processing system using a microcomputer is installed to control the engine control, airbag, air conditioner, etc. of the car, and its operation clock signal frequency is, for example, 8 MHz to 20 MHz. z. These data processing systems are supplied with power from the battery of the vehicle, and are connected to the semiconductor integrated circuit device such as a micro computer used in the data processing system and the power cable connected to the battery. Then, a current flows in synchronization with the operation peak signal of the semiconductor integrated circuit device. As a result, the power cable operates like a monopole antenna due to the electromagnetic noise. Of the above electromagnetic noise, the harmonic noise corresponding to the AM / FM radio frequency band is received from the antenna of the car, and the radio reception sensitivity deteriorates. Similarly, the video noise and audio noise due to the harmonic noise generated in the TV frequency band Will occur. This kind of electromagnetic noise tends to be a particularly serious problem in vehicle-mounted electronic systems.

 In other words, in vehicles, the safety of the vehicle itself is given top priority, and noise including electromagnetic noise that may affect other electronic systems tends to be particularly severe. On the other hand, in-vehicle electronic systems usually have to be installed in a very limited space, such as inside the console panel of a car or in an engine room. For this reason, it is difficult to keep a plurality of electronic systems sufficiently electrically and physically separated from each other.

In addition, wireless communication devices such as on-board radio receivers are different from electronic systems that are fixedly installed in fixed buildings, etc. This is because the electric field strength of the electromagnetic wave changes remarkably greatly with movement, and it is desired that the influence of noise on communication electromagnetic waves with a very weak electric field strength can be eliminated.

 Therefore, by using the timing adjustment circuit in a semiconductor integrated circuit device such as a microcomputer for engine control or the like mounted on an automobile or in a data processing system using the semiconductor integrated circuit device, AM / FM Higher harmonic noise generated in the radio frequency band and TV frequency band can be particularly reduced.

 Although the invention made by the present inventor has been specifically described above, the present invention is not limited thereto, and can be variously modified without departing from the gist thereof. Semiconductor integrated circuit devices are not limited to logic LSIs called microprocessors and microcontrollers, but are equipped with digital signal processing processors, floating-point arithmetic processors, and other desired functions such as processors and DRAMs. The system LSI may be a system-on-chip system.

 In addition, the counter C NTR in the timing adjustment circuit T ADJ described with reference to FIG. 20 can be regarded as a shift register. Therefore, in the above timing adjustment circuit, a digital delay circuit which is operated by the output of the oscillation circuit and whose delay amount is set in accordance with the amount to be time-adjusted is connected to the output of the oscillation circuit. It can be considered that the shift register is constituted by a shift register configuration circuit which receives as a shift input and sets the number of shifts corresponding to the amount to be adjusted. Industrial applicability

The present invention is not limited to on-vehicle devices, Use with wireless communication devices, portable information devices such as mobile phones and PDAs, computer devices such as personal computers, medical devices, etc., which have low electromagnetic noise immunity or whose electromagnetic noise can have a significant effect. It can be widely applied to data processing devices and semiconductor integrated circuit devices.

Claims

The scope of the request. A circuit block that operates in synchronization with the clock signal,  A first power terminal;  A semiconductor integrated circuit device having a second power supply terminal,  The circuit block has a plurality of circuit groups that cause a current change between the first power supply terminal and the second power supply terminal,  A timing adjustment circuit that can change a phase difference between a current change caused by operating a first circuit group of the plurality of circuit groups and a current change caused by operating a second circuit group is provided. Semiconductor integrated circuit device having the same. The clock signal has a first edge at which the potential changes from a first potential to a second potential, and a second edge at which the potential changes from the second potential to the first potential. The second circuit group operates in synchronization with the second edge, and the timing adjustment circuit operates in synchronization with the first edge of the clock signal. 2. The semiconductor integrated circuit device according to claim 1, wherein the evening of the second edge is changed. 3. The semiconductor integrated circuit device according to claim 2, wherein said timing adjustment circuit further comprises a timing setting circuit for setting the timing of the first edge or the second edge of the clock signal. 4. The semiconductor integrated circuit device according to claim 3, further comprising a quick signal generation circuit that generates the quick signal. 5. The semiconductor integrated circuit device according to claim 4, wherein said circuit block, said timing adjustment circuit, and said cook signal generation circuit are formed on one semiconductor substrate. 6. The timing adjustment circuit includes a plurality of evening adjustment element circuits and a selection circuit provided between an input node and an output node to which a clock signal to be evening-adjusted is supplied. 2. The semiconductor integrated circuit device according to claim 1, wherein timing adjustment is performed by a combination of the timing adjustment element circuit and the selection circuit.  7. The plurality of timing adjustment element circuits include circuits having different timing characteristics from each other, and the selection circuit determines a circuit to be selected among the plurality of timing adjustment element circuits by the input node and the output node. 7. The semiconductor integrated circuit according to claim 6, wherein said semiconductor integrated circuit is selectively coupled between 8. Each of the above-mentioned evening adjustment element circuits is provided with a delay circuit, one input of which is provided with an input to be adjusted in timing, and the other input which is provided with the input to be adjusted in the evening through the delay circuit. 8. The semiconductor integrated circuit device according to claim 7, having a supplied gate circuit.  9. The timing adjustment circuit includes an oscillation circuit synchronized with an input clock signal, and a digital delay circuit which is operated by the output of the oscillation circuit and whose delay amount is set according to the amount to be adjusted. 2. The semiconductor integrated circuit according to claim 1, wherein an output whose timing is adjusted based on an output of said digital delay circuit is obtained. 10. The digital delay circuit according to claim 9, comprising a count circuit which receives an output of the oscillation circuit as a counter input, and a count number of which is set according to an amount to be adjusted in timing. The semiconductor integrated circuit device according to the item. 1 1. The digital delay circuit receives the output of the oscillation circuit as a shift input and sets the number of shifts corresponding to the amount to be adjusted in the evening. 10. The semiconductor integrated circuit device according to claim 9, wherein said semiconductor integrated circuit device comprises a shift register component circuit.  12. The semiconductor according to claim 1, wherein the timing adjustment circuit is provided with a setting circuit capable of setting a content to be held as a circuit operation and instructing a timing adjustment amount according to the held content. Integrated circuit 13. The semiconductor integrated circuit according to claim 12, wherein the semiconductor integrated circuit device has a configuration having a bus, and the setting circuit is configured to set contents to be held therein via the bus. apparatus. 14. The semiconductor integrated circuit device according to claim 13, wherein the semiconductor integrated circuit device constitutes a microcomputer, and the setting circuit is configured to set contents to be held therein via a bus of the microphone port computer. Semiconductor integrated circuit device.  15. The timing adjustment circuit according to claim 6, wherein the content to be held in the timing adjustment circuit can be set as a circuit operation, and the timing adjustment circuit includes a setting circuit for indicating a selection state of the selection circuit based on the held content. Semiconductor integrated circuit device.  16. The semiconductor integrated circuit device according to claim 12, wherein the semiconductor integrated circuit device has a bus, and the setting circuit sets contents to be held in the bus via the bus.  17. The semiconductor integrated circuit device constitutes a microcomputer, and the setting circuit sets contents to be stored in the microcomputer via a bus of the microcomputer. 7. The semiconductor integrated circuit device according to item 6. 1 8. The timing adjustment circuit can set the contents to be held as the circuit operation, and the digital delay circuit depends on the held contents. A setting circuit for instructing the amount of delay of the digital signal 10. The semiconductor integrated circuit device according to item 9. 19. The semiconductor integrated circuit according to claim 18, wherein the semiconductor integrated circuit device has a bus, and the setting circuit sets contents to be held in the bus via the bus. apparatus.  20. The semiconductor integrated circuit device constitutes a microcomputer, and the setting circuit sets contents to be held in the microcomputer via a bus of the microcomputer. 10. The semiconductor integrated circuit device according to item 9. 21. The semiconductor integrated circuit device has a bus, the digital delay circuit receives the output of the oscillation circuit as a count input, and the number of counts is set according to the amount to be adjusted. The circuit consists of  19. The semiconductor integrated circuit according to claim 18, wherein the setting circuit holds the contents that define the number of counts of the count circuit, and sets the contents to be held therein via the bus. apparatus. 22. The semiconductor integrated circuit device according to claim 21, wherein the setting circuit is configured to set contents to be held in the microcomputer via the microcomputer bus. The semiconductor integrated circuit device as described in the above.  23. The semiconductor integrated circuit device has a bus, and the digital delay circuit receives the output of the oscillation circuit as a shift input and sets the number of shifts in accordance with the amount to be adjusted. The shift register consists of The setting circuit holds the contents that define the number of shifts in the shift register configuration circuit, and sets the contents to be held in the shift register via the bus. 19. The semiconductor integrated circuit device according to claim 18, wherein: 4. The semiconductor integrated circuit device constitutes a microcomputer, and the setting circuit is configured to set contents to be held in the microphone opening via a bus of the microphone opening and closing. 2. The semiconductor integrated circuit device according to claim 1.  5. Multiple circuit blocks operating in synchronization with multiple internal clock signals;  A first power terminal;  A second power terminal;  A clock signal generation circuit that generates the plurality of internal clock signals; and  The plurality of circuit blocks have a plurality of circuit groups that cause a current change between the first power supply terminal and the second power supply terminal,  A phase difference between a current change caused by the operation of the first circuit group of the plurality of circuit groups and a current change caused by the operation of the second circuit group of the plurality of circuit groups is changed. A semiconductor integrated circuit device having a plurality of timing adjustment circuits capable of enabling each of the plurality of internal clock signals to have a first edge that changes from a first potential to a second potential and a second edge from a second potential to a first potential; It has a second edge that changes potential,  The plurality of circuit groups operate in synchronization with a first edge or a second edge of the plurality of internal clock signals, The plurality of timing adjustment circuits may change a phase difference of the current change by changing a timing of a first edge or a second edge of the plurality of internal clock signals. 2 Clause 5 Semiconductor integrated circuit device. 27. The semiconductor integrated circuit device according to claim 26, wherein said timing adjustment circuit is provided for each of said plurality of internal clock signals. 28. The semiconductor integrated circuit according to claim 27, wherein said timing adjustment circuit further comprises a timing setting circuit for setting said timing. 29. The timing setting circuit sets the timing of the first edge or the second edge of the plurality of internal clock signals for each of the plurality of internal clock signals supplied to the plurality of circuit blocks. 29. The semiconductor integrated circuit device according to claim 28, wherein:  30. The first power supply terminal, the second power supply terminal, the plurality of circuit blocks, the quick signal generation circuit, and the plurality of timing adjustment circuits are one semiconductor 30. The semiconductor integrated circuit device according to claim 29, formed on a substrate. 3 1. A semiconductor signal processing device that operates in synchronization with a clock signal,  Having first and second power supply wirings for supplying a power supply current to the semiconductor signal processing device,  The semiconductor signal processing device,  A circuit block that operates in synchronization with a click signal,  A first power supply terminal connected to the first power supply wiring,  A second power terminal connected to the second power wiring,  The circuit block has a plurality of circuit groups that cause a current change between the first power supply terminal and the second power supply terminal, The phase difference between the current change caused by the operation of the first circuit group of the plurality of circuit groups and the current change caused by the operation of the second circuit group of the plurality of circuit groups is changed. And a timing adjustment circuit that can be adjusted. 32.The clock signal has a first edge that changes potential from a first potential to a second potential, and a second edge that changes potential from a second potential to the first potential, and the plurality of circuit groups include: Operates in synchronization with the first edge or the second edge of the above-mentioned click signal,  The evening adjustment circuit can change the phase difference of the current change by changing the evening of the first edge or the second edge of the clock signal that operates in synchronization with the circuit group. Claims The data processing system according to claim 31. 33. The data processing system according to claim 32, wherein said timing adjustment circuit further comprises a timing setting circuit for setting the timing of the first edge or the second edge of the clock signal. 34. The data processing system according to claim 33, wherein said clock signal is externally supplied to said semiconductor signal processing device. 35. The data processing system according to claim 33, further comprising a quick signal generation circuit for generating the quick signal in the semiconductor signal processing device.  36. An internal clock signal generation circuit for generating a plurality of internal clock signals from the clock signal,  A plurality of the circuit blocks operating in synchronization with the plurality of internal clock signals;  The data processing system according to claim 35, further comprising the timing adjustment circuit for each of the plurality of internal clock signals. 37. For each of the plurality of internal clock signals supplied to the plurality of circuit blocks, the time for changing the timing of the first edge or the second edge of the internal clock signal is different. 3 Item 6 Data processing system.  38. The data processing system according to claim 37, wherein said data processing system is for use in a vehicle.  39. A plurality of semiconductor signal processing devices operating in synchronization with a clock signal, a first power supply,  A second power supply, comprising: a first power supply and the second power supply when one of the plurality of semiconductor signal processing devices operates. A data adjustment circuit having a timing adjustment circuit that can change a phase difference between a current change generated between power supplies and a current change caused by the operation of another semiconductor signal processing device. —Evening treatment system.  40.The above-mentioned signal has a first edge that changes potential from the first potential to the second potential and a second edge that changes potential from the second potential to the first potential. The device operates in synchronization with the first or second edge of the clock signal,  The timing adjustment circuit can set a phase difference of a current change by changing a timing of a first edge or a second edge of a clock signal operated by the semiconductor signal processing device in synchronization. A data processing system according to claim 39. 41. The data processing system according to claim 40, wherein said timing adjustment circuit further comprises a timing setting circuit for setting the timing of the first edge or the second edge of the clock signal. 42. The data processing system according to claim 41, wherein the clock signal is supplied from outside. 43. The data processing system according to claim 41, further comprising a clock signal generation circuit that internally generates the clock signal. 4. an internal clock signal generation circuit for generating a plurality of internal clock signals from the above-mentioned clock signal;  A plurality of semiconductor signal processing devices operating in synchronization with the plurality of internal clock signals;  The data processing system according to claim 43, further comprising the timing adjustment circuit for each of the plurality of internal clock signals.  5. The plurality of internal clock signals supplied to the plurality of semiconductor signal processing devices, wherein the time for changing the timing of the first edge or the second edge of the internal clock signal is different. Data processing system according to the item.  6. The data processing system described above is for use in a vehicle. The data processing system according to item 5.  7. The operation is performed in synchronization with the clock signal that repeats the first transition and the second transition. The power supply current at the timing corresponding to the first transition and the power supply current at the timing corresponding to the second transition A semiconductor integrated circuit device that consumes  The period from the time when the first transition occurs to the time when the second transition occurs and the period from the time when the second transition occurs to the time when the first transition occurs again are relatively changed. Equipped with a timing adjustment circuit, The timing adjustment circuit corresponds to a harmonic component of a predetermined order with respect to the clock signal out of the power supply current noise caused by the power supply current corresponding to the first transition and the power supply current corresponding to the second transition. The level of the harmonic noise is lower than the level of the harmonic noise corresponding to the harmonic component of the order with respect to the clock signal when there is no timing adjustment by the timing adjustment circuit. Semiconductor integrated circuit device.