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WO2000051177A1 - Dispositif a circuit integre avec dielectrique a entrefer - Google Patents

Dispositif a circuit integre avec dielectrique a entrefer Download PDF

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Publication number
WO2000051177A1
WO2000051177A1 PCT/US1999/022125 US9922125W WO0051177A1 WO 2000051177 A1 WO2000051177 A1 WO 2000051177A1 US 9922125 W US9922125 W US 9922125W WO 0051177 A1 WO0051177 A1 WO 0051177A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
forming
conductive lines
openings
conductive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US1999/022125
Other languages
English (en)
Inventor
Thomas Werner
John G. Pellerin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of WO2000051177A1 publication Critical patent/WO2000051177A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention is generally directed to the field of semiconductor processing, and, more particularly, to the field of conductive interconnections on integrated circuit devices
  • Efforts to reduce the hne-to-hne capacitance have included, among other things, the formation of various types of dielectric materials having a relatively low dielectric constant between the conductive lines
  • a process layer 10 comprised of a dielectric material having a relatively low dielectric constant, e g , hydrogen silsesquioxane (HSQ)
  • HSQ hydrogen silsesquioxane
  • another dielectric layer 12 comprised of, for example, silicon dioxide
  • Openings or vias 21 may then be formed in the process layer 12 usmg traditional photolithography and etching methods
  • Conductive plugs (not shown) are thereafter formed in the vias 21 to establish electrical connections with the conductive lines 16
  • the separate dielectric layers 10 12 could be replaced with a single dielectric layer that extends from the substrate
  • the present invention is directed to a method and integrated circuit device for solving or at least reducing the effects of some or all of the aforementioned problems DISCLOSURE OF INVENTION
  • the present invention is directed to an integrated circuit device having a plurality of conductive interconnections and a method for making same
  • the method comprises forming a plurality of conductive lines and forming a first layer of material between adjacent conductive lines
  • the method further comprises forming a second layer of material above the first layer of material and forming a plurality of openings in the second layer of material
  • the method further comprises removing a portion of the first layer of material through the openmgs to define an air gap positioned between the adjacent conductive lines
  • Figure 1 is an illustrative prior art integrated circuit device having a plurality of conductive lines formed thereon
  • Figure 2 is one illustrative embodiment of an integrated circuit device partially formed in accordance with the present invention
  • Figure 3 is the device depicted in Figure 2 after the dielectric material has been removed from between the adjacent conductive lines
  • Figure 4 is a plan view of a portion of the device shown in Figure 3
  • Figure 5 is the device depicted in Figure 3 after yet another non-conformal or non-gap-filling dielectric layer has been positioned above the device shown in Figure 3
  • FIG. 6 is another illustrative embodiment of an integrated circuit device partially formed in accordance with the present invention.
  • Figure 7 is the device depicted in Figure 6 after the dielectric material has been removed from between adjacent conductive lines
  • Figure 8 is a plan view of a portion of the device shown in Figure 7
  • Figure 9 is a cross-sectional view of the device depicted in Figure 8 after a conformal process layer has been formed thereabove and
  • Figure 10 is a cross-sectional view of the device depicted in Figure 9 after illustrative conductive plugs have been formed above the illustrative conductive lines
  • the present invention is directed to the formation of an air gap between conductive interconnections on an integrated circuit device
  • Two illustrative embodiments of the invention are disclosed herein The first embodiment is disclosed in Figures 2-5, and the second embodiment is disclosed m Figures 6-10
  • the present method is applicable to a variety of technologies, e g , NMOS, PMOS, CMOS, etc , and is readily applicable to a variety of devices including, but not limited to, logic devices, memory devices, etc
  • a plurality of conductive lines 16 may be formed above a semiconducting substrate
  • the conductive lines 16 may also have an optional anti-reflective coating 18 formed thereabove
  • the conductive lines 16 and anti-reflective coatings 18 are formed using known techniques for formation of such layers, e g , chemical vapor deposition, sputtering, electrochemical deposition, physical vapor deposition, etc , and are patterned using traditional photolithography techniques
  • the particular methods used to form the conductive lines 16 and, if used, anti-reflective coatings 18 should not be considered a limitation of the present invention
  • the conductive lines 16 may be comprised of a variety of conductive materials, such as a metal or metal alloy, e g , aluminum aluminum alloys, titanium, copper, copper alloys, tungsten, cobalt or titanium sihcide, polysi con, etc
  • the thickness of the process layer (not shown) used to form the conductive lines 16 may be va ⁇ ed as a matter of design choice
  • the conductive lines 16 are comprised of aluminum alloy having a height above a surface 25 of a substrate 26 that ranges from approximately 4000-20,000 A
  • the anti-reflective coating 18 may be comprised of a variety of materials, such as titanium nitride (TiN)
  • the anti-reflective coating 18 is comprised of titanium nit ⁇ de having a thickness ranging from approximately 0 02-0 2mm (200-2000 A)
  • the process layer 20 may be comprised of a variety of materials, e g , an organic-based dielectric material (such as those described above) or a silicon-based dielectric material (such as those described above)
  • the process layer 20 may be formed by a variety of techniques known for forming such layers, e g , chemical vapor deposition, sputtering, spin-on, etc , and the thickness of the process layer 20 may be varied as a matter of design choice
  • the particular method used to form the process layer 20 should not be considered to be a limitation of the present invention
  • the process layer 20 is comprised of a deposited layer of silicon dioxide having a thickness ranging from approximately 0 5-0 8mm (5000-8000 A)
  • the materials of construction for both the process layer 24 and the process layer 20 are selected such that the process layer 24 may be selectively removed with respect to the process layer 20
  • This selective removal may be accomplished by, for example, dry (plasma or reactive ion) etching, oxidation, photon degradation, thermal degradation, thermally oxidative degradation, or chemical dissolution (wet etching)
  • dry etching e g a plasma oxygen etch
  • the materials of construction for the process layer 24 and the process layer 20 must be selectively etchable with respect to one another
  • the next operation involves the formation of a plurality of openings 22 in the process layer 20
  • the openings 22 are used to provide access for removal of portions of the process layer 24 lying underneath the process layer 20 between the conductive lines 16
  • This process results in the formation of an air gap 28 (see Figure 3) between the conductive lines 16
  • the size, configuration, and spacing of the openings 22 are matters of design choice that may vary dependmg upon a particular application
  • the openmgs 22 may be of any shape, e g circular, square, elliptical, oval, rectangular, etc
  • the number, size and spacing of the openings 22 may be varied as a matter of design choice or as required by a particular application
  • the number, size and spacing mav depend, in part, on the material used to make the process layer 24.
  • the openmgs 22 are generally circular in cross-section and have a diameter of approximately 0 5mm (5000 A)
  • the openings 22 are located approximately equidistant between edges 35 of the conductive lines 16 and have a center-to-center spacing along the conductive lines 16 of approximately 0 5mm (5000 A) apart, although other configurations and patterns may also be used
  • a layer of thermally-labile polymers approximately 04-2 0mm (4000-20 000 A) thick
  • the process layer 20 is comprised of a layer of silicon dioxide approximately 0 4-2 0mm (4000-20.000 A) thick
  • the spacmg between the edges 35 of the conductive lines 16 is approximately 0 7- l mm (7000-10 000 A)
  • the openmgs 22 are generally circular in cross-section and have a diameter of approximately 0 5mm (5000 A)
  • the openings 22 are located approximately equidistant between edges 35 of the conductive lines 16 and have a center-to-center spacing along the conductive lines 16 of approximately
  • the first process layer 24 may be comprised of, for example, thermally-labile polymers, polynorbornene, polyimide, polyparaxylylene, polytetrafluoroethylene, or like mate ⁇ als
  • the process layer 20 may be comprised of, for example, silicon dioxide, fluo ⁇ nated silicon oxide, silicon nitride, silicon oxynit ⁇ de, or like mate ⁇ als
  • the device is heated to a temperature ranging from approximately 250-500°C for approximately 1-60 minutes using a tube furnace or a rapid thermal anneal process
  • this selective removal may be accomplished by any method, including etching, oxidation, thermal degradation, chemical dissolution (wet chemistry), etc
  • portions of the process layer 20 may be also removed, e g , the openings 22 may become slightly larger, but, in general, the process layer 20 will not be removed during the removal of the portions of the process layer 24 under the openings
  • the present method allows the formation of air gaps 28 between adjacent conductive lines 16
  • the removal of the process layer 24 may not be complete, / e , some portions of the process layer 24 may remain under the process layer 20
  • portions of the process layer 24 may remain adjacent the conductive lines 16 and or substrate 26 Nevertheless, the formation of the air gaps 28, even if a portion of the process layer 24 is not removed, provides a lower hne-to-hne capacitance between adjacent conductive lines 16
  • the present invention has been disclosed in the context of the formation of air gaps 28 between a plurality of conductive lines 16 formed above a semiconducting substrate 26, those skilled m the art will recognize that the present invention may be used on conductive lines 16 formed well above the surface of the substrate
  • vias can be patterned, etched and filled with metal to make electrical contact to conductive lines 1 16 Subsequent conductive lines can be formed on top of the vias (repetitive layer as shown in Figure 5)
  • FIG. 6-10 Another illustrative embodiment of the present invention is depicted in Figures 6-10 As shown in Figure 6, a plurality of conductive lines 1 16 may be formed above a semiconductmg substrate 126 Although not required, if desired, the conductive lines 1 16 may also have an optional anti-reflective coating 1 18 formed thereabove
  • the conductive lines 1 16 and anti-reflective coatings 118 are formed using known techniques for formation of such layers, e g , chemical vapor deposition, sputte ⁇ ng, physical vapor deposition, electrochemical deposition, etc , and are patterned using traditional photolithography techniques
  • the particular methods used to form the conductive lines 1 16 and, if used, anti-reflective coatings 1 18 should not be considered a limitation of the present invention
  • the conductive lines 1 16 may be comprised of a variety of conductive mate ⁇ als, such as a metal or metal alloy, e g , aluminum, aluminum alloys, titanium, copper, copper alloys, tungsten, cobalt or titanium silicide, polysihcon, etc
  • the thickness of the process layer (not shown) used to form the conductive lines 1 16 may be vaned as a matter of design choice
  • the conductive lines 116 are comprised of aluminum alloy havmg a height above the surface 125 of the substrate 126 that ranges from approximately 0 4- 2 0mm (4000-20 000 A)
  • the anti-reflective coating 1 18 may be comprised of a variety of materials such as titanium nitride (TiN)
  • the anti-reflective coating 1 18 is comprised of titanium nitride havmg a thickness ranging from approximately 0 02-0 2mm (200-2000 A)
  • a process layer 124 is formed above the substrate 126
  • the process layer 124 may be comprised of a variety of materials, such as those set forth above for the process layer 24
  • the process layer 124 is a sacrificial layer, / e , at least portions of the process layer 124 will be removed during further processing, as described below
  • the process layer 124 it may be, if desired, subjected to a chemical mechanical polishing or plasma etch-back process to plana ⁇ ze a surface 127
  • the process layer 124 could be comprised of a material and/or formed by a technique that results in a self- plana ⁇ zed layer 124
  • a second process layer 120 is formed above the process layer 124
  • the process layer 120 may be comprised of a variety of materials, such as those set forth above for the process layer 20
  • the process layer 120 may be formed by a variety of techniques known for forming such layers, e g , chemical vapor deposition, sputtering, spin-on, etc , and the thickness of the process layer 120 may be varied as a matter of design choice
  • the particular method used to form the process layer 120 should not be considered to be a limitation of the present invention
  • the process layer 120 is comprised of a deposited layer of silicon dioxide having a thickness ranging from approximately 0 5-0 8mm (5000-8000 A)
  • the materials of construction for both the process layer 124 and the process layer 120 are selected such that the process layer 124 may be selectively removed with respect to the process layer 120
  • This selective removal may be accomplished by, for example, dry etching, oxidation, thermal degradation, or chemical dissolution (wet etching)
  • an etching process e , a plasma oxygen etch
  • the materials of construction for the process layer 124 and the process layer 120 must be selectively etchable with respect to one another
  • the next operation involves the formation of a plurality of openings 122 in the process layer 120 above the conductive lines 1 16
  • the gaps 133 extending beyond the conductive lines 1 16 are used to provide access for removal of portions of the process layer 124 lying underneath the process layer 120 between the conductive lines 116 This process results in the formation of an air gap 128 (see Figure 7) between the conductive lines 1 16
  • the size of the gap 133 may be varied as a matter of design
  • the openings 122 may not extend entirely across or along the conductive lines 1 16, ; e , the openings 122 could be positioned such that only one gap 133 is formed adjacent the conductive line 1 16 by that particular opening 122
  • Other configurations of the openmgs 122 and their positioning relative to the conductive lines 1 16 are, of course, possible
  • the size, configuration, and spacing of the openings 122 are matters of design choice that may vary depending upon a particular application
  • the openings 122 may be of any shape, e g , circular, square elliptical, rectangular, etc
  • the number size and spacing of the openings 122 may be varied as a matter of design choice or as required by a particular application
  • the number, size and spacing may depend, in part, on the material used to make the process layer 124, the amount of the process layer 124 to be removed through each of the openings 122, the edge-to-edge spacing between adjacent conductive lines 1 16, and the particular removal process used In one illustrative embodiment, where selective
  • this selective removal may be accomplished by any method, including etching, oxidation, thermal degradation, chemical dissolution (wet chemistry), etc
  • portions of the process layer 120 may be also removed e g , the openings 122 may become slightly larger, but, in general, the process layer 120 will not be removed during the removal of the portions of the process layer 124
  • the present method allows the formation of air gaps 128 between adjacent conductive lines 16
  • the removal of the process layer 124 may not be complete, t e , some portions of the process layer 124 may remain under the process layer 120
  • portions of the process layer 124 may remain adjacent the conductive lines 1 16 and/or substrate 126 Nevertheless, the formation of the air gaps 128, even if a portion of the process layer 124 is not removed, provides a lower hne-to-hne capacitance between adjacent conductive lines 1 16
  • the present invention has been disclosed m the context of the formation of air gaps 128 between a plurality of conductive lines 1 16 formed above a semiconducting substrate 126, those skilled in the art will recognize that the present invention may be used on conductive lines 1 16
  • the next process involves the removal of a portion of the process layer 132 positioned above the anti-reflective coating 118 This process may be accomplished by a variety of techniques, such as an anisotropic etching of the process layer 132 which results in the structure of the process layer 132 shown in Figure
  • conductive plugs 134 may be formed above the anti-reflective coating 118 between the remaining portions of the process layer 132. as shown in Figure 9
  • the conductive plugs 134 may be formed by a variety of well-known techniques, and may be comprised of a variety of conductive mate ⁇ als, such as copper and copper alloys, aluminum and aluminum alloys, tungsten, titanium, tantalum, or other like materials, as well as alloys of such materials.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

Cette invention se rapporte à un dispositif à circuit intégré comportant un entrefer (28) formé entre des lignes conductrices adjacentes (16), ainsi qu'à un procédé de fabrication de ce dispositif, lequel consiste à former plusieurs lignes conductrices (16) et une première couche (24) d'un matériau entre ces lignes conductrices (16), puis à former une seconde couche (20) d'un matériau au-dessus de ces lignes conductrices (16) et à percer plusieurs ouvertures (22) dans cette seconde couche (20) de matériau. Ce procédé consiste en outre à retirer des parties de cette première couche (24) de matériau par les ouvertures (22) ménagées dans la seconde couche (20). Ce dispositif à circuit intégré se compose d'au moins deux lignes conductrices (16) séparées par un entrefer (28) et d'une couche de matériau disposée au-dessus des lignes conductrices (16) et de l'entrefer (28).
PCT/US1999/022125 1999-02-26 1999-09-24 Dispositif a circuit integre avec dielectrique a entrefer Ceased WO2000051177A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US25979999A 1999-02-26 1999-02-26
US09/259,799 1999-02-26

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WO2000051177A1 true WO2000051177A1 (fr) 2000-08-31

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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10142201A1 (de) * 2001-08-29 2003-04-10 Infineon Technologies Ag Mittels einer gefrierenden Prozessflüssigkeit erzeugte Hohlräume mit Submikrometer-Strukturen in einer Halbleitereinrichtung
DE10142223A1 (de) * 2001-08-29 2003-04-10 Infineon Technologies Ag Mittels Polymerisation erzeugte Hohlräume mit Submikrometer-Abmessungen in einer Halbleitereinrichtung
DE10142224A1 (de) * 2001-08-29 2003-04-24 Infineon Technologies Ag Mittels eines Quellvorgangs erzeugte Hohlräume mit Submikrometer-Abmessungen in einer Halbleitereinrichtung
WO2004007349A1 (fr) * 2001-07-10 2004-01-22 Honeywell International Inc. Utilisation d'un dielectrique organique comme couche sacrificielle
US6693355B1 (en) 2003-05-27 2004-02-17 Motorola, Inc. Method of manufacturing a semiconductor device with an air gap formed using a photosensitive material
DE10238024A1 (de) * 2002-08-20 2004-03-11 Infineon Technologies Ag Mikroelektronischer Prozess und Aufbau
WO2004041972A3 (fr) * 2002-11-02 2004-07-15 Honeywell Int Inc Materiaux de formation de couche de gaz

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0812016A1 (fr) * 1996-06-04 1997-12-10 Harris Corporation Dispositif semi-conducteur avec une structure de pont d'air et procédé de fabrication
EP0872887A2 (fr) * 1997-04-18 1998-10-21 NEC Corporation Structure d'interconnexions à plusiers niveaux ayant un espace d'air entre les interconnexions

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0812016A1 (fr) * 1996-06-04 1997-12-10 Harris Corporation Dispositif semi-conducteur avec une structure de pont d'air et procédé de fabrication
EP0872887A2 (fr) * 1997-04-18 1998-10-21 NEC Corporation Structure d'interconnexions à plusiers niveaux ayant un espace d'air entre les interconnexions

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
KOHL P A ET AL: "Air-gaps for electrical interconnections", ELECTROCHEMICAL AND SOLID-STATE LETTERS, JULY 1998, ELECTROCHEM. SOC, USA, vol. 1, no. 1, pages 49 - 51, XP002128468, ISSN: 1099-0062 *

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004007349A1 (fr) * 2001-07-10 2004-01-22 Honeywell International Inc. Utilisation d'un dielectrique organique comme couche sacrificielle
US6645850B2 (en) 2001-08-29 2003-11-11 Infineon Technologies Ag Semiconductor device having cavities with submicrometer dimensions generated by a swelling process
US6734095B2 (en) 2001-08-29 2004-05-11 Infineon Technologies Ag Method for producing cavities with submicrometer patterns in a semiconductor device using a freezing process liquid
DE10142223C2 (de) * 2001-08-29 2003-10-16 Infineon Technologies Ag Verfahren zum Erzeugen von Hohlräumen mit Submikrometer-Abmessungen in einer Halbleitereinrichtung mittels Polymerisation
DE10142201C2 (de) * 2001-08-29 2003-10-16 Infineon Technologies Ag Verfahren zur Erzeugung von Hohlräumen mit Submikrometer-Strukturen in einer Halbleitereinrichtung mittels einer gefrierenden Prozessflüssigkeit
DE10142224C2 (de) * 2001-08-29 2003-11-06 Infineon Technologies Ag Verfahren zum Erzeugen von Hohlräumen mit Submikrometer-Abmessungen in einer Halbleitereinrichtung mittels eines Quellvorgangs
DE10142201A1 (de) * 2001-08-29 2003-04-10 Infineon Technologies Ag Mittels einer gefrierenden Prozessflüssigkeit erzeugte Hohlräume mit Submikrometer-Strukturen in einer Halbleitereinrichtung
DE10142223A1 (de) * 2001-08-29 2003-04-10 Infineon Technologies Ag Mittels Polymerisation erzeugte Hohlräume mit Submikrometer-Abmessungen in einer Halbleitereinrichtung
DE10142224A1 (de) * 2001-08-29 2003-04-24 Infineon Technologies Ag Mittels eines Quellvorgangs erzeugte Hohlräume mit Submikrometer-Abmessungen in einer Halbleitereinrichtung
US6696315B2 (en) 2001-08-29 2004-02-24 Infineon Technologies Ag Semiconductor device configuration with cavities of submicrometer dimensions and method of fabricating structured cavities
DE10238024A1 (de) * 2002-08-20 2004-03-11 Infineon Technologies Ag Mikroelektronischer Prozess und Aufbau
US7022582B2 (en) 2002-08-20 2006-04-04 Infineon Technologies Ag Microelectronic process and structure
DE10238024B4 (de) * 2002-08-20 2007-03-08 Infineon Technologies Ag Verfahren zur Integration von Luft als Dielektrikum in Halbleitervorrichtungen
WO2004041972A3 (fr) * 2002-11-02 2004-07-15 Honeywell Int Inc Materiaux de formation de couche de gaz
US6693355B1 (en) 2003-05-27 2004-02-17 Motorola, Inc. Method of manufacturing a semiconductor device with an air gap formed using a photosensitive material

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