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WO2000049648A1 - Condensateur multicouche en ceramique a couches minces - Google Patents

Condensateur multicouche en ceramique a couches minces Download PDF

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Publication number
WO2000049648A1
WO2000049648A1 PCT/DE1999/000441 DE9900441W WO0049648A1 WO 2000049648 A1 WO2000049648 A1 WO 2000049648A1 DE 9900441 W DE9900441 W DE 9900441W WO 0049648 A1 WO0049648 A1 WO 0049648A1
Authority
WO
WIPO (PCT)
Prior art keywords
oxide
thin layer
ceramic
ceramic thin
multilayer capacitor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/DE1999/000441
Other languages
German (de)
English (en)
Inventor
Rainer Waser
Michael Grossmann
Susanne Hoffmann
Roland Slowak
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Forschungszentrum Juelich GmbH
Original Assignee
Forschungszentrum Juelich GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Forschungszentrum Juelich GmbH filed Critical Forschungszentrum Juelich GmbH
Priority to PCT/DE1999/000441 priority Critical patent/WO2000049648A1/fr
Priority to JP2000600298A priority patent/JP2003533007A/ja
Priority to EP99915481A priority patent/EP1161766A1/fr
Publication of WO2000049648A1 publication Critical patent/WO2000049648A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/692—Electrodes
    • H10D1/711—Electrodes having non-planar surfaces, e.g. formed by texturisation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/682—Capacitors having no potential barriers having dielectrics comprising perovskite structures

Definitions

  • the present invention relates to a ceramic multilayer capacitor with a plurality of plate capacitors and a method for producing a ceramic multilayer capacitor with a plurality of plate capacitors.
  • Such multilayer ceramic capacitors have been generally known as discrete components for many years. These capacitors have a ceramic composite produced by lamination. The metallic inner electrode layers are alternately connected to head contacts in such a way that with n inner electrode layers n-1 plate capacitors are formed which are connected in parallel. In this way, extraordinarily high capacitance densities are achieved due to a large number of individual capacitors, a small electrode spacing (the so-called dielectric layer thickness, standard today: 10 ⁇ m) and dielectric ceramics with large dielectric constants, which, depending on the type of capacitor and with poor temperature characteristics 10,000 can lie.
  • dielectric layer thickness standard today: 10 ⁇ m
  • Such multilayer capacitors are manufactured using powdered dispersions, which are drawn out to form green foils, and by screen printing techniques for the metal electrodes.
  • the manufacturing temperatures for the standard types are above 1000 ° C.
  • the smallest dimensions for multilayer capacitors are approximately 0.5 x 1.0 x 0.5 mm 3 (type: 0402).
  • capacitors are integrated in thick-film or thin-film technology on substrates or (exclusively) in thin-film technology on semiconductor circuits.
  • the known discrete ceramic multilayer capacitors have the following disadvantages:
  • the dielectric layer thickness cannot easily be reduced to less than 1 ⁇ m with the aid of powder-based ceramic techniques.
  • an MMgO single crystal is used as the substrate.
  • this material is not used as a substrate in semiconductor technology and is therefore unsuitable for the integration of the capacitors.
  • the object of the present invention is therefore to create discrete ceramic multilayer capacitors or a method for their production, which can be produced using thin-layer methods of semiconductor technology and can be used for integrated circuits.
  • inventive features according to claims 1 and 11 make it possible to create ceramic multilayer capacitors, the minimum size of which is limited only by the resolution of the technology used. Are there Arrangements possible that allow optimal integration.
  • La shows a schematic representation of a first production step for a ceramic multilayer capacitor according to the invention
  • Fig. Lb is a schematic representation of a second manufacturing step subsequent to Fig. La;
  • FIG. 1 c shows a schematic illustration of a third production step following FIG. 1 b;
  • FIG. 1d shows a schematic representation of a fourth production step following FIG. 1c;
  • Fig. Le is a schematic representation of a ceramic two-layer capacitor.
  • the ceramic multilayer capacitor 1 comprises a plurality, two in the present embodiment, of plate capacitors 3, 5, which are connected to different connection contacts (not shown).
  • Each plate capacitor 3, 5 comprises an oxide ceramic thin layer 7.
  • This thin layer is made using various technologies, such as, for. B. CSD, MOCVD, PVD, etc., deposited on a bottom electrode 9 (bottom electrode).
  • the bottom electrode in turn is applied to a platinized silicon wafer 11.
  • a second electrically conductive layer or later electrode 13 is formed over a predetermined area of the first oxide ceramic thin layer 7.
  • a second oxide ceramic thin layer 15 is applied over the predetermined area of the second electrode 13 and over the first oxide ceramic thin layer 7.
  • a continuous contact hole 17 is formed through the first and second oxide ceramic thin layers 7, 15.
  • a third electrode 19 is formed in the contact hole 17 and makes contact with the bottom electrode 9.
  • the contact hole 17 is formed by an etching process, whereby both wet and dry etching processes can be used.
  • the thin layers 7, 15 and the electrically conductive layers 9, 13, 19 could be obtained by wet chemical deposition with photosensitive precursors and by means of photolithography. This has the advantage that a ceramic layer is only formed where the gel layer remains after development.
  • the Si wafer serving as the substrate can be etched away from the rear. Discrete multilayer capacitors are then obtained, the dielectric layer thicknesses of which are far below that of conventional types.
  • Each oxide ceramic thin layer 7, 15 consists of a material selected from the group consisting of titanate, zirconate, niobate and tantalate.
  • the temperature response of the capacitance can be controlled by using different compositions for the dielectric thin films 7, 15 within a multilayer thin film capacitor 1.
  • Each electrode and / or base electrode 9, 13, 19 consists of a material selected from the group of metals and metallic-conductive non-metals, such as. B. oxides, nitrides, silicides, carbides, etc.
  • Electrodes 9, 13, 19 are preferably made using shadow masks or liftoff technology.
  • the electrically conductive layers are deposited using an electrode mask B or D.
  • the contact hole is etched using an etching mask A.
  • FIG. 2 shows a top view of a structured multilayer thin-film capacitor.
  • etching holes are etched through the ceramic layers, the ceramic layers outside the capacitor surfaces remain as dead dimensions left. This can be useful for sealing purposes.
  • FIG. 3 shows a laminated ceramic multilayer capacitor of the prior art as an example.

Landscapes

  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Abstract

Condensateur multicouche en céramique qui comporte une pluralité de condensateurs sous forme de plaques, dotés d'une couche mince en céramique à base d'oxyde, lesdits condensateurs étant chacun déposés sur une électrode.
PCT/DE1999/000441 1999-02-17 1999-02-17 Condensateur multicouche en ceramique a couches minces Ceased WO2000049648A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
PCT/DE1999/000441 WO2000049648A1 (fr) 1999-02-17 1999-02-17 Condensateur multicouche en ceramique a couches minces
JP2000600298A JP2003533007A (ja) 1999-02-17 1999-02-17 セラミック多層薄層コンデンサ
EP99915481A EP1161766A1 (fr) 1999-02-17 1999-02-17 Condensateur multicouche en ceramique a couches minces

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/DE1999/000441 WO2000049648A1 (fr) 1999-02-17 1999-02-17 Condensateur multicouche en ceramique a couches minces

Publications (1)

Publication Number Publication Date
WO2000049648A1 true WO2000049648A1 (fr) 2000-08-24

Family

ID=6918808

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE1999/000441 Ceased WO2000049648A1 (fr) 1999-02-17 1999-02-17 Condensateur multicouche en ceramique a couches minces

Country Status (3)

Country Link
EP (1) EP1161766A1 (fr)
JP (1) JP2003533007A (fr)
WO (1) WO2000049648A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7224280B2 (en) 2002-12-31 2007-05-29 Avery Dennison Corporation RFID device and method of forming
US7307527B2 (en) 2004-07-01 2007-12-11 Avery Dennison Corporation RFID device preparation system and method
US7842152B2 (en) 2005-08-22 2010-11-30 Avery Dennison Corporation Method of making RFID devices

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4857642B2 (ja) * 2005-07-29 2012-01-18 Ｔｄｋ株式会社 薄膜電子部品の製造方法
JP4957835B2 (ja) * 2010-05-31 2012-06-20 Ｔｄｋ株式会社 薄膜電子部品及び薄膜電子部品の製造方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5135883A (en) * 1990-06-29 1992-08-04 Samsung Electronics Co., Ltd. Process for producing a stacked capacitor of a dram cell
US5206788A (en) * 1991-12-12 1993-04-27 Ramtron Corporation Series ferroelectric capacitor structure for monolithic integrated circuits and method

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5135883A (en) * 1990-06-29 1992-08-04 Samsung Electronics Co., Ltd. Process for producing a stacked capacitor of a dram cell
US5206788A (en) * 1991-12-12 1993-04-27 Ramtron Corporation Series ferroelectric capacitor structure for monolithic integrated circuits and method

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
GROSSMANN M ET AL: "A novel integrated thin film capacitor realized by a multilayer ceramic-electrode sandwich structure", ELECTROCERAMICS VI '98, MONTREUX, SWITZERLAND, 24-27 AUG. 1998, vol. 19, no. 6-7, Journal of the European Ceramic Society, 1999, Elsevier, UK, pages 1413 - 1415, XP004166104, ISSN: 0955-2219 *
HENNINGS D ET AL: "ADVANCED DIELECTRICS: BULK CERAMICS AND THIN FILMS**", ADVANCED MATERIALS, vol. 3, no. 7/08, 1 July 1991 (1991-07-01), pages 334 - 340, XP000329352, ISSN: 0935-9648 *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7224280B2 (en) 2002-12-31 2007-05-29 Avery Dennison Corporation RFID device and method of forming
US8072333B2 (en) 2002-12-31 2011-12-06 Avery Dennison Corporation RFID device and method of forming
US7307527B2 (en) 2004-07-01 2007-12-11 Avery Dennison Corporation RFID device preparation system and method
US7842152B2 (en) 2005-08-22 2010-11-30 Avery Dennison Corporation Method of making RFID devices

Also Published As

Publication number Publication date
JP2003533007A (ja) 2003-11-05
EP1161766A1 (fr) 2001-12-12

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