WO1999035820A1 - Imaging device with load transfer on a connecting element - Google Patents

Abstract

The invention concerns an imaging device comprising: a plurality of imaging elements (10); at least one storage element (20); at least one signal output circuit (40); and at least a connecting element (2) for load transfer with floating potential, constituting a capacitor, and connecting between them an assembly of imaging elements, at least one storage element and at least one signal output circuit.

Description

 DEVICE FOR TAKING PICTURES WITH TRANSFER OF CHARGES ON

A CONNECTION ELEMENT

Technical Field The invention relates to a charge transfer method and a micro-electronic picture taking device comprising picture taking elements, for example, in the form of bars juxtaposed or arranged in the form of a matrix, and implementing the charge transfer method.

The invention relates in particular to shooting devices operating in a so-called TDI mode ("Time Delay and Integration", in which when a point of an image passes successively in front of shooting elements different, the electric charges generated during the detection of this image point are memorized and summed in the same memory.

The invention finds applications for shooting in the visible spectral domain and in the infrared domain.

As a particular example, the invention can be implemented in the production of panoramic monitoring systems or in the production of infrared spectroscopy systems.

State of the art

Figures 1 to 4 attached make it possible to specify the operation of a shooting line operating according to the TDI mode mentioned above. The expression line is understood to mean a set of shooting elements, generally arranged in line, and a set of memory elements intended for receive, memorize and summon the signals produced by the shooting elements.

In Figures 1 to 4 is shown, for reasons of simplification, a matrix of only three shooting elements and three memory elements also called "memories". The shooting elements and the memories are respectively identified by the references Pi, P ₂ , P ₃ , Mi, M ₂ and M ₃ . They are respectively connected by electrical connections L shown schematically. An image moving in front of the shooting elements at a speed V, called the scanning speed, is represented by four points, called image points, identified with the references Xi, X ₂ , X ₃ and X „. In FIG. 1, corresponding to an initial instant t ₀ , the first image point Xi is in front of the first image pickup element Pi and y generates a signal in the form of an electric charge C _x . This signal is stored in the memory Mi. The term flight time denotes the time increment Δt that an image point takes to go from one shooting element to the next shooting element. The displacement of the image in front of the shooting elements and the flight time Δt are linked by the scanning speed V mentioned previously and an acquisition cycle for a shooting element is adjusted to be synchronous with the time of flight.

Thus, at time ti, such that tι = t ₀ + Δt the image point Xi has moved, as shown in FIG. 2, in front of the second shooting element P ₂ . Similarly, a second image point X ₂ is now in front of the first shooting element Pi- The first point 99/35820 _

image Xi generates in the first shooting element a signal in the form of a charge Ci, summed in the memory Mi. The second image point X ₂ generates a signal corresponding to a load denoted C ₂ and is stored in the memory M ₂ .

At time t ₂ , such as t ₂ = t ₀ + 2Δt, as shown in FIG. 3, a third image point X ₃ is opposite the first shooting element. The first, second and third image points Xi, X ₂ , X ₃ respectively in front of the third, second and first shooting elements P ₃ , P _{2 /} Pi respectively generate signals in the form of charges Ci, C ₂ , C ₃ . These signals are stored and summed respectively in the memories Mi, M ₂ and M ₃ . At the end of time t ₂ the first image point Xi leaves the field of the detection matrix. All the charges (3xCι) which have been supplied by the shooting elements, relating to this image point, and stored in the first memory Mi, are directed to an output S of the shooting line.

The other image points are processed according to the same reading cycle with an offset depending on the flight time.

FIG. 4 corresponds to a time t ₃ such that t ₃ = t ₀ + 3Δt. A fourth image point, denoted X _4, enters the field of the detection matrix and is located in front of the first shooting element Pi. A detection signal in the form of a charge C ₄ corresponding to this image point is memorized in the first memory Mi whose content has been reset to zero by the transfer to the output S of the charges corresponding to the first image point Xi. 99/35820,

More generally, for a line comprising a number n of shooting elements

(detectors), the charges d generated by an image point X_ which passes successively in front of the shooting elements are summed in the same memory M_ taken from among n memories.

The improvement of the shooting devices has led to a reduction in the pitch of the elementary detectors of the detection matrices and, consequently, in a reduction in the pitch of the electronic means for reading each shooting element.

The space below each shooting element is generally used to house the electronic interface means. Thus, the means and for storing the electrical signals produced by the detectors are deported outside the detection zone and are therefore separated from the detection matrix.

From there arises the problem of transferring the information or signals produced by the elementary detectors to the means of memorizing and exploiting these signals.

Various methods are known for transferring the electrical signals supplied by the shooting elements to the storage means.

In known structures of the CCD (Charge Coupled Device) type, the electrical signal from the shooting element, coded by charges, is transmitted to storage areas by a successive transfer of electrical charges from sites. so-called transmitters to so-called receiver sites. 99/35820 r-

Thus, the transmission of the signal requires a succession of transmitting sites and adjacent receiving sites between each shooting element and each associated memory. This requirement constitutes a topological constraint in producing circuits for CCD devices.

In order to overcome this constraint, connections by metallic connection elements in the form of conductive tracks are also envisaged.

In devices using metal connections between the imaging elements and the storage areas, the electrical signal provided by the imaging elements, which is in the form of an electrical charge, is coded before being transmitted. The signals undergo a charge / voltage or charge / current conversion so that they can be transmitted over the metal connection to the storage areas. In this case again, the need to use electronic charge / voltage or charge / current conversion circuits constitutes a constraint in the production of miniaturized devices.

By way of illustrative known shooting devices, it may be ^"refer to the material (1), (2) and (3) whose references are given at the end of this description.

SUMMARY OF THE INVENTION The aim of the present invention is to propose a shooting device which does not present the difficulties mentioned above. 99/35820,

In particular, the object of the invention is to propose a device which does not require a succession of transmitter sites and charge receiver sites for transferring the detection signals from the shooting elements to the storage elements.

Another object of the invention is to provide a device that does not require conversion circuits for the transfer of detection signals. Another object of the invention is to propose a shooting device usable in the visible and infrared fields, using a reduced number of components.

Finally, an aim is to propose such a device capable of being produced with strong integration of the components.

To achieve these goals, the subject of the invention is more precisely a device for taking pictures comprising: a plurality of picture-taking elements,

- at least one storage element, and

- at least one signal output circuit.

In accordance with the invention, the device further comprises at least one charge transfer connection element, with floating potential, constituting a capacitor, and connecting together, at least one shooting element, a set of elements of storage and at least one signal output circuit. The connection element can be produced, for example, in the form of a metal track or of polycrystalline silicon, forming a bus line. 99/35820 -

Thanks to the invention, the charges which encode the optical signal detected in the shooting elements are transferred to the storage elements by means of a direct charge transfer which takes place via the metallic connection elements.

Thus, the device of the invention has, like the CCD type structures, the advantage of not requiring any conversion of the signals.

In addition, the device of the invention is free from the topological constraints specific to CCD structures, mentioned above.

According to a particular aspect of the invention, the shooting elements may include a generator capable of delivering an electric current in response to the reception of photons, a capacitor for integrating said electric current and a transistor connecting said capacitor to the connection element.

In the case of a device intended to operate in the visible spectrum, the imaging elements may include depletion MOS structures. These structures then constitute both the current generator and the integration capacitor. In particular, - the capacitor plates are formed by the channel and the grid of the MOS structure.

For applications in the infrared field, it is possible to perform a thermal type or bolometric type detection. The photoelectric current generator of the photographic elements can comprise photodiodes or photoconductive. It can also include variable resistances with temperature or capacitors generating 99/35820 _Q

electrical charges as a function of temperature, in the case of pyroelectric detectors.

A device according to the invention, intended to operate with numerous shooting elements, arranged in a matrix, may comprise a plurality of metallic connection elements in the form of bus lines, each connection element connecting a plurality of shooting elements, a plurality of storage elements and an associated signal output circuit.

The signal output circuits are connected for example to a multiplexer circuit for processing these signals and forming, for example, an image. According to a particular embodiment of the signal output circuits, these can each include a sample-and-hold circuit comprising a capacitor for receiving signals in the form of electrical charges, coming from all the storage elements connected to the same connection element, and a follower transistor stage adapted to measure and output the potential of the receiving capacitor. Signal output circuits may also include an anti-glare system. According to another ^" particular aspect of the invention, the device of the invention may further comprise for each connection element a so-called initialization circuit, connected to said connection element. The initialization circuit makes it possible to prepare the state charge of the connection element prior to each charge transfer and thus facilitate the charge transfer. It comprises, for example, 99/35820 _Q

a capacitor and a transistor, the transistor being able to be activated during an initialization cycle to transfer an electrical charge from the initialization capacitor to the connection element. The invention also relates to a method for transferring an electrical charge from a first capacitor to a second capacitor, by means of an electrical connection element with floating potential, constituting a third capacitor, and connected to the second capacitor by a field effect transistor, in which:

an initialization load is applied to the electrical connection element to fix an electrical initialization potential of the connection element at a value substantially equal to a threshold voltage of the field effect transistor, and greater than a charge potential of the second capacitor and then

- the first capacitor, brought to a potential greater than the initialization potential, is connected to the connection element to cause a flow of charges from the first capacitor to the connection element and from the connection element to the second capacitor .

This method can be implemented by a device as described ^" above in particular for a charge transfer between the shooting elements and the storage elements, that is to say between the storage elements and the output circuit.

Other characteristics and advantages of the present invention will emerge more clearly from the description which follows, with reference to the figures of the appended drawings. This description is given purely by way of non-limiting illustration. 99/35820

Brief description of the figures

- Figures 1 to 4, already described, are partial and simplified schematic representations illustrating an operating principle of known shooting devices.

- Figure 5 is a simplified schematic representation of a particular embodiment of a shooting line of a device according to the invention.

- Figures 6 and 7 are simplified schematic representations illustrating particular embodiments of the shooting elements of the device of the invention. - Figure 8 is a simplified overall schematic representation of a shooting device according to the invention.

FIGS. 9A to 9F represent in the form of timing diagrams of the signals controlling the operation of the device of FIG. 5.

- Figure 10 shows a connection element according to the invention and indicates its operation, in the form of load diagrams.

- Figure 11 shows, in the form of load diagrams, the steps of an initialization cycle of a connection element according to one invention.

- Figure 12 shows in the form of charge diagrams the steps of a charge transfer cycle, according to the invention.

- Figure 13 indicates, in the form of diagrams, control signals of the device of one invention. - Figure 14 shows schematically and simplified charge transfer sequences in a shooting device according to one invention.

Detailed description of methods of implementing the invention

Figure 5 shows a line of view 1 of a device according to the invention. The shooting line comprises a plurality of shooting elements 10 capable of transforming a light signal into a signal in the form of an electric charge. Among these shooting elements only one is shown in detail in the figure. The line of view in FIG. 1 further comprises a plurality of storage elements 20, only one of which is shown in detail. The number of memory elements preferably corresponds to the number of shooting elements. Line 1 also includes a circuit 30, called the initialization circuit, and a signal output circuit 40 allowing the reading of the storage elements.

The signal output circuit 40 is connected to a line multiplexer device 50 which is not shown in detail in this figure and the operation of which is known per se. The multiplexer receives signals from a set of shooting lines and makes it possible to manage these signals, for example, for the formation of an image. The picture-taking elements, the memory elements, the initialization circuit and the signal output circuit mentioned above are connected together by a floating potential connection element. 9/35820 ₂

which is, in the embodiment described, in the form of a bus line 2.

The shooting elements 10 each comprise a field effect transistor 12, one channel terminal of which, for example the source, is connected to the bus line 2 and of which another channel terminal, for example the drain, is connected to an electro-optical sensor and to a first armature of an accumulation capacitor 16. The electro-optical sensor is shown diagrammatically by a current generator 14 delivering a current, denoted I _ph , which results from a conversion of the photons received into an electric current . The charges of the current generated by the current generator 14 are directed and accumulated in the accumulation capacitor 16.

The second armature of the accumulation capacitor 16 is connected to an external control line receiving a signal denoted F _ci which is used to control the charge transfer. The gate of the transistor 12 is addressed by a control line receiving a signal F _a ι which makes it possible to control the reading of the accumulation capacitor 16, that is to say the transfer of the charges accumulated in this transistor to an element of memorization. Figures 6 and 7 show two particular embodiments of the shooting elements. For reasons of simplification, the parts of this figure identical or similar to those of FIG. 5, bear the same references. In the shooting elements of FIGS. 6 and 7, the components are produced according to a technology of the MOS (Metal-Oxide-Semiconductor) type. 99/35820 - -

In the case of FIG. 6, the current generator 14 and the accumulation capacitor are produced by an MOS structure, the silicon of which under the grid is put into a deep depletion regime. The depleted volume acts as a generator of photon conversion current and the inversion channel which forms acts as an accumulation capacitor 16.

In the case of FIG. 6, the shooting element comprises the MOS structure described above and a switch formed by the field effect transistor 12, also of the MOS type. These components can be implanted in a silicon substrate with a pitch of less than 10 μm. The shooting element of FIG. 6 is particularly suitable for the production of a shooting device operating in the visible spectrum.

For a shooting in the infrared domain, an embodiment of the shooting element according to FIG. 7 can be retained.

In the case of FIG. 7, we find the field effect transistor 12 forming a switch, an accumulation capacitor 16 formed by an MOS structure, but also a ^" detection element 14 associated with the MOS structure (by hybridization). An impedance matching transistor 15 connects the detection element 14 to the accumulation capacitor 16. This transistor is controlled by a control line receiving a signal denoted F _in j.

Incidentally, the signal F _inj and the impedance matching transistor 15 also make it possible to 99/35820 ₁₄

control the integration time of the current supplied by the detection element 14.

The detection element 14 here constitutes the current generator capable of delivering an electric current corresponding to the conversion of light energy. The detection element is made of a semiconductor material other than silicon, such as, for example, CdHgTe or InSb. Indeed, a silicon detector is incapable of detecting photons whose energy is lower than the forbidden band of silicon, that is to say a wavelength of 1 μm.

In FIG. 7, the detection element 14 is shown diagrammatically by a diode. The detection element 14 can, however, be produced by another type of detector, such as photoconductors, for example.

Returning to FIG. 5, it can be seen that each storage element 20 comprises an addressing transistor 22, for example of the field effect type, one channel terminal of which is connected to the bus line 2 and the other of which channel terminal can be selectively connected, either to a first armature of a memory capacitor 26, or to a source of bus reset voltage denoted Vi. The selective connection of the addressing transistor 22 to the memory capacitor or to the voltage Vi is ensured by switches 27e and 27i respectively.

The switches 27e and 27i are controlled by signals Fe and Fi. During a read or write operation, the switch 27e is closed to connect the addressing transistor 22 to the memory capacitor 26. The switch 27i is then open. During an initialization operation, the switch 27i is closed to connect the addressing transistor 22 to the 99/35820 ₁₅

initialization voltage V_ and the switch 27e is open.

It should be specified that all the switches visible in FIG. 5 can be produced either by MOS transistors (MOS or CMOS technology) or by bipolar transistors

(BICMOS technology).

The gate of the addressing transistor 22 is connected to a line making it possible to apply to the transistor a control signal denoted F _mera .

The bus line initialization circuit 30 essentially comprises an initialization transistor 32, one channel terminal of which is connected to the bus line 2. The other channel terminal of the initialization transistor 32 is connected to a first armature of a capacitor 36, called initialization, and to a voltage source denoted V _rz , by means of a controlled switch 37.

The second armature of the capacitor 36 is connected to a line receiving a voltage signal F _cr and the switch 37 is connected to a line receiving a control signal F _xz .

Finally, the transistor - initialization 32 has a gate connected to a line for applying a control signal F _aι .

In the present description, for reasons of simplification, the control lines and the control signals applied to these lines are designated by the same references. The signal output circuit 40 includes a sample-and-hold circuit having a write transistor 42. A first channel terminal, for example the source, of the write transistor 42 is 99/35820 - -

connected to bus line 2. The second channel terminal is connected to a first armature of an output capacitor 46, to a follower stage 48, and to a voltage source denoted V _eb2 by means of a switch controllable 47. The switch 47 is controlled by a signal F _ebz to reset the state of charge of the capacitor 46.

The follower stage 48, built around a field effect transistor, delivers, in the form of a voltage, a read signal from the shooting line to multiplexer means 50 and image processing means. These means are known per se and are not described in detail here.

The signal output circuit 40 further includes an anti-glare circuit. This circuit includes an anti-glare transistor 43, one channel terminal of which is connected to the bus line 2 and the other channel terminal of which is connected to an anti-glare potential V _ae . The gate of transistor 43 is polarized by a signal F _ae . Thus, when the voltage of the bus line increases excessively, the excess charges are directed towards the potential V _ae .

FIG. 8 is an overview of a shooting device comprising a plurality of parallel shooting lines, of the type described above.

Each shooting line 1 comprises a bus line 2 connected to a multiplexer circuit 50 by a signal output circuit 40. There is a shooting area identified with the reference 3. In this area are arranged the elements of shot 10 of each line. These elements are juxtaposed according to an orthogonal network of 99/35820 _{± η}

matrix type. In such a network, the shooting elements are arranged in rows and columns of shooting elements.

After the shooting area 3, there is a memory area 4 grouping together the storage elements 20.

Reference 5 designates a set of control circuits. The control circuits are connected to the recording and storage elements, as well as to the initialization or signal output circuits, by electrical connections 6. These connections, shown diagrammatically, make it possible in particular to deliver the signals of control of the field effect transistors and switches mentioned above.

It can be noted that all the signals of the shooting elements arranged in the same column are acquired simultaneously.

By way of illustration, FIG. 9 schematically indicates the form of the main control signals.

The reference Δt in FIG. 9 indicates the flight time.

During each flight time, the currents of the shooting elements are integrated, and summed for each image point. When a picture point leaves the detection matrix, the memory element in which the charges corresponding to the detection currents generated by this picture point are stored, must be read and sampled. During the signal transfer phase (charges) the anti-dazzle function is inhibited. 99/35820 -, o

The shooting operating cycle is broken down into two stages: an integration time Ti of the photonic current I _ph of the _recording elements, and a summation and output time denoted T _c . During the integration time, all of the control signals are at rest. During the summation and output time T _c , the shooting elements and the memory elements are addressed to transfer the charges integrated in the shooting elements to the memory elements.

During time T _c, the output circuit is also addressed to read and output a signal corresponding to the charges accumulated in a storage element associated with an image point which leaves a line of view.

For devices that can be used in infrared, the integration time must be much less than the flight time. This time is adjustable by controlling the gate of the impedance matching transistor 15, visible in FIG. 7, which receives the signal F _inj .

Part A of FIG. 9 indicates the control signal F _ae applied to the anti-glare transistor 43, visible in FIG. 5. The signal F _ae makes it possible to polarize this transistor at the limit of the conduction state so as to be able to ^" drain towards the potential V _ae any excess charge which could be injected on the bus line 2 by" overflow "of an integration capacitor 16, following an excess of illumination, for example. Part B of the FIG. 9 indicates the signal F _ai applied to transistor 12 of a shooting element 10. 99/35820 ₁₉

Part C of FIG. 9 indicates the signal F _m em applied to transistor 22 of a summation storage element 20.

Part D of FIG. 9 indicates the signal F _ae applied to the read transistor 42 of the means 40 for reading and outputting the signal.

Part E of FIG. 8 indicates commands for addressing the reading or writing elements of the shooting elements 10, of the storage elements 20, of the initialization circuit 30 or of the output circuit 40.

Part F of FIG. 9 indicates the control of the current generator (transistor 14 of FIG. 6) or of the impedance matching transistor 15, visible in FIG. 7. The shooting is carried out during the high level of the signal F _ιn] .

Before setting out more precisely all of the control signals of the device, it is advisable to examine each of the stages of a charge transfer cycle via a floating potential connection element ( bus line) . This cycle includes an initialization phase and a transfer phase. It is illustrated in FIG. 10 which shows in the form of a diagram the state of charge of the connection element.

The connection element, that is to say the bus line 2 in the example described, is shown diagrammatically in part A of FIG. 10. The bus line is connected to a capacitor denoted C by the through a field effect transistor. The capacitor C represents for example the memory capacitor of a storage element. The source of the field effect transistor is connected to the bus line, and its drain to the capacitor C.

On the time scale specific to shooting the metallic connection (bus line) is in quasi static equilibrium; it is equipotential. In the use that is made of it, the potential of the bus line is "floating", that is to say that the line is isolated from any potential reference. It constitutes a capacitor, denoted C _bus . in relation to its environment. Under these conditions any charge which is injected into it varies its potential, denoted V _bus .

In a MOS transistor in saturation mode the voltage on the source, denoted V _s , is controlled by the gate voltage denoted V _g , and is independent of the drain voltage. The source voltage constitutes with respect to the bus line a potential barrier which is of the order of V _g -V _th , V _th being the threshold voltage of the transistor. Before the transfer of a load, the channel of the MOS transistor thus isolates the source and the drain.

The transfer of an electric charge is illustrated by parts B, C and 'D of Figure 10.

Part A of Figure 10 corresponds to a state of equilibrium. It is assumed that the capacitor C has a zero initial charge. It is also assumed that the bus line 2 has been initialized at a voltage V _bus equal to the source voltage V _s (V _bus = V _s ). The source voltage V _s of the transistor constitutes a potential barrier which prevents any circulation of current. The current passing through the transistor is zero. The load of bus line 2 is noted Q _b u _S. Part C of Figure 10 corresponds to a charge injection. A signal load, noted Q _s , in excess with respect to the equilibrium state, is emitted on the bus line and modifies the voltage V _bU3 . The voltage V _bus applied to the source of the MOS transistor makes it conductive and causes a current I _DS to the capacitor C. The current I _D s is in the form of a transient pulse of duration shorter than the μs. Part D of Figure 10 corresponds to a return to balance. The voltage of the bus line V _bus becomes again equal to the source voltage V _s . The current I _DS in the transistor is canceled. The signal charge Q _s injected on the bus line has been fully transferred into the capacitor C connected to the drain of the transistor.

It appears that the initial equilibrium condition V _bus = V _s is important to ensure a transfer of the signal charge under good conditions.

Mismatches between the bus line and the imaging elements or the memory elements can impair the transfer of charges.

Indeed, any initial imbalance between the voltage of the bus line and the source voltage of the transistor penalizes the transfer of charges. The imbalance is further amplified when there is a significant relationship between the electrical capacity of the bus C _bus and the capacity C to which the charges are to be transferred.

Voltage imbalances can have different causes. In particular, the gate voltage signal V _g is supplied by generators of voltage, piloted by a clock, which are distinct for the various elements of shooting and memory. Thus, the voltage V _g can vary from one shooting or memory element to another. In addition, the active level of the gate voltage application signal may be affected by noise.

Furthermore, the threshold voltage V _ch itself changes from one transistor to another. This disparity in values induces a so-called spatial noise, which is all the more important when the capacity of the bus line C _bus is much greater than the integration capacity C to which the load is to be transferred.

Finally, the threshold voltage V _th is also marred by a so-called temporal noise, the spectral density of which increases towards the low frequencies. Electronic components, and in particular MOS transistors, in fact exhibit so-called low frequency noise, which corresponds to a random temporal variation in intrinsic electrical behavior. This temporal variation is all the more important as the period considered for the observation of the behavior of the component is long. For the quality of the transfer, which is defined here in terms of noise, it is advantageous to adapt the initial voltage of the bus to each addressing transistor. This adaptation preferably takes place as soon as possible before the load transfer.

A bus line initialization phase is illustrated in FIG. 11. More precisely, FIG. 11 illustrates an initialization of the bus line carried out for the subsequent transfer of a signal load to a particular storage element. Such initialization can be performed individually for each memory element addressed.

In FIG. 11, there have been shown successive stages of the initialization of a bus line 2 to which are connected, on the one hand, a capacitor 36 and a field effect transistor 32 of an initialization circuit and, on the other hand, a memory capacitor 26 and an addressing transistor 22 of a storage element. FIG. 11 is accompanied by diagrams indicating the state of charge and voltage of the capacitors and of the bus line.

The capacitor 36 of the initialization circuit has an armature connected to the bus line 2 via the field effect transistor 32. The second armature is connected to a variable potential F _cr . The transistor is driven by a signal F _ai .

Furthermore, an armature of the capacitor 26 of the storage element is connected to the bus line 2 by the field effect transistor 22. The second armature of the capacitor 26 is connected to a variable potential F _cm .

Part A of FIG. 11 represents the state of the line before initialization. References Q ₃₆ , Qbus and Q ₂₆ respectively indicate the charges accumulated in the capacitor of the initialization circuit, the capacitor formed by the bus line and the capacitor of the storage element.

The signals F _cr and F _mer - are such that the transistors 32 and 22 are blocked. Part B of FIG. 11 represents the state of the line during a step of preparing an initialization transfer. The signals F _cr and F _mem applied to the gates of the transistors 32 and 22 are adapted to the transfer of the initialization charge. It can be noted, moreover, that the field effect transistor 22 is in the same state as the state in which it is used during the transfer of a signal charge, this aspect is discussed later, with reference to the figure. 12.

Part C of FIG. 11 indicates the start of a transfer of initialization charge Q ₃₆ from the capacitor 36 of the initialization circuit. The transfer of the initialization charge takes place by a current, denoted Ii, which passes through the addressing transistor 22 to be directed towards the potential V_.

It should be noted that, during this transfer, the memory capacitor 26 is disconnected from the addressing transistor 22. Thus, the charge Q ₂ β stored in this capacitor is not affected by the transfer of the initialization charge . During the transfer of the initialization charge, the capacitor C _bus formed by the bus line 2 absorbs a charge Qi, and makes it possible to establish the bus line at an optimal potential for the subsequent transfer of a signal charge to through the addressing transistor 22. Referring to FIG. 5, the step of transferring the initialization charge takes place while the signals F _e and F_ applied to the switches 27e and 27i are such that the switch 27e connecting the addressing transistor 22 of the storage element to the memory capacitor 26 is open and the switch 27i connecting the transistor 22 to the potential V_ is closed. On this subject, it can be noted that the surface potential of the switch 27i does not influence the voltage of the bus line, since it is isolated from it by the channel of the addressing transistor 22. Part D of the figure 11 illustrates the state of the bus line at the end of the transfer of the first charge Qi. It is observed that the capacitor 36 of the initialization circuit is discharged and that the potential of the bus line 2 is equal to the source potential V _s of the addressing transistor.

Part E of FIG. 11 corresponds to a last step during which the capacitor 36 of the initialization circuit is isolated from the bus line by blocking of the transistor 32 of the initialization circuit. The capacitor 36 can then be recharged with a new charge denoted Q ₃₆ A

Furthermore, and still referring to the general diagram of FIG. 5, the signals F _e and Fi of the switches 27e and 27i of the storage element are switched so as to isolate the addressing transistor 22 from the potential Vi and for connect it to the memory capacitor 26.

The switch 27e connecting the addressing transistor 22 to the memory capacitor 26 is closed and the switch 27i is open.

The signal F _mem applied to the gate of the addressing transistor 22 of the storage element remains unchanged.

Thus any charge now emitted on the bus by a shooting element is transferred directly into the memory capacitor 26 of the addressed memory element. The bus voltage, and its state of charge is indeed optimized for the transfer of a signal charge to this storage element.

The bus line initialization can preferably be carried out on the order of a microsecond or even less before the transfer of a signal load. The adaptation of the bus line can thus take into account precisely the temporal noise affecting the threshold voltage of the addressing transistor. More precisely, when the transfer of the signal charge takes place at approximately 1 μs, after the initialization cycle the noises whose correlation time is greater than this duration (noises of frequency less than a few kilohertz) are eliminated. In addition, since the initialization is carried out each time with the addressing transistor of the storage element to which a signal load must be directed, the adaptation of the bus line also makes it possible to take spatial noise into account. fixed, due in particular to the dispersions of characteristics of all the addressing transistors.

FIG. 12 illustrates in chronological order the stages of a cycle of transfer of a signal charge on the bus line between a shooting element and a storage element with respect to which the potential of the bus line has been adapted during the initialization cycle described above.

FIG. 12 shows a bus line 2 to which are connected, on the one hand, an accumulation capacitor 16 of a shooting element, and on the other hand a memory capacitor 26 of a memory element selected. The storage and storage capacitors 16 and 26 are respectively connected to the bus line 2 by means of a field effect transistor 12 and by means of an addressing transistor 22, also of the field effect type. Furthermore, variable potentials (F _ci and

F _cm ) are respectively applied to the accumulation capacitors 16 and memory 26, in order to control the charge transfer current.

In addition, by analogy with FIG. 11, FIG. 12 includes diagrams representing the state of charge and voltage of the accumulation capacitors 16, and of storage 26, as well as the charge of the bus line. These charges are designated by the references Qι ₆ , Q _bus and Q ₂₆ . Part A of FIG. 12 corresponds to a step of addressing the storage element to which a signal charge Qiβ, accumulated in the accumulation capacitor 16 of the shooting element, must be transferred. The state of charge of the bus line is such that its voltage is equal to the threshold voltage of the addressing transistor of the storage element. This state of charge is obtained following an initialization cycle as described with reference to FIG. 11.

On this subject, it is observed that the control signal F _mem applied to the addressing transistor 22 is the same as that which is applied to this same transistor at the end of the initialization cycle (corresponding to parts B to E of FIG. 11 ).

Part B of FIG. 12 corresponds to a step of addressing a shooting element from which the signal charge Q ₁₆ must be transmitted. A closing control signal F _ai is applied to the gate of the transistor 12 of the shooting element in order to put it in a state in which this transistor can let current flow. The control level of the signal F _al is however adjusted so as to leave a potential barrier between the bus line 2 and the accumulation capacitor 16, which is sufficient to prevent the flow of a current from the bus line. 2 to this capacitor.

Part C of FIG. 12 corresponds to the transfer of the signal charge Qι ₆ , proper.

The variable potential F _C1 applied to the accumulation capacitor is increased according to a voltage ramp so that a current is established between this capacitor and the bus line.

This causes a flow of charges from the accumulation capacitor 16 of the recording element to the memory capacitor 26 of the storage element via the bus line 2 and the field effect transistors 12 and 22.

The slope of the voltage ramp applied to the accumulation capacitor 16 is preferably adjusted so that the potential of the bus remains at all times in the dynamic operating range of the transistors. This dynamic operating range is 0-3, 3V, or 0-5V for CMOS (Complementary Semiconductor Metal Oxide) type field effect transistors. Excessive potential of the bus line during the transient phase of the charge transfer would induce leakage currents to the substrate on which the components are made. Total load signal would not be retained during the transfer.

Thus, by controlling the voltage ramp applied to the accumulation capacitor, it is possible to carry out a charge transfer almost without losses on the bus line.

The losses by the Joule effect are in fact almost negligible during the transfer of charges.

Part D of Figure 12 corresponds to the end of the transfer. When the signal charge Qι ₆ is transferred to the memory capacitor 26, the control signal F _mem applied to the gate of the addressing transistor is such that it causes the blocking of the addressing transistor 22 which no longer lets through current. The memory capacitor 26 is then isolated from the bus line.

The charge stored in the memory capacitor 26 is now the sum of the charges Q ₂₆ + Qiβ. The state of charge of bus line 2, Q _bus . remains unchanged.

During a last step, shown in part E of FIG. 12, the control signal F _al applied to the transistor 12 of the shooting element is such that it causes the blocking of this transistor. The capacitors of the recording element, of the storage element and the bus line are then electrically isolated. A new addressing and a new bus line reset cycle can begin. Similarly, new charges corresponding to a shooting signal can be accumulated in the capacitor 16 of the shooting element. Table I below summarizes the switching states of the main switches or transistors during the different phases of a shooting cycle

(the switches not mentioned can occupy an indifferent state).

The table essentially comprises the phases corresponding to the bus line initialization cycle and to the charge transfer cycle to a storage element. The table also indicates phases corresponding to the output of a charge integrated in a shooting element or of a charge memorized in a memory element.

For reasons of simplification, the table only shows the references of the components. These references correspond to Figures 5, 11 and 12.

TABLE I

FIG. 13 appended shows the form of the control signals used during the bus line initialization, charge transfer and signal output operations. More precisely, FIG. 13 indicates in order the following main signals:

the signal F _ai applied to the initialization transistor 32 (part A),

- the potential F _cr applied to the initialization capacitor 36 (part B),

the signal F _al applied to transistor 12 of a shooting element (part C),

the potential F _ci applied to the accumulation capacitor 16 (part D), the signal F _mem applied to the addressing transistor 22 (part E),

- the signal Fi applied to the switch 27i (part F),

- the signal F _e applies to the switch 27e (part G),

- the voltage of bus line 2 (part H), and

- the potential F _cm applied to the memory capacitor 26 (part I).

Part J of figure 13 indicates the evolution of the charge accumulated in the memory capacitor

26. It varies from the value Q ₂₆ during the initialization phase to a value Q ₂ 6 + Qi6 after the transfer phase.

The transfer to the signal output circuit of the charges summed in a memory element

20 or possibly in the storage capacitor of a shooting element, is produced according to a principle identical to that set out above with reference to FIGS. 11, 12 and 13.

The transfer takes place in this case from the accumulation capacitor 16 or from the memory capacitor 26 to the output capacitor 46 visible in FIG. 5. A signal F _aeb makes _it possible to control the conduction state of the read transistor 42 and a variable voltage F _C eb. applied to the capacitor C _e , allows its potential to be controlled. The signal F _aeD and the voltage F _ceb are controlled in a manner comparable to the signals F _mem and F _cra , shown in FIG. 13, during a charge transfer from a shooting element to the element memorization.

FIG. 14 makes it possible to illustrate a charge transfer sequence in a shooting device which, for reasons of clarity, is only represented with four shooting elements, denoted Pi, P ₂ , P ₃ , P ₄ , corresponding to a shooting line, and four storage elements denoted M _l M ₂ , M ₃ , M ₄ . It is considered that a reference picture element reaching the shooting elements moves so as to be seen successively by the shooting elements Pi, P ₂ , P ₃ , then P ₄ . ''

It is observed that the charges accumulated in all of the shooting elements are transferred successively to the associated memory elements.

Firstly, corresponding to part A of FIG. 14, it is considered that a reference picture element I is located in front of the shooting element Pi. With this picture element I entering the matrix detection (formed by Pi, P ₂ , P ₃ and P ₄ ) is associated with a given storage element Mi. The address of the memory Mi associated with this picture element I remains invariant for the duration of its displacement in front of the line of sight.

The charges integrated in the shooting elements Pi to P ₄ are respectively transferred into the memories Mi to M ₄ . Thus, a first signal charge corresponding to the image element I is transferred to the associated memory Mi. It is noted that the content of the memory M _x was reset to zero before this charge transfer. The content of the memory element M ₄ is transferred to the signal output means 40.

Part B of FIG. 14 corresponds to a later time when the picture element I moved in front of the shooting element P ₂ . The charges integrated in the shooting elements Pi to P ₄ are now transferred respectively to the memory elements M ₄ , M, M ₂ and M ₃ . Thus a second signal charge corresponding to the image element I is added to the memory M _x .

The content of the memory M ₃ is transferred to the signal output means 40.

Parts C and D of FIG. 14 show the following steps in which the image element I is located successively in front of the shooting elements P ₃ and P, and during which the charges corresponding to the element of image I are always added in M _:.

When the picture element leaves the shooting line, all of the charges accumulated in the memory Mi during its passage in front of the shooting elements are transferred to the output means 40. This transfer is shown in part D of FIG. 14. The memory Mi is then initialized and ready to receive the signal charges corresponding to a new picture element J reaching the shooting line. This element is represented on part E of figure 14. It can be observed that part E of figure 14 corresponds to part A.

A transfer according to an identical scheme can be carried out for a large number of picture elements.

The selection of the shooting elements and the assignment of an address to a picture element are carried out by management logic circuits and by address decoder circuits.

Claims

1. Device for taking pictures comprising: - a plurality of elements (10) for taking pictures, capable of delivering signals in the form of electrical charges, - at least one storage element (20) capable of receiving signals in the form of charges, and - at least one signal output circuit (40), characterized in that it further comprises at least one connection element (2), for charge transfer, with floating potential, constituting a capacitor, and connecting together, a set of shooting elements, at least one storage element and at least one signal output circuit. 2. Device according to claim 1, in which the shooting elements comprise a generator (14) capable of delivering an electric current in response to the reception of photons, an integration capacitor (16) of said electric current and a transistor (12) connecting said capacitor to the connection element (2). 3. Device according to claim 1, characterized in that the shooting elements (10) comprise a depleted MOS structure. 4. Device according to claim 3, characterized in that the MOS structure is produced on a silicon substrate. 5. Device according to claim 1, characterized in that the current generator (14) of the shooting elements (10) comprises a photodiode or a photoconductor. 6. Device according to claim 1, comprising a plurality of connection elements metallic (2) in the form of bus lines, each connection element connecting a plurality of imaging elements (10), a plurality of storage elements (20) and a signal output means (40) . 7. Device according to claim 6, wherein the signal output circuit (40) is connected to a multiplexer circuit. 8. Device according to claim 1, further comprising for each connection element a circuit (30) said initialization, connected to said connection element. 9. Device according to claim 8, in which the initialization circuit comprises a capacitor (36) and a transistor (32), the transistor (32) being able to be activated to transfer an electric charge from the initialization capacitor to the element. of connection. 10. Device according to claim 1, in which each signal output circuit comprises a sample-and-hold circuit comprising a capacitor (46) for receiving signals in the form of electrical charges and a follower transistor stage capable of measuring and outputting the potential of the reception capacitor. 11. Device according to claim 10, in which each signal output circuit further comprises an anti-dazzle circuit. 12. Method for transferring an electrical charge from a first capacitor to a second capacitor, by means of an electrical connection element with floating potential constituting a third capacitor and connected to the second capacitor by a field effect transistor, in which: an initialization load is applied to the electrical connection element to fix an electrical initialization potential of the connection element at a value substantially equal to a threshold voltage of the field effect transistor, and greater than a charge potential of the second capacitor and then - the first capacitor, brought to a potential greater than the initialization potential, is connected to the connection element to cause a flow of charges from the first capacitor to the connection element and from the connection element to the second capacitor .