WO1999029074A1 - Circuit for generating a modulated signal - Google Patents

Abstract

The invention relates to a circuit for generating a signal (OUT) that is modulated depending on the digital data (DATA) to be transmitted using a predetermined modulation method. Said circuit comprises a frequency generator circuit (10) with modulation capability and a control circuit (16) with a modulation memory (20) containing a modulation table having more than two entries. The control circuit (16) is designed to access the modulation memory (20) depending on the digital data (DATA) to be transferred in order to generate the digital modulation signal (MOD). Such a circuit requires few components and can be flexibly used in different modulation methods.

Description

description

Circuit for generating a modulated signal

The invention relates to a circuit for generating a signal which is modulated as a function of digital data to be transmitted in accordance with a predetermined modulation method. This circuit can be used in all transmitters for digital signals. In particular, use in mobile devices such as, for example, radio telephones or cordless telephones is provided.

From the data sheet "CMOS DDS Modulator AD7008" from Analog Devices, Norwood, USA, 1995, it is known to add a frequency generator circuit designed as a digital synthesis circuit (DDS = direct digital synthesizing) using digital I, Q and phase modulation signals modulate. The data sheet also discloses to optionally apply the contents of two frequency registers to an accumulator of the digital synthesis circuit. In this way, an output signal can be generated which is frequency-modulated as a function of a data stream to be transmitted using a frequency shift keying method (FSK = frequency shift keying).

However, the circuits specified in the data sheet mentioned are only intended for a few special modulation methods. Suitable control circuits must be provided for other modulation methods for transmitting digital data, in particular for complex or narrow-tolerance methods. The data sheet does not provide any information on this.

Accordingly, the object of the invention is to provide a circuit for generating a modulated signal which can be used flexibly for many different modulation methods with little component complexity. In particular, the circuit should have a modulated signal with low tolerance generate, as is required in modern, powerful modulation methods.

According to the invention, this object is achieved by a circuit having the features of claim 1. The dependent claims relate to preferred embodiments of the invention.

The invention is based on the basic idea that, in the case of modulation methods for digital data values, the modulation signal shapes are precisely defined as a function of the data to be transmitted. These required signal curves can therefore be calculated in advance and stored in a modulation table. In order to generate these prescribed signal forms, the invention provides a control circuit which accesses the modulation table and generates a suitable digital modulation signal.

The circuit according to the invention is suitable for modern modulation methods such as the GMSK method (Gauss minimum shift keying) used in the GSM standard or the DPSK method (differential phase shift keying). It requires little hardware, since the modulation values can be calculated in advance for all configurations that occur. The mere storage of a sufficient number of support points of the modulation curves is not complex. Nevertheless, high accuracy can be achieved.

In the sense used here, a signal is understood to be any signal or signal bundle from which digital values can be derived. For example, a digital signal can have a plurality of partial signals which are each transmitted on one line of a parallel data transmission path. Each partial signal then defines a bit of a digital data word at any point in time.

Any signal that has properties of an output signal of a frequency generator circuit influences or sets. In particular, such properties are the frequency and / or a frequency offset and / or a phase position of the output signal. The modulation signal can contain information about a basic or carrier frequency of the output signal and, in extreme cases, completely define the frequency of the output signal. In other embodiments, the modulation signal can only determine a frequency shift of the output signal.

The frequency generator circuit can be configured differently in different exemplary embodiments of the invention. For example, a direct fine stage synthesizer can be used as the frequency generator circuit. It is also possible to use a digital synthesis circuit, such as is contained in the module AD7008 from Analog Devices mentioned at the beginning. As a rule, the output signal of such a circuit must be filtered and, if necessary, mixed up. In preferred embodiments, the frequency generator circuit is designed as a reciprocal digital synthesis circuit. Such a circuit is based on the basic idea of connecting a controlled oscillator to a reference oscillator by means of a digital synthesis circuit, the controlled oscillator being traced via a phase comparison circuit.

In preferred exemplary embodiments of the invention, the modulation memory is addressed as a function of at least one data bit currently to be transmitted and / or of a context of this data bit and / or of oversampling information and / or of carrier frequency information and / or of channel information and / or of band information. A context of a data bit is preferably a range of subsequent and / or previous bits in the digital data to be transmitted. If, in addition to the data bit to be transmitted, one or more of the above information is used to determine the modulation signal, be drawn, a very accurate output signal can be generated.

Preferably, oversampling is carried out in such a way that the modulation signal is updated several times for each data bit to be transmitted and, if necessary, changed. The modulation signal can have several components which can be used for frequency modulation and / or for amplitude modulation of the generated signal. The amplitude of the generated signal is preferably determined by an output stage as a function of a component of the modulation signal.

Several exemplary embodiments and alternative embodiments of the invention are explained in more detail below with reference to the schematic drawings. They represent:

1 is a block diagram of a first embodiment of the invention,

2 shows an exemplary representation of a modulation signal curve,

3 shows a more detailed block diagram of the drive circuit shown in FIG. 1,

Fig. 4 shows an alternative embodiment of the drive circuit shown in Fig. 3, and

Fig. 5 is a block diagram of a second embodiment of the invention.

In the circuit shown in FIG. 1, a frequency generator circuit 10 has an input 12 for a digital carrier frequency signal CF and an input 14 for a digital modulation signal MOD. The frequency generator circuit 10 generates an output signal OUT, the fundamental or carrier frequency of which is determined by the carrier frequency signal CF. The Modulation signal MOD determines a frequency shift with respect to the carrier frequency. Frequency modulation and, due to brief frequency shifts, phase modulation of the output signal OUT is thus possible.

The modulation signal MOD is generated by a control circuit 16 which has an input 18 for digital data to be transmitted DATA and a modulation memory 20 _. a modulation table. The structure of the drive circuit 16 will be described in more detail later. In the exemplary embodiment described here, the input 18 has a width of one bit, and the digital data DATA to be transmitted are read in at a clock rate of 271 kbit / s. The modulation signal MOD has a width of 12 bits and is transmitted to the frequency generator circuit 10 via a corresponding number of parallel lines. The update rate of the modulation signal MOD is higher by a factor of 8 or 16 than the bit clock of the input data and is, for example, 2.17 MWort / s or 4.34 MWort / s. In alternative embodiments, different word widths, different clock rates and / or different clock ratios are provided.

In the exemplary embodiment described here, the frequency generator circuit 10 is designed as a reciprocal digital synthesis circuit. It has an adder 22, a digital synthesis circuit 24, a reference oscillator 26, a phase comparison circuit 28, a low-pass filter 30 and a voltage-controlled oscillator 32.

The adder 22 forms the sum of the carrier frequency signal CF and the digital modulation signal MOD and supplies them as an add value signal ADD to an add value input of the digital synthesis circuit 24. The digital synthesis circuit 24 is known per se and is contained, for example, in the module AD7008 mentioned at the beginning. It has an accumulator, the counter reading of which is increased by the addition value for each clock cycle applied to a clock input 34. The counting The range of the accumulator is thus periodically traversed at a frequency that is directly proportional to the clock frequency and the add value (and inversely proportional to the counting range). The digital synthesis circuit 24 generates a triangular, sine or rectangular synthesis signal SYN, the period of which corresponds to a complete run through the accumulator counting range.

The reference oscillator 26 generates a reference signal REF with a predetermined frequency, which is for example 13 MHz. The phase comparison circuit 28 compares the phase positions of the two signals SYN and REF and generates an analog tuning signal TUNE, which is present via the low-pass filter 30 at an A voice input of the voltage-controlled oscillator 32. The oscillator 32 generates a sinusoidal oscillator signal OSC, which on the one hand serves as a modulated output signal OUT of the entire circuit and on the other hand (via a clock form circuit not shown in FIG. 1) is applied to the clock input 34 of the digital synthesis circuit 24. The output signal OUT can, for example, have a frequency of 900 MHz and a high spectral purity, so that it can be passed directly to a transmission output stage of a mobile telephone.

Overall, in the circuit according to FIG. 1, the voltage-controlled oscillator 32 is tracked in the manner of a PLL loop (phase locked loop) in such a way that the frequencies of the signals SYN and REF match. The digital synthesis circuit 24 acts as a frequency divider, the frequency division factor of which can be set by means of the addition value input. For further details on the frequency generator circuit 10, reference is made to the German patent applications with the file numbers 197 39 757.3 and 197 40 196.1 by the same inventor. In alternative embodiments, the frequency generator circuit 10 is configured differently, for example as a fine-stage synthesizer. The curve shape shown by way of example in FIG. 2 corresponds to the value of the modulation signal MOD for a possible sequence of input data DATA for a given modulation method. Since it is digital input data DATA, the modulation curve shape to be generated is precisely defined and can be calculated in advance. In particular, support points of the modulation curve (represented by dots in FIG. 2) can be calculated at predetermined sampling times (indicated by arrows in FIG. 2). These precalculated reference points or sampling values are stored in the entries in the modulation table and are selected according to suitable criteria and are applied to the frequency generator circuit 10 as a modulation signal MOD.

In the embodiment of the control circuit 16 shown in FIG. 3, the modulation memory 20 is designed as a read-only memory (ROM) and the entries in the modulation table are data words of this read-only memory. These data words serve directly as modulation signal MOD. The modulation table has 128 entries, for the selection of which seven address connections of the modulation memory 20 are provided. A shift register 36 receives the digital data DATA to be transmitted at the input 18. Four parallel outputs of the shift register 36 are connected to four address connections of the modulation memory 20. The data bit currently to be sent and a context of this data bit, which here consists of the three preceding bits, are thus present as addresses on the modulation memory 20.

The three remaining address lines of the modulation memory 20 are connected to a three-bit wide binary counter 38 which is clocked at eight times the frequency of the shift register 36. For each data bit to be transmitted, the binary counter 38 therefore goes through all eight states, and the modulation signal MOD is accordingly updated eight times. The binary counter 38 thus represents oversampling Information ready to allow oversampling of the data bits DATA.

In alternative embodiments of the circuit shown in FIG. 3, a different context of the data bit currently to be transmitted is used. A lower or higher oversampling rate, for example 16 times, can also be selected. The modulation signal MOD can also be determined as a function of further information, as is shown in the embodiment variant according to FIG. 4. Here are additional

Information about the carrier frequency and the modulation method used.

A four-bit wide latch 40 is provided in the circuit according to FIG. 4 in order to store a frequency band signal CF ¹ derived from the carrier frequency signal CF with each carrier frequency or channel change and to apply it to further address inputs of the modulation memory 20. This information is only required if a frequency generator circuit 10 is used, the modulation deviation of which depends on the carrier frequency. This is the case with a reciprocal digital synthesis circuit because the addition of signals CF and MOD in adder 22 reduces the relative influence of a change in modulation signal MOD with increasing carrier frequency. This influence is taken into account in the entries in the modulation memory 20. If there is enough space available, each frequency channel can be treated separately. Generally, however, several adjacent frequency channels will be combined to form a group or a frequency band. Each value of the frequency band signal CF 'corresponds to such a group.

In the circuit according to FIG. 4, the modulation memory 20 also receives a modulation type signal TYPE, which is used to switch between several modulation methods. For example, you can switch between modulation methods for GSM and CDMA. It may be necessary to ta _k t of transmitted digital data DATA and / or the Überab- sampling rate and / or other circuit Para eter (for example, as determined by the cutoff frequency of the low-pass filter 30 loop bandwidth of the PLL control loop) set according to the modulation tionsartsignal TYPE or the modulation method .

In the alternative embodiments described so far, the modulation memory 20 was designed as a read-only memory. The content of this memory can either be specified for a device series or individually programmed for each device. In the second case, device-dependent errors or variations can be taken into account when calculating the entries in the modulation table, so that to some extent an adjustment is possible. If the modulation memory 20 is designed as an erasable and programmable read-only memory (for example as a flash EPROM), such an adjustment can also be carried out during maintenance of the device.

Further alternative embodiments provide for reprogramming the modulation memory 20 during the operation of the device in order to set different modulation methods, for example. Here, the modulation memory 20 only needs to contain the entries for a single modulation method. The modulation memory 20 can be designed as a random access memory (RAM).

The embodiment of the invention shown in FIG. 5 is based on the circuit of FIG. 1. However, several mutually independent changes have been made. First, according to FIG. 5, the digital synthesis circuit 24 has a prescaler 42. This prescaler 42 reduces the frequency in the PLL control loop, which reduces the energy consumption of the individual components.

As a second change compared to the circuit of FIG. 1, an output stage 44 is provided in FIG. 5 which contains the oscillator signal OSC amplified to the output signal OUT. The output signal OUT is sent directly (possibly via a suitable filter and / or a switch) to an antenna. Since the output stage 44 in turn can cause phase errors (for example when the supply voltage decreases), the input signal for the digital synthesis circuit 24 is derived from the output signal OUT. For this purpose, a suitable clock form circuit, not shown in FIG. 5, is used, which can be designed as a limiting amplifier.

Thirdly, according to FIG. 5, the modulation signal MOD is expanded by a component MOD 'which gives information about the amplitude of the signal OUT to be generated. Each entry in the modulation memory 20 is supplemented by this amplitude information, which can be eight bits wide, for example. Such an expansion is possible for all the configurations of the control circuit 16 described above. The component MOD ^{1 of} the modulation signal MOD is applied to a digital-to-analog converter 48 via an input 46 of the frequency generator circuit 20. The latter generates an analog control signal AM for the output stage 44. The output stage 44 controls the amplitude of the generated signal OUT in accordance with the level of the control signal AM.

5, which can also be provided accordingly in the circuit according to FIG. 1, enables precise frequency and amplitude modulation according to a predetermined modulation method. For example, a (multi-stage) quadrature amplitude modulation can be carried out. Furthermore, the amplitude information can be used to compensate for non-linearities of the output stage 44.

In a further embodiment alternative, a control circuit 16 according to FIG. 4 is used in the circuit according to FIG. 5. In this case, the amplitude information can also be addressed depending on the channel in order to compensate, for example, the frequency response of filters after the output stage 44. However, it is also possible to save memory space by dividing the modulation memory 20 into two separately addressable areas for the frequency and the amplitude information. The frequency band signal CF 'then need not be used to address the amplitude information.

Claims

claims 1. A circuit for generating a signal (OUT) which is modulated as a function of digital data (DATA) to be transmitted according to a predetermined modulation method, comprising: a frequency generator circuit (10) with a modulation input (14, 46) for a digital modulation signal (MOD) , and a control circuit (16) connected to the modulation input (14, 46) with an input (18) for the digital data to be transmitted (DATA) and with a modulation memory (20) which has a modulation table with more than two entries, wherein the control circuit (16) is set up to access the modulation memory (20) as a function of the digital data (DATA) to be transmitted in order to generate the digital modulation signal (MOD). 2. Circuit according to claim 1, characterized in that the control circuit (16) is set up to address the modulation memory (20) as a function of at least one data bit currently to be transmitted and / or of a context of this data bit. 3. A circuit according to claim 1 or 2, characterized in that a shift register (36) is provided in order to determine the context of the data bit currently to be transmitted and to provide it for addressing the modulation memory (20). 4. Circuit according to one of claims 1 to 3, characterized in that the digital modulation signal (MOD) is updated in shorter time intervals than the digital data to be transmitted (DATA). 5. Circuit according to one of claims 1 to 4, characterized in that the control circuit (16) is set up to address the modulation memory (20) as a function of oversampling information. 6. Circuit according to claim 5, characterized by a binary counter (38) for providing the oversampling information. 7. Circuit according to one of claims 1 to 6, characterized in that the control circuit (16) is set up to the modulation memory (20) in dependence on a carrier frequency and / or channel and / or band information (CF, CF ') to address. 8. Circuit according to one of claims 1 to 7, characterized in that the modulation signal (MOD) is used for frequency modulation and / or for amplitude modulation of the generated signal (OUT). 9. Circuit according to one of claims 1 to 8, characterized in that the frequency generator circuit (10) is a reciprocal digital synthesis circuit with an oscillator (32), the frequency of which is at least partially influenced by the modulation signal (MOD). 10. Circuit according to one of claims 1 to 9, characterized in that the frequency generator circuit (10) has an output stage (44), and that the amplitude of the generated signal (OUT) is at least partially influenced by the modulation signal (MOD).